iio: st_sensors: Fix indio_dev->trig assignment
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / iio / dac / ad5064.c
CommitLineData
fcf265d6 1/*
6a17a076
LPC
2 * AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1, AD5065, AD5628, AD5629R,
3 * AD5648, AD5666, AD5668, AD5669R Digital to analog converters driver
fcf265d6
LPC
4 *
5 * Copyright 2011 Analog Devices Inc.
6 *
7 * Licensed under the GPL-2.
8 */
9
10#include <linux/device.h>
11#include <linux/err.h>
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/spi/spi.h>
6a17a076 15#include <linux/i2c.h>
fcf265d6
LPC
16#include <linux/slab.h>
17#include <linux/sysfs.h>
18#include <linux/regulator/consumer.h>
6a17a076 19#include <asm/unaligned.h>
fcf265d6 20
06458e27
JC
21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
fcf265d6 23
bb92ff3e 24#define AD5064_MAX_DAC_CHANNELS 8
83c169d5 25#define AD5064_MAX_VREFS 4
fcf265d6
LPC
26
27#define AD5064_ADDR(x) ((x) << 20)
28#define AD5064_CMD(x) ((x) << 24)
29
fcf265d6
LPC
30#define AD5064_ADDR_ALL_DAC 0xF
31
32#define AD5064_CMD_WRITE_INPUT_N 0x0
33#define AD5064_CMD_UPDATE_DAC_N 0x1
34#define AD5064_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2
35#define AD5064_CMD_WRITE_INPUT_N_UPDATE_N 0x3
36#define AD5064_CMD_POWERDOWN_DAC 0x4
37#define AD5064_CMD_CLEAR 0x5
38#define AD5064_CMD_LDAC_MASK 0x6
39#define AD5064_CMD_RESET 0x7
bb92ff3e
LPC
40#define AD5064_CMD_CONFIG 0x8
41
42#define AD5064_CONFIG_DAISY_CHAIN_ENABLE BIT(1)
43#define AD5064_CONFIG_INT_VREF_ENABLE BIT(0)
fcf265d6
LPC
44
45#define AD5064_LDAC_PWRDN_NONE 0x0
46#define AD5064_LDAC_PWRDN_1K 0x1
47#define AD5064_LDAC_PWRDN_100K 0x2
48#define AD5064_LDAC_PWRDN_3STATE 0x3
49
50/**
51 * struct ad5064_chip_info - chip specific information
52 * @shared_vref: whether the vref supply is shared between channels
bb92ff3e
LPC
53 * @internal_vref: internal reference voltage. 0 if the chip has no internal
54 * vref.
fcf265d6 55 * @channel: channel specification
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LPC
56 * @num_channels: number of channels
57 */
fcf265d6
LPC
58
59struct ad5064_chip_info {
60 bool shared_vref;
bb92ff3e 61 unsigned long internal_vref;
83c169d5
LPC
62 const struct iio_chan_spec *channels;
63 unsigned int num_channels;
fcf265d6
LPC
64};
65
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LPC
66struct ad5064_state;
67
68typedef int (*ad5064_write_func)(struct ad5064_state *st, unsigned int cmd,
69 unsigned int addr, unsigned int val);
70
fcf265d6
LPC
71/**
72 * struct ad5064_state - driver instance specific data
6a17a076 73 * @dev: the device for this driver instance
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LPC
74 * @chip_info: chip model specific constants, available modes etc
75 * @vref_reg: vref supply regulators
76 * @pwr_down: whether channel is powered down
77 * @pwr_down_mode: channel's current power down mode
78 * @dac_cache: current DAC raw value (chip does not support readback)
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LPC
79 * @use_internal_vref: set to true if the internal reference voltage should be
80 * used.
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81 * @write: register write callback
82 * @data: i2c/spi transfer buffers
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LPC
83 */
84
85struct ad5064_state {
6a17a076 86 struct device *dev;
fcf265d6 87 const struct ad5064_chip_info *chip_info;
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LPC
88 struct regulator_bulk_data vref_reg[AD5064_MAX_VREFS];
89 bool pwr_down[AD5064_MAX_DAC_CHANNELS];
90 u8 pwr_down_mode[AD5064_MAX_DAC_CHANNELS];
91 unsigned int dac_cache[AD5064_MAX_DAC_CHANNELS];
bb92ff3e 92 bool use_internal_vref;
fcf265d6 93
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LPC
94 ad5064_write_func write;
95
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96 /*
97 * DMA (thus cache coherency maintenance) requires the
98 * transfer buffers to live in their own cache lines.
99 */
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LPC
100 union {
101 u8 i2c[3];
102 __be32 spi;
103 } data ____cacheline_aligned;
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LPC
104};
105
106enum ad5064_type {
107 ID_AD5024,
f8be4af1 108 ID_AD5025,
fcf265d6 109 ID_AD5044,
f8be4af1 110 ID_AD5045,
fcf265d6
LPC
111 ID_AD5064,
112 ID_AD5064_1,
f8be4af1 113 ID_AD5065,
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LPC
114 ID_AD5628_1,
115 ID_AD5628_2,
116 ID_AD5648_1,
117 ID_AD5648_2,
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LPC
118 ID_AD5666_1,
119 ID_AD5666_2,
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120 ID_AD5668_1,
121 ID_AD5668_2,
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LPC
122};
123
6a17a076 124static int ad5064_write(struct ad5064_state *st, unsigned int cmd,
fcf265d6
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125 unsigned int addr, unsigned int val, unsigned int shift)
126{
127 val <<= shift;
128
6a17a076 129 return st->write(st, cmd, addr, val);
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130}
131
132static int ad5064_sync_powerdown_mode(struct ad5064_state *st,
a2630262 133 const struct iio_chan_spec *chan)
fcf265d6
LPC
134{
135 unsigned int val;
136 int ret;
137
a2630262 138 val = (0x1 << chan->address);
fcf265d6 139
a2630262
LPC
140 if (st->pwr_down[chan->channel])
141 val |= st->pwr_down_mode[chan->channel] << 8;
fcf265d6 142
6a17a076 143 ret = ad5064_write(st, AD5064_CMD_POWERDOWN_DAC, 0, val, 0);
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LPC
144
145 return ret;
146}
147
26628f6b
LPC
148static const char * const ad5064_powerdown_modes[] = {
149 "1kohm_to_gnd",
150 "100kohm_to_gnd",
151 "three_state",
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LPC
152};
153
26628f6b
LPC
154static int ad5064_get_powerdown_mode(struct iio_dev *indio_dev,
155 const struct iio_chan_spec *chan)
fcf265d6 156{
fcf265d6
LPC
157 struct ad5064_state *st = iio_priv(indio_dev);
158
26628f6b 159 return st->pwr_down_mode[chan->channel] - 1;
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LPC
160}
161
26628f6b
LPC
162static int ad5064_set_powerdown_mode(struct iio_dev *indio_dev,
163 const struct iio_chan_spec *chan, unsigned int mode)
fcf265d6 164{
fcf265d6 165 struct ad5064_state *st = iio_priv(indio_dev);
fcf265d6
LPC
166 int ret;
167
fcf265d6 168 mutex_lock(&indio_dev->mlock);
26628f6b 169 st->pwr_down_mode[chan->channel] = mode + 1;
fcf265d6 170
a2630262 171 ret = ad5064_sync_powerdown_mode(st, chan);
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LPC
172 mutex_unlock(&indio_dev->mlock);
173
26628f6b 174 return ret;
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175}
176
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LPC
177static const struct iio_enum ad5064_powerdown_mode_enum = {
178 .items = ad5064_powerdown_modes,
179 .num_items = ARRAY_SIZE(ad5064_powerdown_modes),
180 .get = ad5064_get_powerdown_mode,
181 .set = ad5064_set_powerdown_mode,
182};
183
1d0d8794 184static ssize_t ad5064_read_dac_powerdown(struct iio_dev *indio_dev,
fc6d1139 185 uintptr_t private, const struct iio_chan_spec *chan, char *buf)
fcf265d6 186{
fcf265d6 187 struct ad5064_state *st = iio_priv(indio_dev);
fcf265d6 188
1d0d8794 189 return sprintf(buf, "%d\n", st->pwr_down[chan->channel]);
fcf265d6
LPC
190}
191
1d0d8794 192static ssize_t ad5064_write_dac_powerdown(struct iio_dev *indio_dev,
fc6d1139
MH
193 uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
194 size_t len)
fcf265d6 195{
fcf265d6 196 struct ad5064_state *st = iio_priv(indio_dev);
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LPC
197 bool pwr_down;
198 int ret;
199
200 ret = strtobool(buf, &pwr_down);
201 if (ret)
202 return ret;
203
204 mutex_lock(&indio_dev->mlock);
1d0d8794 205 st->pwr_down[chan->channel] = pwr_down;
fcf265d6 206
a2630262 207 ret = ad5064_sync_powerdown_mode(st, chan);
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208 mutex_unlock(&indio_dev->mlock);
209 return ret ? ret : len;
210}
211
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LPC
212static int ad5064_get_vref(struct ad5064_state *st,
213 struct iio_chan_spec const *chan)
214{
215 unsigned int i;
216
217 if (st->use_internal_vref)
218 return st->chip_info->internal_vref;
219
220 i = st->chip_info->shared_vref ? 0 : chan->channel;
221 return regulator_get_voltage(st->vref_reg[i].consumer);
222}
223
fcf265d6
LPC
224static int ad5064_read_raw(struct iio_dev *indio_dev,
225 struct iio_chan_spec const *chan,
226 int *val,
227 int *val2,
228 long m)
229{
230 struct ad5064_state *st = iio_priv(indio_dev);
23a3b8cc 231 int scale_uv;
fcf265d6
LPC
232
233 switch (m) {
09f4eb40 234 case IIO_CHAN_INFO_RAW:
fcf265d6
LPC
235 *val = st->dac_cache[chan->channel];
236 return IIO_VAL_INT;
c8a9f805 237 case IIO_CHAN_INFO_SCALE:
bb92ff3e 238 scale_uv = ad5064_get_vref(st, chan);
fcf265d6
LPC
239 if (scale_uv < 0)
240 return scale_uv;
241
242 scale_uv = (scale_uv * 100) >> chan->scan_type.realbits;
243 *val = scale_uv / 100000;
244 *val2 = (scale_uv % 100000) * 10;
245 return IIO_VAL_INT_PLUS_MICRO;
246 default:
247 break;
248 }
249 return -EINVAL;
250}
251
252static int ad5064_write_raw(struct iio_dev *indio_dev,
253 struct iio_chan_spec const *chan, int val, int val2, long mask)
254{
255 struct ad5064_state *st = iio_priv(indio_dev);
256 int ret;
257
258 switch (mask) {
09f4eb40 259 case IIO_CHAN_INFO_RAW:
c5ef717a 260 if (val >= (1 << chan->scan_type.realbits) || val < 0)
fcf265d6
LPC
261 return -EINVAL;
262
263 mutex_lock(&indio_dev->mlock);
6a17a076 264 ret = ad5064_write(st, AD5064_CMD_WRITE_INPUT_N_UPDATE_N,
fcf265d6
LPC
265 chan->address, val, chan->scan_type.shift);
266 if (ret == 0)
267 st->dac_cache[chan->channel] = val;
268 mutex_unlock(&indio_dev->mlock);
269 break;
270 default:
271 ret = -EINVAL;
272 }
273
274 return ret;
275}
276
277static const struct iio_info ad5064_info = {
278 .read_raw = ad5064_read_raw,
279 .write_raw = ad5064_write_raw,
fcf265d6
LPC
280 .driver_module = THIS_MODULE,
281};
282
26628f6b 283static const struct iio_chan_spec_ext_info ad5064_ext_info[] = {
1d0d8794
LPC
284 {
285 .name = "powerdown",
286 .read = ad5064_read_dac_powerdown,
287 .write = ad5064_write_dac_powerdown,
288 },
26628f6b
LPC
289 IIO_ENUM("powerdown_mode", false, &ad5064_powerdown_mode_enum),
290 IIO_ENUM_AVAILABLE("powerdown_mode", &ad5064_powerdown_mode_enum),
1d0d8794
LPC
291 { },
292};
293
a2630262 294#define AD5064_CHANNEL(chan, addr, bits) { \
1d0d8794
LPC
295 .type = IIO_VOLTAGE, \
296 .indexed = 1, \
297 .output = 1, \
298 .channel = (chan), \
20a0eddd
JC
299 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
300 BIT(IIO_CHAN_INFO_SCALE), \
a2630262 301 .address = addr, \
1d0d8794
LPC
302 .scan_type = IIO_ST('u', (bits), 16, 20 - (bits)), \
303 .ext_info = ad5064_ext_info, \
304}
305
83c169d5
LPC
306#define DECLARE_AD5064_CHANNELS(name, bits) \
307const struct iio_chan_spec name[] = { \
a2630262
LPC
308 AD5064_CHANNEL(0, 0, bits), \
309 AD5064_CHANNEL(1, 1, bits), \
310 AD5064_CHANNEL(2, 2, bits), \
311 AD5064_CHANNEL(3, 3, bits), \
312 AD5064_CHANNEL(4, 4, bits), \
313 AD5064_CHANNEL(5, 5, bits), \
314 AD5064_CHANNEL(6, 6, bits), \
315 AD5064_CHANNEL(7, 7, bits), \
316}
317
318#define DECLARE_AD5065_CHANNELS(name, bits) \
319const struct iio_chan_spec name[] = { \
320 AD5064_CHANNEL(0, 0, bits), \
321 AD5064_CHANNEL(1, 3, bits), \
83c169d5
LPC
322}
323
324static DECLARE_AD5064_CHANNELS(ad5024_channels, 12);
325static DECLARE_AD5064_CHANNELS(ad5044_channels, 14);
326static DECLARE_AD5064_CHANNELS(ad5064_channels, 16);
327
a2630262
LPC
328static DECLARE_AD5065_CHANNELS(ad5025_channels, 12);
329static DECLARE_AD5065_CHANNELS(ad5045_channels, 14);
330static DECLARE_AD5065_CHANNELS(ad5065_channels, 16);
331
1d0d8794
LPC
332static const struct ad5064_chip_info ad5064_chip_info_tbl[] = {
333 [ID_AD5024] = {
334 .shared_vref = false,
83c169d5
LPC
335 .channels = ad5024_channels,
336 .num_channels = 4,
1d0d8794 337 },
f8be4af1
LPC
338 [ID_AD5025] = {
339 .shared_vref = false,
a2630262 340 .channels = ad5025_channels,
f8be4af1
LPC
341 .num_channels = 2,
342 },
1d0d8794
LPC
343 [ID_AD5044] = {
344 .shared_vref = false,
83c169d5
LPC
345 .channels = ad5044_channels,
346 .num_channels = 4,
1d0d8794 347 },
f8be4af1
LPC
348 [ID_AD5045] = {
349 .shared_vref = false,
a2630262 350 .channels = ad5045_channels,
f8be4af1
LPC
351 .num_channels = 2,
352 },
1d0d8794
LPC
353 [ID_AD5064] = {
354 .shared_vref = false,
83c169d5
LPC
355 .channels = ad5064_channels,
356 .num_channels = 4,
1d0d8794
LPC
357 },
358 [ID_AD5064_1] = {
359 .shared_vref = true,
83c169d5
LPC
360 .channels = ad5064_channels,
361 .num_channels = 4,
1d0d8794 362 },
f8be4af1
LPC
363 [ID_AD5065] = {
364 .shared_vref = false,
a2630262 365 .channels = ad5065_channels,
f8be4af1
LPC
366 .num_channels = 2,
367 },
bb92ff3e
LPC
368 [ID_AD5628_1] = {
369 .shared_vref = true,
370 .internal_vref = 2500000,
371 .channels = ad5024_channels,
372 .num_channels = 8,
373 },
374 [ID_AD5628_2] = {
375 .shared_vref = true,
376 .internal_vref = 5000000,
377 .channels = ad5024_channels,
378 .num_channels = 8,
379 },
380 [ID_AD5648_1] = {
381 .shared_vref = true,
382 .internal_vref = 2500000,
383 .channels = ad5044_channels,
384 .num_channels = 8,
385 },
386 [ID_AD5648_2] = {
387 .shared_vref = true,
388 .internal_vref = 5000000,
389 .channels = ad5044_channels,
390 .num_channels = 8,
391 },
64f4eaa5
LPC
392 [ID_AD5666_1] = {
393 .shared_vref = true,
394 .internal_vref = 2500000,
395 .channels = ad5064_channels,
396 .num_channels = 4,
397 },
398 [ID_AD5666_2] = {
399 .shared_vref = true,
400 .internal_vref = 5000000,
401 .channels = ad5064_channels,
402 .num_channels = 4,
403 },
bb92ff3e
LPC
404 [ID_AD5668_1] = {
405 .shared_vref = true,
406 .internal_vref = 2500000,
407 .channels = ad5064_channels,
408 .num_channels = 8,
409 },
410 [ID_AD5668_2] = {
411 .shared_vref = true,
412 .internal_vref = 5000000,
413 .channels = ad5064_channels,
414 .num_channels = 8,
415 },
1d0d8794
LPC
416};
417
fcf265d6
LPC
418static inline unsigned int ad5064_num_vref(struct ad5064_state *st)
419{
83c169d5 420 return st->chip_info->shared_vref ? 1 : st->chip_info->num_channels;
fcf265d6
LPC
421}
422
423static const char * const ad5064_vref_names[] = {
424 "vrefA",
425 "vrefB",
426 "vrefC",
427 "vrefD",
428};
429
430static const char * const ad5064_vref_name(struct ad5064_state *st,
431 unsigned int vref)
432{
433 return st->chip_info->shared_vref ? "vref" : ad5064_vref_names[vref];
434}
435
fc52692c
GKH
436static int ad5064_probe(struct device *dev, enum ad5064_type type,
437 const char *name, ad5064_write_func write)
fcf265d6 438{
fcf265d6
LPC
439 struct iio_dev *indio_dev;
440 struct ad5064_state *st;
f77ae9d8 441 unsigned int midscale;
fcf265d6
LPC
442 unsigned int i;
443 int ret;
444
7cbb7537 445 indio_dev = iio_device_alloc(sizeof(*st));
fcf265d6
LPC
446 if (indio_dev == NULL)
447 return -ENOMEM;
448
449 st = iio_priv(indio_dev);
6a17a076 450 dev_set_drvdata(dev, indio_dev);
fcf265d6
LPC
451
452 st->chip_info = &ad5064_chip_info_tbl[type];
6a17a076
LPC
453 st->dev = dev;
454 st->write = write;
fcf265d6
LPC
455
456 for (i = 0; i < ad5064_num_vref(st); ++i)
457 st->vref_reg[i].supply = ad5064_vref_name(st, i);
458
6a17a076 459 ret = regulator_bulk_get(dev, ad5064_num_vref(st),
fcf265d6 460 st->vref_reg);
bb92ff3e
LPC
461 if (ret) {
462 if (!st->chip_info->internal_vref)
463 goto error_free;
464 st->use_internal_vref = true;
6a17a076 465 ret = ad5064_write(st, AD5064_CMD_CONFIG, 0,
bb92ff3e
LPC
466 AD5064_CONFIG_INT_VREF_ENABLE, 0);
467 if (ret) {
6a17a076 468 dev_err(dev, "Failed to enable internal vref: %d\n",
bb92ff3e
LPC
469 ret);
470 goto error_free;
471 }
472 } else {
473 ret = regulator_bulk_enable(ad5064_num_vref(st), st->vref_reg);
474 if (ret)
475 goto error_free_reg;
476 }
fcf265d6 477
6a17a076
LPC
478 indio_dev->dev.parent = dev;
479 indio_dev->name = name;
fcf265d6
LPC
480 indio_dev->info = &ad5064_info;
481 indio_dev->modes = INDIO_DIRECT_MODE;
83c169d5
LPC
482 indio_dev->channels = st->chip_info->channels;
483 indio_dev->num_channels = st->chip_info->num_channels;
fcf265d6 484
f77ae9d8
LPC
485 midscale = (1 << indio_dev->channels[0].scan_type.realbits) / 2;
486
487 for (i = 0; i < st->chip_info->num_channels; ++i) {
488 st->pwr_down_mode[i] = AD5064_LDAC_PWRDN_1K;
489 st->dac_cache[i] = midscale;
490 }
491
fcf265d6
LPC
492 ret = iio_device_register(indio_dev);
493 if (ret)
494 goto error_disable_reg;
495
496 return 0;
497
498error_disable_reg:
bb92ff3e
LPC
499 if (!st->use_internal_vref)
500 regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
fcf265d6 501error_free_reg:
bb92ff3e
LPC
502 if (!st->use_internal_vref)
503 regulator_bulk_free(ad5064_num_vref(st), st->vref_reg);
fcf265d6 504error_free:
7cbb7537 505 iio_device_free(indio_dev);
fcf265d6
LPC
506
507 return ret;
508}
509
fc52692c 510static int ad5064_remove(struct device *dev)
fcf265d6 511{
6a17a076 512 struct iio_dev *indio_dev = dev_get_drvdata(dev);
fcf265d6
LPC
513 struct ad5064_state *st = iio_priv(indio_dev);
514
515 iio_device_unregister(indio_dev);
516
bb92ff3e
LPC
517 if (!st->use_internal_vref) {
518 regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
519 regulator_bulk_free(ad5064_num_vref(st), st->vref_reg);
520 }
fcf265d6 521
7cbb7537 522 iio_device_free(indio_dev);
fcf265d6
LPC
523
524 return 0;
525}
526
6a17a076
LPC
527#if IS_ENABLED(CONFIG_SPI_MASTER)
528
9660ac70
LPC
529static int ad5064_spi_write(struct ad5064_state *st, unsigned int cmd,
530 unsigned int addr, unsigned int val)
531{
532 struct spi_device *spi = to_spi_device(st->dev);
533
534 st->data.spi = cpu_to_be32(AD5064_CMD(cmd) | AD5064_ADDR(addr) | val);
535 return spi_write(spi, &st->data.spi, sizeof(st->data.spi));
536}
537
fc52692c 538static int ad5064_spi_probe(struct spi_device *spi)
6a17a076
LPC
539{
540 const struct spi_device_id *id = spi_get_device_id(spi);
541
542 return ad5064_probe(&spi->dev, id->driver_data, id->name,
543 ad5064_spi_write);
544}
545
fc52692c 546static int ad5064_spi_remove(struct spi_device *spi)
6a17a076
LPC
547{
548 return ad5064_remove(&spi->dev);
549}
550
551static const struct spi_device_id ad5064_spi_ids[] = {
fcf265d6 552 {"ad5024", ID_AD5024},
f8be4af1 553 {"ad5025", ID_AD5025},
fcf265d6 554 {"ad5044", ID_AD5044},
f8be4af1 555 {"ad5045", ID_AD5045},
fcf265d6
LPC
556 {"ad5064", ID_AD5064},
557 {"ad5064-1", ID_AD5064_1},
f8be4af1 558 {"ad5065", ID_AD5065},
bb92ff3e
LPC
559 {"ad5628-1", ID_AD5628_1},
560 {"ad5628-2", ID_AD5628_2},
561 {"ad5648-1", ID_AD5648_1},
562 {"ad5648-2", ID_AD5648_2},
64f4eaa5
LPC
563 {"ad5666-1", ID_AD5666_1},
564 {"ad5666-2", ID_AD5666_2},
bb92ff3e
LPC
565 {"ad5668-1", ID_AD5668_1},
566 {"ad5668-2", ID_AD5668_2},
567 {"ad5668-3", ID_AD5668_2}, /* similar enough to ad5668-2 */
fcf265d6
LPC
568 {}
569};
6a17a076 570MODULE_DEVICE_TABLE(spi, ad5064_spi_ids);
fcf265d6 571
6a17a076 572static struct spi_driver ad5064_spi_driver = {
fcf265d6
LPC
573 .driver = {
574 .name = "ad5064",
575 .owner = THIS_MODULE,
576 },
6a17a076 577 .probe = ad5064_spi_probe,
fc52692c 578 .remove = ad5064_spi_remove,
6a17a076 579 .id_table = ad5064_spi_ids,
fcf265d6 580};
6a17a076
LPC
581
582static int __init ad5064_spi_register_driver(void)
583{
584 return spi_register_driver(&ad5064_spi_driver);
585}
586
21fa54e4 587static void ad5064_spi_unregister_driver(void)
6a17a076
LPC
588{
589 spi_unregister_driver(&ad5064_spi_driver);
590}
591
592#else
593
594static inline int ad5064_spi_register_driver(void) { return 0; }
595static inline void ad5064_spi_unregister_driver(void) { }
596
597#endif
598
599#if IS_ENABLED(CONFIG_I2C)
600
9660ac70
LPC
601static int ad5064_i2c_write(struct ad5064_state *st, unsigned int cmd,
602 unsigned int addr, unsigned int val)
603{
604 struct i2c_client *i2c = to_i2c_client(st->dev);
605
606 st->data.i2c[0] = (cmd << 4) | addr;
607 put_unaligned_be16(val, &st->data.i2c[1]);
608 return i2c_master_send(i2c, st->data.i2c, 3);
609}
610
fc52692c 611static int ad5064_i2c_probe(struct i2c_client *i2c,
6a17a076
LPC
612 const struct i2c_device_id *id)
613{
614 return ad5064_probe(&i2c->dev, id->driver_data, id->name,
615 ad5064_i2c_write);
616}
617
fc52692c 618static int ad5064_i2c_remove(struct i2c_client *i2c)
6a17a076
LPC
619{
620 return ad5064_remove(&i2c->dev);
621}
622
623static const struct i2c_device_id ad5064_i2c_ids[] = {
624 {"ad5629-1", ID_AD5628_1},
625 {"ad5629-2", ID_AD5628_2},
626 {"ad5629-3", ID_AD5628_2}, /* similar enough to ad5629-2 */
627 {"ad5669-1", ID_AD5668_1},
628 {"ad5669-2", ID_AD5668_2},
629 {"ad5669-3", ID_AD5668_2}, /* similar enough to ad5669-2 */
630 {}
631};
632MODULE_DEVICE_TABLE(i2c, ad5064_i2c_ids);
633
634static struct i2c_driver ad5064_i2c_driver = {
635 .driver = {
636 .name = "ad5064",
637 .owner = THIS_MODULE,
638 },
639 .probe = ad5064_i2c_probe,
fc52692c 640 .remove = ad5064_i2c_remove,
6a17a076
LPC
641 .id_table = ad5064_i2c_ids,
642};
643
644static int __init ad5064_i2c_register_driver(void)
645{
646 return i2c_add_driver(&ad5064_i2c_driver);
647}
648
649static void __exit ad5064_i2c_unregister_driver(void)
650{
651 i2c_del_driver(&ad5064_i2c_driver);
652}
653
654#else
655
656static inline int ad5064_i2c_register_driver(void) { return 0; }
657static inline void ad5064_i2c_unregister_driver(void) { }
658
659#endif
660
661static int __init ad5064_init(void)
662{
663 int ret;
664
665 ret = ad5064_spi_register_driver();
666 if (ret)
667 return ret;
668
669 ret = ad5064_i2c_register_driver();
670 if (ret) {
671 ad5064_spi_unregister_driver();
672 return ret;
673 }
674
675 return 0;
676}
677module_init(ad5064_init);
678
679static void __exit ad5064_exit(void)
680{
681 ad5064_i2c_unregister_driver();
682 ad5064_spi_unregister_driver();
683}
684module_exit(ad5064_exit);
fcf265d6
LPC
685
686MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
6a17a076 687MODULE_DESCRIPTION("Analog Devices AD5024 and similar multi-channel DACs");
fcf265d6 688MODULE_LICENSE("GPL v2");