Commit | Line | Data |
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26717172 LB |
1 | /* |
2 | * intel_idle.c - native hardware idle loop for modern Intel processors | |
3 | * | |
4 | * Copyright (c) 2010, Intel Corporation. | |
5 | * Len Brown <len.brown@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | * intel_idle is a cpuidle driver that loads on specific Intel processors | |
23 | * in lieu of the legacy ACPI processor_idle driver. The intent is to | |
24 | * make Linux more efficient on these processors, as intel_idle knows | |
25 | * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs. | |
26 | */ | |
27 | ||
28 | /* | |
29 | * Design Assumptions | |
30 | * | |
31 | * All CPUs have same idle states as boot CPU | |
32 | * | |
33 | * Chipset BM_STS (bus master status) bit is a NOP | |
34 | * for preventing entry into deep C-stats | |
35 | */ | |
36 | ||
37 | /* | |
38 | * Known limitations | |
39 | * | |
40 | * The driver currently initializes for_each_online_cpu() upon modprobe. | |
41 | * It it unaware of subsequent processors hot-added to the system. | |
42 | * This means that if you boot with maxcpus=n and later online | |
43 | * processors above n, those processors will use C1 only. | |
44 | * | |
45 | * ACPI has a .suspend hack to turn off deep c-statees during suspend | |
46 | * to avoid complications with the lapic timer workaround. | |
47 | * Have not seen issues with suspend, but may need same workaround here. | |
48 | * | |
49 | * There is currently no kernel-based automatic probing/loading mechanism | |
50 | * if the driver is built as a module. | |
51 | */ | |
52 | ||
53 | /* un-comment DEBUG to enable pr_debug() statements */ | |
54 | #define DEBUG | |
55 | ||
56 | #include <linux/kernel.h> | |
57 | #include <linux/cpuidle.h> | |
58 | #include <linux/clockchips.h> | |
26717172 LB |
59 | #include <trace/events/power.h> |
60 | #include <linux/sched.h> | |
2a2d31c8 SL |
61 | #include <linux/notifier.h> |
62 | #include <linux/cpu.h> | |
7c52d551 | 63 | #include <linux/module.h> |
b66b8b9a | 64 | #include <asm/cpu_device_id.h> |
bc83cccc | 65 | #include <asm/mwait.h> |
14796fca | 66 | #include <asm/msr.h> |
26717172 LB |
67 | |
68 | #define INTEL_IDLE_VERSION "0.4" | |
69 | #define PREFIX "intel_idle: " | |
70 | ||
26717172 LB |
71 | static struct cpuidle_driver intel_idle_driver = { |
72 | .name = "intel_idle", | |
73 | .owner = THIS_MODULE, | |
74 | }; | |
75 | /* intel_idle.max_cstate=0 disables driver */ | |
137ecc77 | 76 | static int max_cstate = CPUIDLE_STATE_MAX - 1; |
26717172 | 77 | |
c4236282 | 78 | static unsigned int mwait_substates; |
26717172 | 79 | |
2a2d31c8 | 80 | #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF |
26717172 | 81 | /* Reliable LAPIC Timer States, bit 1 for C1 etc. */ |
d13780d4 | 82 | static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */ |
26717172 | 83 | |
b66b8b9a AK |
84 | struct idle_cpu { |
85 | struct cpuidle_state *state_table; | |
86 | ||
87 | /* | |
88 | * Hardware C-state auto-demotion may not always be optimal. | |
89 | * Indicate which enable bits to clear here. | |
90 | */ | |
91 | unsigned long auto_demotion_disable_flags; | |
32e95180 | 92 | bool disable_promotion_to_c1e; |
b66b8b9a AK |
93 | }; |
94 | ||
95 | static const struct idle_cpu *icpu; | |
3265eba0 | 96 | static struct cpuidle_device __percpu *intel_idle_cpuidle_devices; |
46bcfad7 DD |
97 | static int intel_idle(struct cpuidle_device *dev, |
98 | struct cpuidle_driver *drv, int index); | |
25ac7761 | 99 | static int intel_idle_cpu_init(int cpu); |
26717172 LB |
100 | |
101 | static struct cpuidle_state *cpuidle_state_table; | |
102 | ||
956d033f LB |
103 | /* |
104 | * Set this flag for states where the HW flushes the TLB for us | |
105 | * and so we don't need cross-calls to keep it consistent. | |
106 | * If this flag is set, SW flushes the TLB, so even if the | |
107 | * HW doesn't do the flushing, this flag is safe to use. | |
108 | */ | |
109 | #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000 | |
110 | ||
b1beab48 LB |
111 | /* |
112 | * MWAIT takes an 8-bit "hint" in EAX "suggesting" | |
113 | * the C-state (top nibble) and sub-state (bottom nibble) | |
114 | * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc. | |
115 | * | |
116 | * We store the hint at the top of our "flags" for each state. | |
117 | */ | |
118 | #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF) | |
119 | #define MWAIT2flg(eax) ((eax & 0xFF) << 24) | |
120 | ||
26717172 LB |
121 | /* |
122 | * States are indexed by the cstate number, | |
123 | * which is also the index into the MWAIT hint array. | |
124 | * Thus C0 is a dummy. | |
125 | */ | |
137ecc77 | 126 | static struct cpuidle_state nehalem_cstates[CPUIDLE_STATE_MAX] = { |
e022e7eb | 127 | { |
15e123e5 | 128 | .name = "C1-NHM", |
26717172 | 129 | .desc = "MWAIT 0x00", |
b1beab48 | 130 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, |
26717172 | 131 | .exit_latency = 3, |
26717172 LB |
132 | .target_residency = 6, |
133 | .enter = &intel_idle }, | |
32e95180 LB |
134 | { |
135 | .name = "C1E-NHM", | |
136 | .desc = "MWAIT 0x01", | |
137 | .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, | |
138 | .exit_latency = 10, | |
139 | .target_residency = 20, | |
140 | .enter = &intel_idle }, | |
e022e7eb | 141 | { |
15e123e5 | 142 | .name = "C3-NHM", |
26717172 | 143 | .desc = "MWAIT 0x10", |
b1beab48 | 144 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 145 | .exit_latency = 20, |
26717172 LB |
146 | .target_residency = 80, |
147 | .enter = &intel_idle }, | |
e022e7eb | 148 | { |
15e123e5 | 149 | .name = "C6-NHM", |
26717172 | 150 | .desc = "MWAIT 0x20", |
b1beab48 | 151 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 152 | .exit_latency = 200, |
26717172 LB |
153 | .target_residency = 800, |
154 | .enter = &intel_idle }, | |
e022e7eb LB |
155 | { |
156 | .enter = NULL } | |
26717172 LB |
157 | }; |
158 | ||
137ecc77 | 159 | static struct cpuidle_state snb_cstates[CPUIDLE_STATE_MAX] = { |
e022e7eb | 160 | { |
15e123e5 | 161 | .name = "C1-SNB", |
d13780d4 | 162 | .desc = "MWAIT 0x00", |
b1beab48 | 163 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, |
32e95180 LB |
164 | .exit_latency = 2, |
165 | .target_residency = 2, | |
166 | .enter = &intel_idle }, | |
167 | { | |
168 | .name = "C1E-SNB", | |
169 | .desc = "MWAIT 0x01", | |
170 | .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, | |
171 | .exit_latency = 10, | |
172 | .target_residency = 20, | |
d13780d4 | 173 | .enter = &intel_idle }, |
e022e7eb | 174 | { |
15e123e5 | 175 | .name = "C3-SNB", |
d13780d4 | 176 | .desc = "MWAIT 0x10", |
b1beab48 | 177 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 178 | .exit_latency = 80, |
ddbd550d | 179 | .target_residency = 211, |
d13780d4 | 180 | .enter = &intel_idle }, |
e022e7eb | 181 | { |
15e123e5 | 182 | .name = "C6-SNB", |
d13780d4 | 183 | .desc = "MWAIT 0x20", |
b1beab48 | 184 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 185 | .exit_latency = 104, |
ddbd550d | 186 | .target_residency = 345, |
d13780d4 | 187 | .enter = &intel_idle }, |
e022e7eb | 188 | { |
15e123e5 | 189 | .name = "C7-SNB", |
d13780d4 | 190 | .desc = "MWAIT 0x30", |
b1beab48 | 191 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
d13780d4 | 192 | .exit_latency = 109, |
ddbd550d | 193 | .target_residency = 345, |
d13780d4 | 194 | .enter = &intel_idle }, |
e022e7eb LB |
195 | { |
196 | .enter = NULL } | |
d13780d4 LB |
197 | }; |
198 | ||
137ecc77 | 199 | static struct cpuidle_state ivb_cstates[CPUIDLE_STATE_MAX] = { |
e022e7eb | 200 | { |
6edab08c LB |
201 | .name = "C1-IVB", |
202 | .desc = "MWAIT 0x00", | |
b1beab48 | 203 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, |
6edab08c LB |
204 | .exit_latency = 1, |
205 | .target_residency = 1, | |
206 | .enter = &intel_idle }, | |
32e95180 LB |
207 | { |
208 | .name = "C1E-IVB", | |
209 | .desc = "MWAIT 0x01", | |
210 | .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, | |
211 | .exit_latency = 10, | |
212 | .target_residency = 20, | |
213 | .enter = &intel_idle }, | |
e022e7eb | 214 | { |
6edab08c LB |
215 | .name = "C3-IVB", |
216 | .desc = "MWAIT 0x10", | |
b1beab48 | 217 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
218 | .exit_latency = 59, |
219 | .target_residency = 156, | |
220 | .enter = &intel_idle }, | |
e022e7eb | 221 | { |
6edab08c LB |
222 | .name = "C6-IVB", |
223 | .desc = "MWAIT 0x20", | |
b1beab48 | 224 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
225 | .exit_latency = 80, |
226 | .target_residency = 300, | |
227 | .enter = &intel_idle }, | |
e022e7eb | 228 | { |
6edab08c LB |
229 | .name = "C7-IVB", |
230 | .desc = "MWAIT 0x30", | |
b1beab48 | 231 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
6edab08c LB |
232 | .exit_latency = 87, |
233 | .target_residency = 300, | |
234 | .enter = &intel_idle }, | |
e022e7eb LB |
235 | { |
236 | .enter = NULL } | |
6edab08c LB |
237 | }; |
238 | ||
137ecc77 | 239 | static struct cpuidle_state hsw_cstates[CPUIDLE_STATE_MAX] = { |
e022e7eb | 240 | { |
85a4d2d4 LB |
241 | .name = "C1-HSW", |
242 | .desc = "MWAIT 0x00", | |
243 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, | |
244 | .exit_latency = 2, | |
245 | .target_residency = 2, | |
246 | .enter = &intel_idle }, | |
32e95180 LB |
247 | { |
248 | .name = "C1E-HSW", | |
249 | .desc = "MWAIT 0x01", | |
250 | .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, | |
251 | .exit_latency = 10, | |
252 | .target_residency = 20, | |
253 | .enter = &intel_idle }, | |
e022e7eb | 254 | { |
85a4d2d4 LB |
255 | .name = "C3-HSW", |
256 | .desc = "MWAIT 0x10", | |
257 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
258 | .exit_latency = 33, | |
259 | .target_residency = 100, | |
260 | .enter = &intel_idle }, | |
e022e7eb | 261 | { |
85a4d2d4 LB |
262 | .name = "C6-HSW", |
263 | .desc = "MWAIT 0x20", | |
264 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
265 | .exit_latency = 133, | |
266 | .target_residency = 400, | |
267 | .enter = &intel_idle }, | |
e022e7eb | 268 | { |
85a4d2d4 LB |
269 | .name = "C7s-HSW", |
270 | .desc = "MWAIT 0x32", | |
271 | .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
272 | .exit_latency = 166, | |
273 | .target_residency = 500, | |
274 | .enter = &intel_idle }, | |
86239ceb LB |
275 | { |
276 | .name = "C8-HSW", | |
277 | .desc = "MWAIT 0x40", | |
278 | .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
279 | .exit_latency = 300, | |
280 | .target_residency = 900, | |
281 | .enter = &intel_idle }, | |
282 | { | |
283 | .name = "C9-HSW", | |
284 | .desc = "MWAIT 0x50", | |
285 | .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
286 | .exit_latency = 600, | |
287 | .target_residency = 1800, | |
288 | .enter = &intel_idle }, | |
289 | { | |
290 | .name = "C10-HSW", | |
291 | .desc = "MWAIT 0x60", | |
292 | .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | |
293 | .exit_latency = 2600, | |
294 | .target_residency = 7700, | |
295 | .enter = &intel_idle }, | |
e022e7eb LB |
296 | { |
297 | .enter = NULL } | |
85a4d2d4 LB |
298 | }; |
299 | ||
137ecc77 | 300 | static struct cpuidle_state atom_cstates[CPUIDLE_STATE_MAX] = { |
e022e7eb | 301 | { |
32e95180 | 302 | .name = "C1E-ATM", |
26717172 | 303 | .desc = "MWAIT 0x00", |
b1beab48 | 304 | .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, |
32e95180 LB |
305 | .exit_latency = 10, |
306 | .target_residency = 20, | |
26717172 | 307 | .enter = &intel_idle }, |
e022e7eb | 308 | { |
15e123e5 | 309 | .name = "C2-ATM", |
26717172 | 310 | .desc = "MWAIT 0x10", |
b1beab48 | 311 | .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID, |
26717172 | 312 | .exit_latency = 20, |
26717172 LB |
313 | .target_residency = 80, |
314 | .enter = &intel_idle }, | |
e022e7eb | 315 | { |
15e123e5 | 316 | .name = "C4-ATM", |
26717172 | 317 | .desc = "MWAIT 0x30", |
b1beab48 | 318 | .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
26717172 | 319 | .exit_latency = 100, |
26717172 LB |
320 | .target_residency = 400, |
321 | .enter = &intel_idle }, | |
e022e7eb | 322 | { |
15e123e5 | 323 | .name = "C6-ATM", |
7fcca7d9 | 324 | .desc = "MWAIT 0x52", |
b1beab48 | 325 | .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, |
7fcca7d9 | 326 | .exit_latency = 140, |
7fcca7d9 LB |
327 | .target_residency = 560, |
328 | .enter = &intel_idle }, | |
e022e7eb LB |
329 | { |
330 | .enter = NULL } | |
26717172 LB |
331 | }; |
332 | ||
26717172 LB |
333 | /** |
334 | * intel_idle | |
335 | * @dev: cpuidle_device | |
46bcfad7 | 336 | * @drv: cpuidle driver |
e978aa7d | 337 | * @index: index of cpuidle state |
26717172 | 338 | * |
63ff07be | 339 | * Must be called under local_irq_disable(). |
26717172 | 340 | */ |
46bcfad7 DD |
341 | static int intel_idle(struct cpuidle_device *dev, |
342 | struct cpuidle_driver *drv, int index) | |
26717172 LB |
343 | { |
344 | unsigned long ecx = 1; /* break on interrupt flag */ | |
46bcfad7 | 345 | struct cpuidle_state *state = &drv->states[index]; |
b1beab48 | 346 | unsigned long eax = flg2MWAIT(state->flags); |
26717172 | 347 | unsigned int cstate; |
26717172 LB |
348 | int cpu = smp_processor_id(); |
349 | ||
350 | cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1; | |
351 | ||
6110a1f4 | 352 | /* |
c8381cc3 LB |
353 | * leave_mm() to avoid costly and often unnecessary wakeups |
354 | * for flushing the user TLB's associated with the active mm. | |
6110a1f4 | 355 | */ |
c8381cc3 | 356 | if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED) |
6110a1f4 SS |
357 | leave_mm(cpu); |
358 | ||
26717172 LB |
359 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) |
360 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
361 | ||
e895dad0 | 362 | if (!current_set_polling_and_test()) { |
26717172 | 363 | |
024df8e2 LB |
364 | if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR)) |
365 | clflush((void *)¤t_thread_info()->flags); | |
366 | ||
26717172 LB |
367 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
368 | smp_mb(); | |
369 | if (!need_resched()) | |
370 | __mwait(eax, ecx); | |
371 | } | |
372 | ||
26717172 LB |
373 | if (!(lapic_timer_reliable_states & (1 << (cstate)))) |
374 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
375 | ||
e978aa7d | 376 | return index; |
26717172 LB |
377 | } |
378 | ||
2a2d31c8 SL |
379 | static void __setup_broadcast_timer(void *arg) |
380 | { | |
381 | unsigned long reason = (unsigned long)arg; | |
382 | int cpu = smp_processor_id(); | |
383 | ||
384 | reason = reason ? | |
385 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
386 | ||
387 | clockevents_notify(reason, &cpu); | |
388 | } | |
389 | ||
25ac7761 DL |
390 | static int cpu_hotplug_notify(struct notifier_block *n, |
391 | unsigned long action, void *hcpu) | |
2a2d31c8 SL |
392 | { |
393 | int hotcpu = (unsigned long)hcpu; | |
25ac7761 | 394 | struct cpuidle_device *dev; |
2a2d31c8 SL |
395 | |
396 | switch (action & 0xf) { | |
397 | case CPU_ONLINE: | |
25ac7761 DL |
398 | |
399 | if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) | |
400 | smp_call_function_single(hotcpu, __setup_broadcast_timer, | |
401 | (void *)true, 1); | |
402 | ||
403 | /* | |
404 | * Some systems can hotplug a cpu at runtime after | |
405 | * the kernel has booted, we have to initialize the | |
406 | * driver in this case | |
407 | */ | |
408 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu); | |
409 | if (!dev->registered) | |
410 | intel_idle_cpu_init(hotcpu); | |
411 | ||
2a2d31c8 | 412 | break; |
2a2d31c8 SL |
413 | } |
414 | return NOTIFY_OK; | |
415 | } | |
416 | ||
25ac7761 DL |
417 | static struct notifier_block cpu_hotplug_notifier = { |
418 | .notifier_call = cpu_hotplug_notify, | |
2a2d31c8 SL |
419 | }; |
420 | ||
14796fca LB |
421 | static void auto_demotion_disable(void *dummy) |
422 | { | |
423 | unsigned long long msr_bits; | |
424 | ||
425 | rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); | |
b66b8b9a | 426 | msr_bits &= ~(icpu->auto_demotion_disable_flags); |
14796fca LB |
427 | wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); |
428 | } | |
32e95180 LB |
429 | static void c1e_promotion_disable(void *dummy) |
430 | { | |
431 | unsigned long long msr_bits; | |
432 | ||
433 | rdmsrl(MSR_IA32_POWER_CTL, msr_bits); | |
434 | msr_bits &= ~0x2; | |
435 | wrmsrl(MSR_IA32_POWER_CTL, msr_bits); | |
436 | } | |
14796fca | 437 | |
b66b8b9a AK |
438 | static const struct idle_cpu idle_cpu_nehalem = { |
439 | .state_table = nehalem_cstates, | |
b66b8b9a | 440 | .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE, |
32e95180 | 441 | .disable_promotion_to_c1e = true, |
b66b8b9a AK |
442 | }; |
443 | ||
444 | static const struct idle_cpu idle_cpu_atom = { | |
445 | .state_table = atom_cstates, | |
446 | }; | |
447 | ||
448 | static const struct idle_cpu idle_cpu_lincroft = { | |
449 | .state_table = atom_cstates, | |
450 | .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE, | |
451 | }; | |
452 | ||
453 | static const struct idle_cpu idle_cpu_snb = { | |
454 | .state_table = snb_cstates, | |
32e95180 | 455 | .disable_promotion_to_c1e = true, |
b66b8b9a AK |
456 | }; |
457 | ||
6edab08c LB |
458 | static const struct idle_cpu idle_cpu_ivb = { |
459 | .state_table = ivb_cstates, | |
32e95180 | 460 | .disable_promotion_to_c1e = true, |
6edab08c LB |
461 | }; |
462 | ||
85a4d2d4 LB |
463 | static const struct idle_cpu idle_cpu_hsw = { |
464 | .state_table = hsw_cstates, | |
32e95180 | 465 | .disable_promotion_to_c1e = true, |
85a4d2d4 LB |
466 | }; |
467 | ||
b66b8b9a AK |
468 | #define ICPU(model, cpu) \ |
469 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } | |
470 | ||
471 | static const struct x86_cpu_id intel_idle_ids[] = { | |
472 | ICPU(0x1a, idle_cpu_nehalem), | |
473 | ICPU(0x1e, idle_cpu_nehalem), | |
474 | ICPU(0x1f, idle_cpu_nehalem), | |
8bf11938 BH |
475 | ICPU(0x25, idle_cpu_nehalem), |
476 | ICPU(0x2c, idle_cpu_nehalem), | |
477 | ICPU(0x2e, idle_cpu_nehalem), | |
b66b8b9a AK |
478 | ICPU(0x1c, idle_cpu_atom), |
479 | ICPU(0x26, idle_cpu_lincroft), | |
8bf11938 | 480 | ICPU(0x2f, idle_cpu_nehalem), |
b66b8b9a AK |
481 | ICPU(0x2a, idle_cpu_snb), |
482 | ICPU(0x2d, idle_cpu_snb), | |
6edab08c | 483 | ICPU(0x3a, idle_cpu_ivb), |
23795e58 | 484 | ICPU(0x3e, idle_cpu_ivb), |
85a4d2d4 LB |
485 | ICPU(0x3c, idle_cpu_hsw), |
486 | ICPU(0x3f, idle_cpu_hsw), | |
487 | ICPU(0x45, idle_cpu_hsw), | |
0b15841b | 488 | ICPU(0x46, idle_cpu_hsw), |
b66b8b9a AK |
489 | {} |
490 | }; | |
491 | MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids); | |
492 | ||
26717172 LB |
493 | /* |
494 | * intel_idle_probe() | |
495 | */ | |
496 | static int intel_idle_probe(void) | |
497 | { | |
c4236282 | 498 | unsigned int eax, ebx, ecx; |
b66b8b9a | 499 | const struct x86_cpu_id *id; |
26717172 LB |
500 | |
501 | if (max_cstate == 0) { | |
502 | pr_debug(PREFIX "disabled\n"); | |
503 | return -EPERM; | |
504 | } | |
505 | ||
b66b8b9a AK |
506 | id = x86_match_cpu(intel_idle_ids); |
507 | if (!id) { | |
508 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
509 | boot_cpu_data.x86 == 6) | |
510 | pr_debug(PREFIX "does not run on family %d model %d\n", | |
511 | boot_cpu_data.x86, boot_cpu_data.x86_model); | |
26717172 | 512 | return -ENODEV; |
b66b8b9a | 513 | } |
26717172 LB |
514 | |
515 | if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) | |
516 | return -ENODEV; | |
517 | ||
c4236282 | 518 | cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); |
26717172 LB |
519 | |
520 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || | |
5c2a9f06 TR |
521 | !(ecx & CPUID5_ECX_INTERRUPT_BREAK) || |
522 | !mwait_substates) | |
26717172 | 523 | return -ENODEV; |
26717172 | 524 | |
c4236282 | 525 | pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates); |
26717172 | 526 | |
b66b8b9a AK |
527 | icpu = (const struct idle_cpu *)id->driver_data; |
528 | cpuidle_state_table = icpu->state_table; | |
26717172 | 529 | |
56b9aea3 | 530 | if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */ |
2a2d31c8 | 531 | lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE; |
25ac7761 | 532 | else |
39a74fde | 533 | on_each_cpu(__setup_broadcast_timer, (void *)true, 1); |
25ac7761 | 534 | |
26717172 LB |
535 | pr_debug(PREFIX "v" INTEL_IDLE_VERSION |
536 | " model 0x%X\n", boot_cpu_data.x86_model); | |
537 | ||
538 | pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n", | |
539 | lapic_timer_reliable_states); | |
540 | return 0; | |
541 | } | |
542 | ||
543 | /* | |
544 | * intel_idle_cpuidle_devices_uninit() | |
545 | * unregister, free cpuidle_devices | |
546 | */ | |
547 | static void intel_idle_cpuidle_devices_uninit(void) | |
548 | { | |
549 | int i; | |
550 | struct cpuidle_device *dev; | |
551 | ||
552 | for_each_online_cpu(i) { | |
553 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, i); | |
554 | cpuidle_unregister_device(dev); | |
555 | } | |
556 | ||
557 | free_percpu(intel_idle_cpuidle_devices); | |
558 | return; | |
559 | } | |
46bcfad7 DD |
560 | /* |
561 | * intel_idle_cpuidle_driver_init() | |
562 | * allocate, initialize cpuidle_states | |
563 | */ | |
564 | static int intel_idle_cpuidle_driver_init(void) | |
565 | { | |
566 | int cstate; | |
567 | struct cpuidle_driver *drv = &intel_idle_driver; | |
568 | ||
569 | drv->state_count = 1; | |
570 | ||
e022e7eb LB |
571 | for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { |
572 | int num_substates, mwait_hint, mwait_cstate, mwait_substate; | |
46bcfad7 | 573 | |
e022e7eb LB |
574 | if (cpuidle_state_table[cstate].enter == NULL) |
575 | break; | |
576 | ||
577 | if (cstate + 1 > max_cstate) { | |
46bcfad7 DD |
578 | printk(PREFIX "max_cstate %d reached\n", |
579 | max_cstate); | |
580 | break; | |
581 | } | |
582 | ||
e022e7eb LB |
583 | mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); |
584 | mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint); | |
585 | mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint); | |
586 | ||
46bcfad7 | 587 | /* does the state exist in CPUID.MWAIT? */ |
e022e7eb | 588 | num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4)) |
46bcfad7 | 589 | & MWAIT_SUBSTATE_MASK; |
e022e7eb LB |
590 | |
591 | /* if sub-state in table is not enumerated by CPUID */ | |
592 | if ((mwait_substate + 1) > num_substates) | |
46bcfad7 | 593 | continue; |
46bcfad7 | 594 | |
e022e7eb | 595 | if (((mwait_cstate + 1) > 2) && |
46bcfad7 DD |
596 | !boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
597 | mark_tsc_unstable("TSC halts in idle" | |
598 | " states deeper than C2"); | |
599 | ||
600 | drv->states[drv->state_count] = /* structure copy */ | |
601 | cpuidle_state_table[cstate]; | |
602 | ||
603 | drv->state_count += 1; | |
604 | } | |
605 | ||
b66b8b9a | 606 | if (icpu->auto_demotion_disable_flags) |
39a74fde | 607 | on_each_cpu(auto_demotion_disable, NULL, 1); |
46bcfad7 | 608 | |
32e95180 LB |
609 | if (icpu->disable_promotion_to_c1e) /* each-cpu is redundant */ |
610 | on_each_cpu(c1e_promotion_disable, NULL, 1); | |
611 | ||
46bcfad7 DD |
612 | return 0; |
613 | } | |
614 | ||
615 | ||
26717172 | 616 | /* |
65b7f839 | 617 | * intel_idle_cpu_init() |
26717172 | 618 | * allocate, initialize, register cpuidle_devices |
65b7f839 | 619 | * @cpu: cpu/core to initialize |
26717172 | 620 | */ |
25ac7761 | 621 | static int intel_idle_cpu_init(int cpu) |
26717172 | 622 | { |
65b7f839 | 623 | int cstate; |
26717172 LB |
624 | struct cpuidle_device *dev; |
625 | ||
65b7f839 | 626 | dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu); |
26717172 | 627 | |
65b7f839 | 628 | dev->state_count = 1; |
26717172 | 629 | |
e022e7eb LB |
630 | for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) { |
631 | int num_substates, mwait_hint, mwait_cstate, mwait_substate; | |
26717172 | 632 | |
e022e7eb LB |
633 | if (cpuidle_state_table[cstate].enter == NULL) |
634 | continue; | |
635 | ||
636 | if (cstate + 1 > max_cstate) { | |
dc716e96 | 637 | printk(PREFIX "max_cstate %d reached\n", max_cstate); |
65b7f839 TR |
638 | break; |
639 | } | |
26717172 | 640 | |
e022e7eb LB |
641 | mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags); |
642 | mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint); | |
643 | mwait_substate = MWAIT_HINT2SUBSTATE(mwait_hint); | |
644 | ||
65b7f839 | 645 | /* does the state exist in CPUID.MWAIT? */ |
e022e7eb LB |
646 | num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4)) |
647 | & MWAIT_SUBSTATE_MASK; | |
648 | ||
649 | /* if sub-state in table is not enumerated by CPUID */ | |
650 | if ((mwait_substate + 1) > num_substates) | |
65b7f839 | 651 | continue; |
26717172 | 652 | |
dc716e96 MPS |
653 | dev->state_count += 1; |
654 | } | |
655 | ||
65b7f839 | 656 | dev->cpu = cpu; |
26717172 | 657 | |
65b7f839 TR |
658 | if (cpuidle_register_device(dev)) { |
659 | pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu); | |
660 | intel_idle_cpuidle_devices_uninit(); | |
661 | return -EIO; | |
26717172 LB |
662 | } |
663 | ||
b66b8b9a | 664 | if (icpu->auto_demotion_disable_flags) |
65b7f839 TR |
665 | smp_call_function_single(cpu, auto_demotion_disable, NULL, 1); |
666 | ||
26717172 LB |
667 | return 0; |
668 | } | |
26717172 LB |
669 | |
670 | static int __init intel_idle_init(void) | |
671 | { | |
65b7f839 | 672 | int retval, i; |
26717172 | 673 | |
d1896049 TR |
674 | /* Do not load intel_idle at all for now if idle= is passed */ |
675 | if (boot_option_idle_override != IDLE_NO_OVERRIDE) | |
676 | return -ENODEV; | |
677 | ||
26717172 LB |
678 | retval = intel_idle_probe(); |
679 | if (retval) | |
680 | return retval; | |
681 | ||
46bcfad7 | 682 | intel_idle_cpuidle_driver_init(); |
26717172 LB |
683 | retval = cpuidle_register_driver(&intel_idle_driver); |
684 | if (retval) { | |
3735d524 | 685 | struct cpuidle_driver *drv = cpuidle_get_driver(); |
26717172 | 686 | printk(KERN_DEBUG PREFIX "intel_idle yielding to %s", |
3735d524 | 687 | drv ? drv->name : "none"); |
26717172 LB |
688 | return retval; |
689 | } | |
690 | ||
65b7f839 TR |
691 | intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device); |
692 | if (intel_idle_cpuidle_devices == NULL) | |
693 | return -ENOMEM; | |
694 | ||
695 | for_each_online_cpu(i) { | |
696 | retval = intel_idle_cpu_init(i); | |
697 | if (retval) { | |
698 | cpuidle_unregister_driver(&intel_idle_driver); | |
699 | return retval; | |
700 | } | |
26717172 | 701 | } |
6f8c2e79 | 702 | register_cpu_notifier(&cpu_hotplug_notifier); |
26717172 LB |
703 | |
704 | return 0; | |
705 | } | |
706 | ||
707 | static void __exit intel_idle_exit(void) | |
708 | { | |
709 | intel_idle_cpuidle_devices_uninit(); | |
710 | cpuidle_unregister_driver(&intel_idle_driver); | |
711 | ||
25ac7761 DL |
712 | |
713 | if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) | |
39a74fde | 714 | on_each_cpu(__setup_broadcast_timer, (void *)false, 1); |
25ac7761 | 715 | unregister_cpu_notifier(&cpu_hotplug_notifier); |
2a2d31c8 | 716 | |
26717172 LB |
717 | return; |
718 | } | |
719 | ||
720 | module_init(intel_idle_init); | |
721 | module_exit(intel_idle_exit); | |
722 | ||
26717172 | 723 | module_param(max_cstate, int, 0444); |
26717172 LB |
724 | |
725 | MODULE_AUTHOR("Len Brown <len.brown@intel.com>"); | |
726 | MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION); | |
727 | MODULE_LICENSE("GPL"); |