Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * VIA IDE driver for Linux. Supported southbridges: |
3 | * | |
4 | * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, | |
5 | * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, | |
a7dec1e0 | 6 | * vt8235, vt8237, vt8237a |
1da177e4 LT |
7 | * |
8 | * Copyright (c) 2000-2002 Vojtech Pavlik | |
42036c85 | 9 | * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
10 | * |
11 | * Based on the work of: | |
12 | * Michel Aubry | |
13 | * Jeff Garzik | |
14 | * Andre Hedrick | |
15 | * | |
16 | * Documentation: | |
25985edc | 17 | * Obsolete device documentation publicly available from via.com.tw |
1da177e4 LT |
18 | * Current device documentation available under NDA only |
19 | */ | |
20 | ||
21 | /* | |
22 | * This program is free software; you can redistribute it and/or modify it | |
23 | * under the terms of the GNU General Public License version 2 as published by | |
24 | * the Free Software Foundation. | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | #include <linux/module.h> |
28 | #include <linux/kernel.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
1da177e4 LT |
30 | #include <linux/pci.h> |
31 | #include <linux/init.h> | |
32 | #include <linux/ide.h> | |
bdab00b7 BZ |
33 | #include <linux/dmi.h> |
34 | ||
74a9d5f1 | 35 | #ifdef CONFIG_PPC_CHRP |
1da177e4 LT |
36 | #include <asm/processor.h> |
37 | #endif | |
38 | ||
ced3ec8a BZ |
39 | #define DRV_NAME "via82cxxx" |
40 | ||
1da177e4 LT |
41 | #define VIA_IDE_ENABLE 0x40 |
42 | #define VIA_IDE_CONFIG 0x41 | |
43 | #define VIA_FIFO_CONFIG 0x43 | |
44 | #define VIA_MISC_1 0x44 | |
45 | #define VIA_MISC_2 0x45 | |
46 | #define VIA_MISC_3 0x46 | |
47 | #define VIA_DRIVE_TIMING 0x48 | |
48 | #define VIA_8BIT_TIMING 0x4e | |
49 | #define VIA_ADDRESS_SETUP 0x4c | |
50 | #define VIA_UDMA_TIMING 0x50 | |
51 | ||
75b1d975 BZ |
52 | #define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */ |
53 | #define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */ | |
54 | #define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */ | |
55 | #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */ | |
56 | #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */ | |
57 | #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */ | |
a13e4865 | 58 | #define VIA_SATA_PATA 0x80 /* SATA/PATA combined configuration */ |
1da177e4 | 59 | |
42036c85 BZ |
60 | enum { |
61 | VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */ | |
62 | }; | |
63 | ||
1da177e4 LT |
64 | /* |
65 | * VIA SouthBridge chips. | |
66 | */ | |
67 | ||
68 | static struct via_isa_bridge { | |
69 | char *name; | |
70 | u16 id; | |
71 | u8 rev_min; | |
72 | u8 rev_max; | |
75b1d975 BZ |
73 | u8 udma_mask; |
74 | u8 flags; | |
1da177e4 | 75 | } via_isa_bridges[] = { |
a13e4865 BZ |
76 | { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, |
77 | { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, | |
78 | { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA }, | |
5b6c82ea | 79 | { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
75b1d975 BZ |
80 | { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
81 | { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
2a800b7b | 82 | { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST }, |
75b1d975 BZ |
83 | { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
84 | { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
85 | { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
86 | { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
87 | { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
88 | { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, }, | |
89 | { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, }, | |
90 | { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, }, | |
91 | { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, }, | |
92 | { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, }, | |
93 | { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
94 | { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, }, | |
95 | { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
96 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO }, | |
97 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ }, | |
98 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO }, | |
99 | { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO }, | |
100 | { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO }, | |
101 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK }, | |
102 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, | |
5b6c82ea | 103 | { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
1da177e4 LT |
104 | { NULL } |
105 | }; | |
106 | ||
1da177e4 | 107 | static unsigned int via_clock; |
75b1d975 | 108 | static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" }; |
1da177e4 | 109 | |
7462cbff DD |
110 | struct via82cxxx_dev |
111 | { | |
112 | struct via_isa_bridge *via_config; | |
113 | unsigned int via_80w; | |
114 | }; | |
115 | ||
1da177e4 LT |
116 | /** |
117 | * via_set_speed - write timing registers | |
118 | * @dev: PCI device | |
119 | * @dn: device | |
120 | * @timing: IDE timing data to use | |
121 | * | |
122 | * via_set_speed writes timing values to the chipset registers | |
123 | */ | |
124 | ||
7462cbff | 125 | static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) |
1da177e4 | 126 | { |
36501650 | 127 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
ee77325b BZ |
128 | struct ide_host *host = pci_get_drvdata(dev); |
129 | struct via82cxxx_dev *vdev = host->host_priv; | |
1da177e4 LT |
130 | u8 t; |
131 | ||
7462cbff | 132 | if (~vdev->via_config->flags & VIA_BAD_AST) { |
1da177e4 | 133 | pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t); |
d6cddd3c | 134 | t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); |
1da177e4 LT |
135 | pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t); |
136 | } | |
137 | ||
138 | pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)), | |
d6cddd3c | 139 | ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); |
1da177e4 LT |
140 | |
141 | pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn), | |
d6cddd3c | 142 | ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); |
1da177e4 | 143 | |
75b1d975 | 144 | switch (vdev->via_config->udma_mask) { |
d6cddd3c HH |
145 | case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; |
146 | case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break; | |
147 | case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; | |
148 | case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; | |
1da177e4 LT |
149 | } |
150 | ||
68d0a036 BZ |
151 | /* Set UDMA unless device is not UDMA capable */ |
152 | if (vdev->via_config->udma_mask) { | |
153 | u8 udma_etc; | |
154 | ||
155 | pci_read_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, &udma_etc); | |
156 | ||
157 | /* clear transfer mode bit */ | |
158 | udma_etc &= ~0x20; | |
159 | ||
160 | if (timing->udma) { | |
161 | /* preserve 80-wire cable detection bit */ | |
162 | udma_etc &= 0x10; | |
163 | udma_etc |= t; | |
164 | } | |
165 | ||
166 | pci_write_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, udma_etc); | |
167 | } | |
1da177e4 LT |
168 | } |
169 | ||
170 | /** | |
171 | * via_set_drive - configure transfer mode | |
8776168c | 172 | * @hwif: port |
1da177e4 | 173 | * @drive: Drive to set up |
1da177e4 | 174 | * |
88b2b32b BZ |
175 | * via_set_drive() computes timing values configures the chipset to |
176 | * a desired transfer mode. It also can be called by upper layers. | |
1da177e4 LT |
177 | */ |
178 | ||
8776168c | 179 | static void via_set_drive(ide_hwif_t *hwif, ide_drive_t *drive) |
1da177e4 | 180 | { |
7e59ea21 | 181 | ide_drive_t *peer = ide_get_pair_dev(drive); |
36501650 | 182 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
ee77325b BZ |
183 | struct ide_host *host = pci_get_drvdata(dev); |
184 | struct via82cxxx_dev *vdev = host->host_priv; | |
1da177e4 LT |
185 | struct ide_timing t, p; |
186 | unsigned int T, UT; | |
8776168c | 187 | const u8 speed = drive->dma_mode; |
1da177e4 | 188 | |
1da177e4 LT |
189 | T = 1000000000 / via_clock; |
190 | ||
75b1d975 BZ |
191 | switch (vdev->via_config->udma_mask) { |
192 | case ATA_UDMA2: UT = T; break; | |
193 | case ATA_UDMA4: UT = T/2; break; | |
194 | case ATA_UDMA5: UT = T/3; break; | |
195 | case ATA_UDMA6: UT = T/4; break; | |
196 | default: UT = T; | |
1da177e4 LT |
197 | } |
198 | ||
199 | ide_timing_compute(drive, speed, &t, T, UT); | |
200 | ||
7e59ea21 | 201 | if (peer) { |
f0e5f62d | 202 | ide_timing_compute(peer, peer->pio_mode, &p, T, UT); |
1da177e4 LT |
203 | ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); |
204 | } | |
205 | ||
898ec223 | 206 | via_set_speed(hwif, drive->dn, &t); |
1da177e4 LT |
207 | } |
208 | ||
209 | /** | |
88b2b32b | 210 | * via_set_pio_mode - set host controller for PIO mode |
e085b3ca | 211 | * @hwif: port |
26bcb879 | 212 | * @drive: drive |
1da177e4 LT |
213 | * |
214 | * A callback from the upper layers for PIO-only tuning. | |
215 | */ | |
216 | ||
e085b3ca | 217 | static void via_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
1da177e4 | 218 | { |
8776168c BZ |
219 | drive->dma_mode = drive->pio_mode; |
220 | via_set_drive(hwif, drive); | |
1da177e4 LT |
221 | } |
222 | ||
7462cbff DD |
223 | static struct via_isa_bridge *via_config_find(struct pci_dev **isa) |
224 | { | |
225 | struct via_isa_bridge *via_config; | |
7462cbff | 226 | |
5b6c82ea BZ |
227 | for (via_config = via_isa_bridges; |
228 | via_config->id != PCI_DEVICE_ID_VIA_ANON; via_config++) | |
652aa162 | 229 | if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA + |
7462cbff DD |
230 | !!(via_config->flags & VIA_BAD_ID), |
231 | via_config->id, NULL))) { | |
232 | ||
44c10138 AK |
233 | if ((*isa)->revision >= via_config->rev_min && |
234 | (*isa)->revision <= via_config->rev_max) | |
7462cbff | 235 | break; |
652aa162 | 236 | pci_dev_put(*isa); |
7462cbff DD |
237 | } |
238 | ||
239 | return via_config; | |
1da177e4 LT |
240 | } |
241 | ||
cd36beec BZ |
242 | /* |
243 | * Check and handle 80-wire cable presence | |
244 | */ | |
feb22b7f | 245 | static void via_cable_detect(struct via82cxxx_dev *vdev, u32 u) |
cd36beec BZ |
246 | { |
247 | int i; | |
248 | ||
75b1d975 BZ |
249 | switch (vdev->via_config->udma_mask) { |
250 | case ATA_UDMA4: | |
cd36beec BZ |
251 | for (i = 24; i >= 0; i -= 8) |
252 | if (((u >> (i & 16)) & 8) && | |
253 | ((u >> i) & 0x20) && | |
254 | (((u >> i) & 7) < 2)) { | |
255 | /* | |
256 | * 2x PCI clock and | |
257 | * UDMA w/ < 3T/cycle | |
258 | */ | |
259 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
260 | } | |
261 | break; | |
262 | ||
75b1d975 | 263 | case ATA_UDMA5: |
cd36beec BZ |
264 | for (i = 24; i >= 0; i -= 8) |
265 | if (((u >> i) & 0x10) || | |
266 | (((u >> i) & 0x20) && | |
267 | (((u >> i) & 7) < 4))) { | |
268 | /* BIOS 80-wire bit or | |
269 | * UDMA w/ < 60ns/cycle | |
270 | */ | |
271 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
272 | } | |
273 | break; | |
274 | ||
75b1d975 | 275 | case ATA_UDMA6: |
cd36beec BZ |
276 | for (i = 24; i >= 0; i -= 8) |
277 | if (((u >> i) & 0x10) || | |
278 | (((u >> i) & 0x20) && | |
279 | (((u >> i) & 7) < 6))) { | |
280 | /* BIOS 80-wire bit or | |
281 | * UDMA w/ < 60ns/cycle | |
282 | */ | |
283 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
284 | } | |
285 | break; | |
286 | } | |
287 | } | |
288 | ||
1da177e4 LT |
289 | /** |
290 | * init_chipset_via82cxxx - initialization handler | |
291 | * @dev: PCI device | |
1da177e4 LT |
292 | * |
293 | * The initialization callback. Here we determine the IDE chip type | |
294 | * and initialize its drive independent registers. | |
295 | */ | |
296 | ||
2ed0ef54 | 297 | static int init_chipset_via82cxxx(struct pci_dev *dev) |
1da177e4 | 298 | { |
ee77325b BZ |
299 | struct ide_host *host = pci_get_drvdata(dev); |
300 | struct via82cxxx_dev *vdev = host->host_priv; | |
37525beb | 301 | struct via_isa_bridge *via_config = vdev->via_config; |
1da177e4 | 302 | u8 t, v; |
cd36beec BZ |
303 | u32 u; |
304 | ||
1da177e4 | 305 | /* |
cd36beec | 306 | * Detect cable and configure Clk66 |
1da177e4 | 307 | */ |
cd36beec BZ |
308 | pci_read_config_dword(dev, VIA_UDMA_TIMING, &u); |
309 | ||
310 | via_cable_detect(vdev, u); | |
1da177e4 | 311 | |
75b1d975 | 312 | if (via_config->udma_mask == ATA_UDMA4) { |
7462cbff | 313 | /* Enable Clk66 */ |
7462cbff DD |
314 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008); |
315 | } else if (via_config->flags & VIA_BAD_CLK66) { | |
1da177e4 | 316 | /* Would cause trouble on 596a and 686 */ |
1da177e4 LT |
317 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008); |
318 | } | |
319 | ||
320 | /* | |
321 | * Check whether interfaces are enabled. | |
322 | */ | |
323 | ||
324 | pci_read_config_byte(dev, VIA_IDE_ENABLE, &v); | |
325 | ||
326 | /* | |
327 | * Set up FIFO sizes and thresholds. | |
328 | */ | |
329 | ||
330 | pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t); | |
331 | ||
332 | /* Disable PREQ# till DDACK# */ | |
333 | if (via_config->flags & VIA_BAD_PREQ) { | |
334 | /* Would crash on 586b rev 41 */ | |
335 | t &= 0x7f; | |
336 | } | |
337 | ||
338 | /* Fix FIFO split between channels */ | |
339 | if (via_config->flags & VIA_SET_FIFO) { | |
340 | t &= (t & 0x9f); | |
341 | switch (v & 3) { | |
342 | case 2: t |= 0x00; break; /* 16 on primary */ | |
343 | case 1: t |= 0x60; break; /* 16 on secondary */ | |
344 | case 3: t |= 0x20; break; /* 8 pri 8 sec */ | |
345 | } | |
346 | } | |
347 | ||
348 | pci_write_config_byte(dev, VIA_FIFO_CONFIG, t); | |
349 | ||
1da177e4 LT |
350 | return 0; |
351 | } | |
352 | ||
bdab00b7 BZ |
353 | /* |
354 | * Cable special cases | |
355 | */ | |
356 | ||
1855256c | 357 | static const struct dmi_system_id cable_dmi_table[] = { |
bdab00b7 BZ |
358 | { |
359 | .ident = "Acer Ferrari 3400", | |
360 | .matches = { | |
361 | DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."), | |
362 | DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"), | |
363 | }, | |
364 | }, | |
365 | { } | |
366 | }; | |
367 | ||
58e47bb1 | 368 | static int via_cable_override(struct pci_dev *pdev) |
bdab00b7 BZ |
369 | { |
370 | /* Systems by DMI */ | |
371 | if (dmi_check_system(cable_dmi_table)) | |
372 | return 1; | |
58e47bb1 BZ |
373 | |
374 | /* Arima W730-K8/Targa Visionary 811/... */ | |
375 | if (pdev->subsystem_vendor == 0x161F && | |
376 | pdev->subsystem_device == 0x2032) | |
377 | return 1; | |
378 | ||
bdab00b7 BZ |
379 | return 0; |
380 | } | |
381 | ||
f454cbe8 | 382 | static u8 via82cxxx_cable_detect(ide_hwif_t *hwif) |
bdab00b7 | 383 | { |
36501650 | 384 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
ee77325b BZ |
385 | struct ide_host *host = pci_get_drvdata(pdev); |
386 | struct via82cxxx_dev *vdev = host->host_priv; | |
bdab00b7 | 387 | |
58e47bb1 | 388 | if (via_cable_override(pdev)) |
bdab00b7 BZ |
389 | return ATA_CBL_PATA40_SHORT; |
390 | ||
a13e4865 BZ |
391 | if ((vdev->via_config->flags & VIA_SATA_PATA) && hwif->channel == 0) |
392 | return ATA_CBL_SATA; | |
393 | ||
bdab00b7 BZ |
394 | if ((vdev->via_80w >> hwif->channel) & 1) |
395 | return ATA_CBL_PATA80; | |
396 | else | |
397 | return ATA_CBL_PATA40; | |
398 | } | |
399 | ||
ac95beed BZ |
400 | static const struct ide_port_ops via_port_ops = { |
401 | .set_pio_mode = via_set_pio_mode, | |
402 | .set_dma_mode = via_set_drive, | |
403 | .cable_detect = via82cxxx_cable_detect, | |
404 | }; | |
1da177e4 | 405 | |
fe31edc8 | 406 | static const struct ide_port_info via82cxxx_chipset = { |
ced3ec8a | 407 | .name = DRV_NAME, |
6157332e | 408 | .init_chipset = init_chipset_via82cxxx, |
6157332e | 409 | .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } }, |
ac95beed | 410 | .port_ops = &via_port_ops, |
6157332e | 411 | .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST | |
6157332e | 412 | IDE_HFLAG_POST_SET_MODE | |
5e71d9c5 | 413 | IDE_HFLAG_IO_32BIT, |
6157332e BZ |
414 | .pio_mask = ATA_PIO5, |
415 | .swdma_mask = ATA_SWDMA2, | |
416 | .mwdma_mask = ATA_MWDMA2, | |
1da177e4 LT |
417 | }; |
418 | ||
fe31edc8 | 419 | static int via_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 | 420 | { |
23a1b2a7 AC |
421 | struct pci_dev *isa = NULL; |
422 | struct via_isa_bridge *via_config; | |
ee77325b BZ |
423 | struct via82cxxx_dev *vdev; |
424 | int rc; | |
6157332e | 425 | u8 idx = id->driver_data; |
039788e1 | 426 | struct ide_port_info d; |
6157332e BZ |
427 | |
428 | d = via82cxxx_chipset; | |
8acf28c0 | 429 | |
23a1b2a7 AC |
430 | /* |
431 | * Find the ISA bridge and check we know what it is. | |
432 | */ | |
433 | via_config = via_config_find(&isa); | |
8acf28c0 | 434 | |
37525beb BZ |
435 | /* |
436 | * Print the boot message. | |
437 | */ | |
ced3ec8a | 438 | printk(KERN_INFO DRV_NAME " %s: VIA %s (rev %02x) IDE %sDMA%s\n", |
28cfd8af | 439 | pci_name(dev), via_config->name, isa->revision, |
37525beb BZ |
440 | via_config->udma_mask ? "U" : "MW", |
441 | via_dma[via_config->udma_mask ? | |
28cfd8af | 442 | (fls(via_config->udma_mask) - 1) : 0]); |
37525beb BZ |
443 | |
444 | pci_dev_put(isa); | |
445 | ||
446 | /* | |
447 | * Determine system bus clock. | |
448 | */ | |
449 | via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000; | |
450 | ||
451 | switch (via_clock) { | |
452 | case 33000: via_clock = 33333; break; | |
453 | case 37000: via_clock = 37500; break; | |
454 | case 41000: via_clock = 41666; break; | |
455 | } | |
456 | ||
457 | if (via_clock < 20000 || via_clock > 50000) { | |
ced3ec8a | 458 | printk(KERN_WARNING DRV_NAME ": User given PCI clock speed " |
37525beb | 459 | "impossible (%d), using 33 MHz instead.\n", via_clock); |
37525beb BZ |
460 | via_clock = 33333; |
461 | } | |
462 | ||
42036c85 | 463 | if (idx == 1) |
6157332e | 464 | d.enablebits[1].reg = d.enablebits[0].reg = 0; |
42036c85 BZ |
465 | else |
466 | d.host_flags |= IDE_HFLAG_NO_AUTODMA; | |
467 | ||
468 | if (idx == VIA_IDFLAG_SINGLE) | |
469 | d.host_flags |= IDE_HFLAG_SINGLE; | |
6157332e BZ |
470 | |
471 | if ((via_config->flags & VIA_NO_UNMASK) == 0) | |
472 | d.host_flags |= IDE_HFLAG_UNMASK_IRQS; | |
caea7602 | 473 | |
6157332e | 474 | d.udma_mask = via_config->udma_mask; |
8acf28c0 | 475 | |
ee77325b BZ |
476 | vdev = kzalloc(sizeof(*vdev), GFP_KERNEL); |
477 | if (!vdev) { | |
ced3ec8a BZ |
478 | printk(KERN_ERR DRV_NAME " %s: out of memory :(\n", |
479 | pci_name(dev)); | |
ee77325b BZ |
480 | return -ENOMEM; |
481 | } | |
482 | ||
37525beb BZ |
483 | vdev->via_config = via_config; |
484 | ||
ee77325b BZ |
485 | rc = ide_pci_init_one(dev, &d, vdev); |
486 | if (rc) | |
487 | kfree(vdev); | |
488 | ||
489 | return rc; | |
1da177e4 LT |
490 | } |
491 | ||
fe31edc8 | 492 | static void via_remove(struct pci_dev *dev) |
585f67e7 BZ |
493 | { |
494 | struct ide_host *host = pci_get_drvdata(dev); | |
495 | struct via82cxxx_dev *vdev = host->host_priv; | |
496 | ||
497 | ide_pci_remove(dev); | |
498 | kfree(vdev); | |
499 | } | |
500 | ||
9cbcc5e3 BZ |
501 | static const struct pci_device_id via_pci_tbl[] = { |
502 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 }, | |
503 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 }, | |
84f7e451 | 504 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 }, |
42036c85 | 505 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE }, |
9cbcc5e3 | 506 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 }, |
a354ae87 | 507 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6415), 1 }, |
9cbcc5e3 | 508 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 }, |
1da177e4 LT |
509 | { 0, }, |
510 | }; | |
511 | MODULE_DEVICE_TABLE(pci, via_pci_tbl); | |
512 | ||
a9ab09e2 | 513 | static struct pci_driver via_pci_driver = { |
1da177e4 LT |
514 | .name = "VIA_IDE", |
515 | .id_table = via_pci_tbl, | |
516 | .probe = via_init_one, | |
fe31edc8 | 517 | .remove = via_remove, |
feb22b7f BZ |
518 | .suspend = ide_pci_suspend, |
519 | .resume = ide_pci_resume, | |
1da177e4 LT |
520 | }; |
521 | ||
82ab1eec | 522 | static int __init via_ide_init(void) |
1da177e4 | 523 | { |
a9ab09e2 | 524 | return ide_pci_register_driver(&via_pci_driver); |
1da177e4 LT |
525 | } |
526 | ||
585f67e7 BZ |
527 | static void __exit via_ide_exit(void) |
528 | { | |
a9ab09e2 | 529 | pci_unregister_driver(&via_pci_driver); |
585f67e7 BZ |
530 | } |
531 | ||
1da177e4 | 532 | module_init(via_ide_init); |
585f67e7 | 533 | module_exit(via_ide_exit); |
1da177e4 | 534 | |
42036c85 | 535 | MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick"); |
1da177e4 LT |
536 | MODULE_DESCRIPTION("PCI driver module for VIA IDE"); |
537 | MODULE_LICENSE("GPL"); |