[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / via82cxxx.c

/*
 * VIA IDE driver for Linux. Supported southbridges:
 *
 *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
 *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
 *   vt8235, vt8237, vt8237a
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
 *
 * Based on the work of:
 *	Michel Aubry
 *	Jeff Garzik
 *	Andre Hedrick
 *
 * Documentation:
 *	Obsolete device documentation publically available from via.com.tw
 *	Current device documentation available under NDA only
 */

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/dmi.h>

#ifdef CONFIG_PPC_CHRP
#include <asm/processor.h>
#endif

#define DRV_NAME "via82cxxx"

#define VIA_IDE_ENABLE		0x40
#define VIA_IDE_CONFIG		0x41
#define VIA_FIFO_CONFIG		0x43
#define VIA_MISC_1		0x44
#define VIA_MISC_2		0x45
#define VIA_MISC_3		0x46
#define VIA_DRIVE_TIMING	0x48
#define VIA_8BIT_TIMING		0x4e
#define VIA_ADDRESS_SETUP	0x4c
#define VIA_UDMA_TIMING		0x50

#define VIA_BAD_PREQ		0x01 /* Crashes if PREQ# till DDACK# set */
#define VIA_BAD_CLK66		0x02 /* 66 MHz clock doesn't work correctly */
#define VIA_SET_FIFO		0x04 /* Needs to have FIFO split set */
#define VIA_NO_UNMASK		0x08 /* Doesn't work with IRQ unmasking on */
#define VIA_BAD_ID		0x10 /* Has wrong vendor ID (0x1107) */
#define VIA_BAD_AST		0x20 /* Don't touch Address Setup Timing */
#define VIA_SATA_PATA		0x80 /* SATA/PATA combined configuration */

enum {
	VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */
};

/*
 * VIA SouthBridge chips.
 */

static struct via_isa_bridge {
	char *name;
	u16 id;
	u8 rev_min;
	u8 rev_max;
	u8 udma_mask;
	u8 flags;
} via_isa_bridges[] = {
	{ "vx855",	PCI_DEVICE_ID_VIA_VX855,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
	{ "vx800",	PCI_DEVICE_ID_VIA_VX800,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
	{ "cx700",	PCI_DEVICE_ID_VIA_CX700,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
	{ "vt8261",	PCI_DEVICE_ID_VIA_8261,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237s",	PCI_DEVICE_ID_VIA_8237S,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt6415",	PCI_DEVICE_ID_VIA_6410,     0x00, 0xff, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8251",	PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237a",	PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233a",	PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233c",	PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, ATA_UDMA5, },
	{ "vt8233",	PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, ATA_UDMA5, },
	{ "vt8231",	PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, ATA_UDMA5, },
	{ "vt82c686b",	PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, ATA_UDMA5, },
	{ "vt82c686a",	PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c686",	PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c596b",	PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c596a",	PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586a",	PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586",	PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f,      0x00, VIA_SET_FIFO },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
	{ "vtxxxx",	PCI_DEVICE_ID_VIA_ANON,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ NULL }
};

static unsigned int via_clock;
static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };

struct via82cxxx_dev
{
	struct via_isa_bridge *via_config;
	unsigned int via_80w;
};

/**
 *	via_set_speed			-	write timing registers
 *	@dev: PCI device
 *	@dn: device
 *	@timing: IDE timing data to use
 *
 *	via_set_speed writes timing values to the chipset registers
 */

static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	struct ide_host *host = pci_get_drvdata(dev);
	struct via82cxxx_dev *vdev = host->host_priv;
	u8 t;

	if (~vdev->via_config->flags & VIA_BAD_AST) {
		pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
		t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
		pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	}

	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
		((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
		((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
	case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break;
	case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
	case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
	}

	/* Set UDMA unless device is not UDMA capable */
	if (vdev->via_config->udma_mask) {
		u8 udma_etc;

		pci_read_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, &udma_etc);

		/* clear transfer mode bit */
		udma_etc &= ~0x20;

		if (timing->udma) {
			/* preserve 80-wire cable detection bit */
			udma_etc &= 0x10;
			udma_etc |= t;
		}

		pci_write_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, udma_etc);
	}
}

/**
 *	via_set_drive		-	configure transfer mode
 *	@hwif: port
 *	@drive: Drive to set up
 *
 *	via_set_drive() computes timing values configures the chipset to
 *	a desired transfer mode.  It also can be called by upper layers.
 */

static void via_set_drive(ide_hwif_t *hwif, ide_drive_t *drive)
{
	ide_drive_t *peer = ide_get_pair_dev(drive);
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	struct ide_host *host = pci_get_drvdata(dev);
	struct via82cxxx_dev *vdev = host->host_priv;
	struct ide_timing t, p;
	unsigned int T, UT;
	const u8 speed = drive->dma_mode;

	T = 1000000000 / via_clock;

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: UT = T;   break;
	case ATA_UDMA4: UT = T/2; break;
	case ATA_UDMA5: UT = T/3; break;
	case ATA_UDMA6: UT = T/4; break;
	default:	UT = T;
	}

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer) {
		ide_timing_compute(peer, peer->pio_mode, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	via_set_speed(hwif, drive->dn, &t);
}

/**
 *	via_set_pio_mode	-	set host controller for PIO mode
 *	@hwif: port
 *	@drive: drive
 *
 *	A callback from the upper layers for PIO-only tuning.
 */

static void via_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	drive->dma_mode = drive->pio_mode;
	via_set_drive(hwif, drive);
}

static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
{
	struct via_isa_bridge *via_config;

	for (via_config = via_isa_bridges;
	     via_config->id != PCI_DEVICE_ID_VIA_ANON; via_config++)
		if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
			!!(via_config->flags & VIA_BAD_ID),
			via_config->id, NULL))) {

			if ((*isa)->revision >= via_config->rev_min &&
			    (*isa)->revision <= via_config->rev_max)
				break;
			pci_dev_put(*isa);
		}

	return via_config;
}

/*
 * Check and handle 80-wire cable presence
 */
static void via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
{
	int i;

	switch (vdev->via_config->udma_mask) {
		case ATA_UDMA4:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> (i & 16)) & 8) &&
				    ((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 2)) {
					/*
					 * 2x PCI clock and
					 * UDMA w/ < 3T/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA5:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 4))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA6:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 6))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;
	}
}

/**
 *	init_chipset_via82cxxx	-	initialization handler
 *	@dev: PCI device
 *
 *	The initialization callback. Here we determine the IDE chip type
 *	and initialize its drive independent registers.
 */

static int init_chipset_via82cxxx(struct pci_dev *dev)
{
	struct ide_host *host = pci_get_drvdata(dev);
	struct via82cxxx_dev *vdev = host->host_priv;
	struct via_isa_bridge *via_config = vdev->via_config;
	u8 t, v;
	u32 u;

	/*
	 * Detect cable and configure Clk66
	 */
	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);

	via_cable_detect(vdev, u);

	if (via_config->udma_mask == ATA_UDMA4) {
		/* Enable Clk66 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
	} else if (via_config->flags & VIA_BAD_CLK66) {
		/* Would cause trouble on 596a and 686 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	}

	/*
	 * Check whether interfaces are enabled.
	 */

	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);

	/*
	 * Set up FIFO sizes and thresholds.
	 */

	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);

	/* Disable PREQ# till DDACK# */
	if (via_config->flags & VIA_BAD_PREQ) {
		/* Would crash on 586b rev 41 */
		t &= 0x7f;
	}

	/* Fix FIFO split between channels */
	if (via_config->flags & VIA_SET_FIFO) {
		t &= (t & 0x9f);
		switch (v & 3) {
			case 2: t |= 0x00; break;	/* 16 on primary */
			case 1: t |= 0x60; break;	/* 16 on secondary */
			case 3: t |= 0x20; break;	/* 8 pri 8 sec */
		}
	}

	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);

	return 0;
}

/*
 *	Cable special cases
 */

static const struct dmi_system_id cable_dmi_table[] = {
	{
		.ident = "Acer Ferrari 3400",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
			DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
		},
	},
	{ }
};

static int via_cable_override(struct pci_dev *pdev)
{
	/* Systems by DMI */
	if (dmi_check_system(cable_dmi_table))
		return 1;

	/* Arima W730-K8/Targa Visionary 811/... */
	if (pdev->subsystem_vendor == 0x161F &&
	    pdev->subsystem_device == 0x2032)
		return 1;

	return 0;
}

static u8 via82cxxx_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	struct ide_host *host = pci_get_drvdata(pdev);
	struct via82cxxx_dev *vdev = host->host_priv;

	if (via_cable_override(pdev))
		return ATA_CBL_PATA40_SHORT;

	if ((vdev->via_config->flags & VIA_SATA_PATA) && hwif->channel == 0)
		return ATA_CBL_SATA;

	if ((vdev->via_80w >> hwif->channel) & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static const struct ide_port_ops via_port_ops = {
	.set_pio_mode		= via_set_pio_mode,
	.set_dma_mode		= via_set_drive,
	.cable_detect		= via82cxxx_cable_detect,
};

static const struct ide_port_info via82cxxx_chipset __devinitdata = {
	.name		= DRV_NAME,
	.init_chipset	= init_chipset_via82cxxx,
	.enablebits	= { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
	.port_ops	= &via_port_ops,
	.host_flags	= IDE_HFLAG_PIO_NO_BLACKLIST |
			  IDE_HFLAG_POST_SET_MODE |
			  IDE_HFLAG_IO_32BIT,
	.pio_mask	= ATA_PIO5,
	.swdma_mask	= ATA_SWDMA2,
	.mwdma_mask	= ATA_MWDMA2,
};

static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct pci_dev *isa = NULL;
	struct via_isa_bridge *via_config;
	struct via82cxxx_dev *vdev;
	int rc;
	u8 idx = id->driver_data;
	struct ide_port_info d;

	d = via82cxxx_chipset;

	/*
	 * Find the ISA bridge and check we know what it is.
	 */
	via_config = via_config_find(&isa);

	/*
	 * Print the boot message.
	 */
	printk(KERN_INFO DRV_NAME " %s: VIA %s (rev %02x) IDE %sDMA%s\n",
		pci_name(dev), via_config->name, isa->revision,
		via_config->udma_mask ? "U" : "MW",
		via_dma[via_config->udma_mask ?
			(fls(via_config->udma_mask) - 1) : 0]);

	pci_dev_put(isa);

	/*
	 * Determine system bus clock.
	 */
	via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;

	switch (via_clock) {
	case 33000: via_clock = 33333; break;
	case 37000: via_clock = 37500; break;
	case 41000: via_clock = 41666; break;
	}

	if (via_clock < 20000 || via_clock > 50000) {
		printk(KERN_WARNING DRV_NAME ": User given PCI clock speed "
			"impossible (%d), using 33 MHz instead.\n", via_clock);
		via_clock = 33333;
	}

	if (idx == 1)
		d.enablebits[1].reg = d.enablebits[0].reg = 0;
	else
		d.host_flags |= IDE_HFLAG_NO_AUTODMA;

	if (idx == VIA_IDFLAG_SINGLE)
		d.host_flags |= IDE_HFLAG_SINGLE;

	if ((via_config->flags & VIA_NO_UNMASK) == 0)
		d.host_flags |= IDE_HFLAG_UNMASK_IRQS;

	d.udma_mask = via_config->udma_mask;

	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
	if (!vdev) {
		printk(KERN_ERR DRV_NAME " %s: out of memory :(\n",
			pci_name(dev));
		return -ENOMEM;
	}

	vdev->via_config = via_config;

	rc = ide_pci_init_one(dev, &d, vdev);
	if (rc)
		kfree(vdev);

	return rc;
}

static void __devexit via_remove(struct pci_dev *dev)
{
	struct ide_host *host = pci_get_drvdata(dev);
	struct via82cxxx_dev *vdev = host->host_priv;

	ide_pci_remove(dev);
	kfree(vdev);
}

static const struct pci_device_id via_pci_tbl[] = {
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1),  0 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1),  0 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410),      1 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6415),      1 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, via_pci_tbl);

static struct pci_driver via_pci_driver = {
	.name 		= "VIA_IDE",
	.id_table 	= via_pci_tbl,
	.probe 		= via_init_one,
	.remove		= __devexit_p(via_remove),
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init via_ide_init(void)
{
	return ide_pci_register_driver(&via_pci_driver);
}

static void __exit via_ide_exit(void)
{
	pci_unregister_driver(&via_pci_driver);
}

module_init(via_ide_init);
module_exit(via_ide_exit);

MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for VIA IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* VIA IDE driver for Linux. Supported southbridges:
	3	*
	4	* vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
	5	* vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
a7dec1e0	6	* vt8235, vt8237, vt8237a
1da177e4 LT	7	*
1da177e4 LT	8	* Copyright (c) 2000-2002 Vojtech Pavlik
42036c85	9	* Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
1da177e4 LT	10	*
	11	* Based on the work of:
	12	* Michel Aubry
	13	* Jeff Garzik
	14	* Andre Hedrick
	15	*
	16	* Documentation:
	17	* Obsolete device documentation publically available from via.com.tw
	18	* Current device documentation available under NDA only
	19	*/
	20
	21	/*
	22	* This program is free software; you can redistribute it and/or modify it
	23	* under the terms of the GNU General Public License version 2 as published by
	24	* the Free Software Foundation.
	25	*/
	26
1da177e4 LT	27	#include <linux/module.h>
1da177e4 LT	28	#include <linux/kernel.h>
1da177e4 LT	29	#include <linux/pci.h>
	30	#include <linux/init.h>
	31	#include <linux/ide.h>
bdab00b7 BZ	32	#include <linux/dmi.h>
bdab00b7 BZ	33
74a9d5f1	34	#ifdef CONFIG_PPC_CHRP
1da177e4 LT	35	#include <asm/processor.h>
	36	#endif
	37
ced3ec8a BZ	38	#define DRV_NAME "via82cxxx"
ced3ec8a BZ	39
1da177e4 LT	40	#define VIA_IDE_ENABLE 0x40
	41	#define VIA_IDE_CONFIG 0x41
	42	#define VIA_FIFO_CONFIG 0x43
	43	#define VIA_MISC_1 0x44
	44	#define VIA_MISC_2 0x45
	45	#define VIA_MISC_3 0x46
	46	#define VIA_DRIVE_TIMING 0x48
	47	#define VIA_8BIT_TIMING 0x4e
	48	#define VIA_ADDRESS_SETUP 0x4c
	49	#define VIA_UDMA_TIMING 0x50
	50
75b1d975 BZ	51	#define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
	52	#define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
	53	#define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
	54	#define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
	55	#define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
	56	#define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
a13e4865	57	#define VIA_SATA_PATA 0x80 /* SATA/PATA combined configuration */
1da177e4	58
42036c85 BZ	59	enum {
	60	VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */
	61	};
	62
1da177e4 LT	63	/*
	64	* VIA SouthBridge chips.
	65	*/
	66
	67	static struct via_isa_bridge {
	68	char *name;
	69	u16 id;
	70	u8 rev_min;
	71	u8 rev_max;
75b1d975 BZ	72	u8 udma_mask;
75b1d975 BZ	73	u8 flags;
1da177e4	74	} via_isa_bridges[] = {
a13e4865 BZ	75	{ "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST \| VIA_SATA_PATA },
	76	{ "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST \| VIA_SATA_PATA },
	77	{ "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST \| VIA_SATA_PATA },
5b6c82ea	78	{ "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
75b1d975 BZ	79	{ "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
75b1d975 BZ	80	{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
a354ae87	81	{ "vt6415", PCI_DEVICE_ID_VIA_6410, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST },
75b1d975 BZ	82	{ "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	83	{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	84	{ "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	85	{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	86	{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	87	{ "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
	88	{ "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
	89	{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
	90	{ "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
	91	{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
	92	{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	93	{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
	94	{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	95	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	96	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO \| VIA_BAD_PREQ },
	97	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	98	{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	99	{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
	100	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK },
	101	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK \| VIA_BAD_ID },
5b6c82ea	102	{ "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
1da177e4 LT	103	{ NULL }
	104	};
	105
1da177e4	106	static unsigned int via_clock;
75b1d975	107	static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
1da177e4	108
7462cbff DD	109	struct via82cxxx_dev
	110	{
	111	struct via_isa_bridge *via_config;
	112	unsigned int via_80w;
	113	};
	114
1da177e4 LT	115	/**
	116	* via_set_speed - write timing registers
	117	* @dev: PCI device
	118	* @dn: device
	119	* @timing: IDE timing data to use
	120	*
	121	* via_set_speed writes timing values to the chipset registers
	122	*/
	123
7462cbff	124	static void via_set_speed(ide_hwif_t hwif, u8 dn, struct ide_timing timing)
1da177e4	125	{
36501650	126	struct pci_dev *dev = to_pci_dev(hwif->dev);
ee77325b BZ	127	struct ide_host *host = pci_get_drvdata(dev);
ee77325b BZ	128	struct via82cxxx_dev *vdev = host->host_priv;
1da177e4 LT	129	u8 t;
1da177e4 LT	130
7462cbff	131	if (~vdev->via_config->flags & VIA_BAD_AST) {
1da177e4	132	pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
d6cddd3c	133	t = (t & ~(3 << ((3 - dn) << 1))) \| ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
1da177e4 LT	134	pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	135	}
	136
	137	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
d6cddd3c	138	((clamp_val(timing->act8b, 1, 16) - 1) << 4) \| (clamp_val(timing->rec8b, 1, 16) - 1));
1da177e4 LT	139
1da177e4 LT	140	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
d6cddd3c	141	((clamp_val(timing->active, 1, 16) - 1) << 4) \| (clamp_val(timing->recover, 1, 16) - 1));
1da177e4	142
75b1d975	143	switch (vdev->via_config->udma_mask) {
d6cddd3c HH	144	case ATA_UDMA2: t = timing->udma ? (0xe0 \| (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
	145	case ATA_UDMA4: t = timing->udma ? (0xe8 \| (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break;
	146	case ATA_UDMA5: t = timing->udma ? (0xe0 \| (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
	147	case ATA_UDMA6: t = timing->udma ? (0xe0 \| (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
1da177e4 LT	148	}
1da177e4 LT	149
68d0a036 BZ	150	/* Set UDMA unless device is not UDMA capable */
	151	if (vdev->via_config->udma_mask) {
	152	u8 udma_etc;
	153
	154	pci_read_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, &udma_etc);
	155
	156	/* clear transfer mode bit */
	157	udma_etc &= ~0x20;
	158
	159	if (timing->udma) {
	160	/* preserve 80-wire cable detection bit */
	161	udma_etc &= 0x10;
	162	udma_etc \|= t;
	163	}
	164
	165	pci_write_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, udma_etc);
	166	}
1da177e4 LT	167	}
	168
	169	/**
	170	* via_set_drive - configure transfer mode
8776168c	171	* @hwif: port
1da177e4	172	* @drive: Drive to set up
1da177e4	173	*
88b2b32b BZ	174	* via_set_drive() computes timing values configures the chipset to
88b2b32b BZ	175	* a desired transfer mode. It also can be called by upper layers.
1da177e4 LT	176	*/
1da177e4 LT	177
8776168c	178	static void via_set_drive(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	179	{
7e59ea21	180	ide_drive_t *peer = ide_get_pair_dev(drive);
36501650	181	struct pci_dev *dev = to_pci_dev(hwif->dev);
ee77325b BZ	182	struct ide_host *host = pci_get_drvdata(dev);
ee77325b BZ	183	struct via82cxxx_dev *vdev = host->host_priv;
1da177e4 LT	184	struct ide_timing t, p;
1da177e4 LT	185	unsigned int T, UT;
8776168c	186	const u8 speed = drive->dma_mode;
1da177e4	187
1da177e4 LT	188	T = 1000000000 / via_clock;
1da177e4 LT	189
75b1d975 BZ	190	switch (vdev->via_config->udma_mask) {
	191	case ATA_UDMA2: UT = T; break;
	192	case ATA_UDMA4: UT = T/2; break;
	193	case ATA_UDMA5: UT = T/3; break;
	194	case ATA_UDMA6: UT = T/4; break;
	195	default: UT = T;
1da177e4 LT	196	}
	197
	198	ide_timing_compute(drive, speed, &t, T, UT);
	199
7e59ea21	200	if (peer) {
f0e5f62d	201	ide_timing_compute(peer, peer->pio_mode, &p, T, UT);
1da177e4 LT	202	ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	203	}
	204
898ec223	205	via_set_speed(hwif, drive->dn, &t);
1da177e4 LT	206	}
	207
	208	/**
88b2b32b	209	* via_set_pio_mode - set host controller for PIO mode
e085b3ca	210	* @hwif: port
26bcb879	211	* @drive: drive
1da177e4 LT	212	*
	213	* A callback from the upper layers for PIO-only tuning.
	214	*/
	215
e085b3ca	216	static void via_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	217	{
8776168c BZ	218	drive->dma_mode = drive->pio_mode;
8776168c BZ	219	via_set_drive(hwif, drive);
1da177e4 LT	220	}
1da177e4 LT	221
7462cbff DD	222	static struct via_isa_bridge via_config_find(struct pci_dev *isa)
	223	{
	224	struct via_isa_bridge *via_config;
7462cbff	225
5b6c82ea BZ	226	for (via_config = via_isa_bridges;
5b6c82ea BZ	227	via_config->id != PCI_DEVICE_ID_VIA_ANON; via_config++)
652aa162	228	if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
7462cbff DD	229	!!(via_config->flags & VIA_BAD_ID),
	230	via_config->id, NULL))) {
	231
44c10138 AK	232	if ((*isa)->revision >= via_config->rev_min &&
44c10138 AK	233	(*isa)->revision <= via_config->rev_max)
7462cbff	234	break;
652aa162	235	pci_dev_put(*isa);
7462cbff DD	236	}
	237
	238	return via_config;
1da177e4 LT	239	}
1da177e4 LT	240
cd36beec BZ	241	/*
	242	* Check and handle 80-wire cable presence
	243	*/
feb22b7f	244	static void via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
cd36beec BZ	245	{
	246	int i;
	247
75b1d975 BZ	248	switch (vdev->via_config->udma_mask) {
75b1d975 BZ	249	case ATA_UDMA4:
cd36beec BZ	250	for (i = 24; i >= 0; i -= 8)
	251	if (((u >> (i & 16)) & 8) &&
	252	((u >> i) & 0x20) &&
	253	(((u >> i) & 7) < 2)) {
	254	/*
	255	* 2x PCI clock and
	256	* UDMA w/ < 3T/cycle
	257	*/
	258	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	259	}
	260	break;
	261
75b1d975	262	case ATA_UDMA5:
cd36beec BZ	263	for (i = 24; i >= 0; i -= 8)
	264	if (((u >> i) & 0x10) \|\|
	265	(((u >> i) & 0x20) &&
	266	(((u >> i) & 7) < 4))) {
	267	/* BIOS 80-wire bit or
	268	* UDMA w/ < 60ns/cycle
	269	*/
	270	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	271	}
	272	break;
	273
75b1d975	274	case ATA_UDMA6:
cd36beec BZ	275	for (i = 24; i >= 0; i -= 8)
	276	if (((u >> i) & 0x10) \|\|
	277	(((u >> i) & 0x20) &&
	278	(((u >> i) & 7) < 6))) {
	279	/* BIOS 80-wire bit or
	280	* UDMA w/ < 60ns/cycle
	281	*/
	282	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	283	}
	284	break;
	285	}
	286	}
	287
1da177e4 LT	288	/**
	289	* init_chipset_via82cxxx - initialization handler
	290	* @dev: PCI device
1da177e4 LT	291	*
	292	* The initialization callback. Here we determine the IDE chip type
	293	* and initialize its drive independent registers.
	294	*/
	295
2ed0ef54	296	static int init_chipset_via82cxxx(struct pci_dev *dev)
1da177e4	297	{
ee77325b BZ	298	struct ide_host *host = pci_get_drvdata(dev);
ee77325b BZ	299	struct via82cxxx_dev *vdev = host->host_priv;
37525beb	300	struct via_isa_bridge *via_config = vdev->via_config;
1da177e4	301	u8 t, v;
cd36beec BZ	302	u32 u;
cd36beec BZ	303
1da177e4	304	/*
cd36beec	305	* Detect cable and configure Clk66
1da177e4	306	*/
cd36beec BZ	307	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
	308
	309	via_cable_detect(vdev, u);
1da177e4	310
75b1d975	311	if (via_config->udma_mask == ATA_UDMA4) {
7462cbff	312	/* Enable Clk66 */
7462cbff DD	313	pci_write_config_dword(dev, VIA_UDMA_TIMING, u\|0x80008);
7462cbff DD	314	} else if (via_config->flags & VIA_BAD_CLK66) {
1da177e4	315	/* Would cause trouble on 596a and 686 */
1da177e4 LT	316	pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	317	}
	318
	319	/*
	320	* Check whether interfaces are enabled.
	321	*/
	322
	323	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
	324
	325	/*
	326	* Set up FIFO sizes and thresholds.
	327	*/
	328
	329	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
	330
	331	/* Disable PREQ# till DDACK# */
	332	if (via_config->flags & VIA_BAD_PREQ) {
	333	/* Would crash on 586b rev 41 */
	334	t &= 0x7f;
	335	}
	336
	337	/* Fix FIFO split between channels */
	338	if (via_config->flags & VIA_SET_FIFO) {
	339	t &= (t & 0x9f);
	340	switch (v & 3) {
	341	case 2: t \|= 0x00; break; /* 16 on primary */
	342	case 1: t \|= 0x60; break; /* 16 on secondary */
	343	case 3: t \|= 0x20; break; /* 8 pri 8 sec */
	344	}
	345	}
	346
	347	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
	348
1da177e4 LT	349	return 0;
	350	}
	351
bdab00b7 BZ	352	/*
	353	* Cable special cases
	354	*/
	355
1855256c	356	static const struct dmi_system_id cable_dmi_table[] = {
bdab00b7 BZ	357	{
	358	.ident = "Acer Ferrari 3400",
	359	.matches = {
	360	DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
	361	DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
	362	},
	363	},
	364	{ }
	365	};
	366
58e47bb1	367	static int via_cable_override(struct pci_dev *pdev)
bdab00b7 BZ	368	{
	369	/* Systems by DMI */
	370	if (dmi_check_system(cable_dmi_table))
	371	return 1;
58e47bb1 BZ	372
	373	/* Arima W730-K8/Targa Visionary 811/... */
	374	if (pdev->subsystem_vendor == 0x161F &&
	375	pdev->subsystem_device == 0x2032)
	376	return 1;
	377
bdab00b7 BZ	378	return 0;
	379	}
	380
f454cbe8	381	static u8 via82cxxx_cable_detect(ide_hwif_t *hwif)
bdab00b7	382	{
36501650	383	struct pci_dev *pdev = to_pci_dev(hwif->dev);
ee77325b BZ	384	struct ide_host *host = pci_get_drvdata(pdev);
ee77325b BZ	385	struct via82cxxx_dev *vdev = host->host_priv;
bdab00b7	386
58e47bb1	387	if (via_cable_override(pdev))
bdab00b7 BZ	388	return ATA_CBL_PATA40_SHORT;
bdab00b7 BZ	389
a13e4865 BZ	390	if ((vdev->via_config->flags & VIA_SATA_PATA) && hwif->channel == 0)
	391	return ATA_CBL_SATA;
	392
bdab00b7 BZ	393	if ((vdev->via_80w >> hwif->channel) & 1)
	394	return ATA_CBL_PATA80;
	395	else
	396	return ATA_CBL_PATA40;
	397	}
	398
ac95beed BZ	399	static const struct ide_port_ops via_port_ops = {
	400	.set_pio_mode = via_set_pio_mode,
	401	.set_dma_mode = via_set_drive,
	402	.cable_detect = via82cxxx_cable_detect,
	403	};
1da177e4	404
85620436	405	static const struct ide_port_info via82cxxx_chipset __devinitdata = {
ced3ec8a	406	.name = DRV_NAME,
6157332e	407	.init_chipset = init_chipset_via82cxxx,
6157332e	408	.enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
ac95beed	409	.port_ops = &via_port_ops,
6157332e	410	.host_flags = IDE_HFLAG_PIO_NO_BLACKLIST \|
6157332e	411	IDE_HFLAG_POST_SET_MODE \|
5e71d9c5	412	IDE_HFLAG_IO_32BIT,
6157332e BZ	413	.pio_mask = ATA_PIO5,
	414	.swdma_mask = ATA_SWDMA2,
	415	.mwdma_mask = ATA_MWDMA2,
1da177e4 LT	416	};
	417
	418	static int __devinit via_init_one(struct pci_dev dev, const struct pci_device_id id)
	419	{
23a1b2a7 AC	420	struct pci_dev *isa = NULL;
23a1b2a7 AC	421	struct via_isa_bridge *via_config;
ee77325b BZ	422	struct via82cxxx_dev *vdev;
ee77325b BZ	423	int rc;
6157332e	424	u8 idx = id->driver_data;
039788e1	425	struct ide_port_info d;
6157332e BZ	426
6157332e BZ	427	d = via82cxxx_chipset;
8acf28c0	428
23a1b2a7 AC	429	/*
	430	* Find the ISA bridge and check we know what it is.
	431	*/
	432	via_config = via_config_find(&isa);
8acf28c0	433
37525beb BZ	434	/*
	435	* Print the boot message.
	436	*/
ced3ec8a	437	printk(KERN_INFO DRV_NAME " %s: VIA %s (rev %02x) IDE %sDMA%s\n",
28cfd8af	438	pci_name(dev), via_config->name, isa->revision,
37525beb BZ	439	via_config->udma_mask ? "U" : "MW",
37525beb BZ	440	via_dma[via_config->udma_mask ?
28cfd8af	441	(fls(via_config->udma_mask) - 1) : 0]);
37525beb BZ	442
	443	pci_dev_put(isa);
	444
	445	/*
	446	* Determine system bus clock.
	447	*/
	448	via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;
	449
	450	switch (via_clock) {
	451	case 33000: via_clock = 33333; break;
	452	case 37000: via_clock = 37500; break;
	453	case 41000: via_clock = 41666; break;
	454	}
	455
	456	if (via_clock < 20000 \|\| via_clock > 50000) {
ced3ec8a	457	printk(KERN_WARNING DRV_NAME ": User given PCI clock speed "
37525beb	458	"impossible (%d), using 33 MHz instead.\n", via_clock);
37525beb BZ	459	via_clock = 33333;
	460	}
	461
42036c85	462	if (idx == 1)
6157332e	463	d.enablebits[1].reg = d.enablebits[0].reg = 0;
42036c85 BZ	464	else
	465	d.host_flags \|= IDE_HFLAG_NO_AUTODMA;
	466
	467	if (idx == VIA_IDFLAG_SINGLE)
	468	d.host_flags \|= IDE_HFLAG_SINGLE;
6157332e BZ	469
	470	if ((via_config->flags & VIA_NO_UNMASK) == 0)
	471	d.host_flags \|= IDE_HFLAG_UNMASK_IRQS;
caea7602	472
6157332e	473	d.udma_mask = via_config->udma_mask;
8acf28c0	474
ee77325b BZ	475	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
ee77325b BZ	476	if (!vdev) {
ced3ec8a BZ	477	printk(KERN_ERR DRV_NAME " %s: out of memory :(\n",
ced3ec8a BZ	478	pci_name(dev));
ee77325b BZ	479	return -ENOMEM;
	480	}
	481
37525beb BZ	482	vdev->via_config = via_config;
37525beb BZ	483
ee77325b BZ	484	rc = ide_pci_init_one(dev, &d, vdev);
	485	if (rc)
	486	kfree(vdev);
	487
	488	return rc;
1da177e4 LT	489	}
1da177e4 LT	490
585f67e7 BZ	491	static void __devexit via_remove(struct pci_dev *dev)
	492	{
	493	struct ide_host *host = pci_get_drvdata(dev);
	494	struct via82cxxx_dev *vdev = host->host_priv;
	495
	496	ide_pci_remove(dev);
	497	kfree(vdev);
	498	}
	499
9cbcc5e3 BZ	500	static const struct pci_device_id via_pci_tbl[] = {
	501	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 },
	502	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 },
84f7e451	503	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 },
42036c85	504	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE },
9cbcc5e3	505	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 },
a354ae87	506	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6415), 1 },
9cbcc5e3	507	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
1da177e4 LT	508	{ 0, },
	509	};
	510	MODULE_DEVICE_TABLE(pci, via_pci_tbl);
	511
a9ab09e2	512	static struct pci_driver via_pci_driver = {
1da177e4 LT	513	.name = "VIA_IDE",
	514	.id_table = via_pci_tbl,
	515	.probe = via_init_one,
a69999e2	516	.remove = __devexit_p(via_remove),
feb22b7f BZ	517	.suspend = ide_pci_suspend,
feb22b7f BZ	518	.resume = ide_pci_resume,
1da177e4 LT	519	};
1da177e4 LT	520
82ab1eec	521	static int __init via_ide_init(void)
1da177e4	522	{
a9ab09e2	523	return ide_pci_register_driver(&via_pci_driver);
1da177e4 LT	524	}
1da177e4 LT	525
585f67e7 BZ	526	static void __exit via_ide_exit(void)
585f67e7 BZ	527	{
a9ab09e2	528	pci_unregister_driver(&via_pci_driver);
585f67e7 BZ	529	}
585f67e7 BZ	530
1da177e4	531	module_init(via_ide_init);
585f67e7	532	module_exit(via_ide_exit);
1da177e4	533
42036c85	534	MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick");
1da177e4 LT	535	MODULE_DESCRIPTION("PCI driver module for VIA IDE");
1da177e4 LT	536	MODULE_LICENSE("GPL");