[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / via82cxxx.c

/*
 * VIA IDE driver for Linux. Supported southbridges:
 *
 *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
 *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
 *   vt8235, vt8237, vt8237a
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
 *
 * Based on the work of:
 *	Michel Aubry
 *	Jeff Garzik
 *	Andre Hedrick
 *
 * Documentation:
 *	Obsolete device documentation publically available from via.com.tw
 *	Current device documentation available under NDA only
 */

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/dmi.h>

#ifdef CONFIG_PPC_CHRP
#include <asm/processor.h>
#endif

#define DRV_NAME "via82cxxx"

#define VIA_IDE_ENABLE		0x40
#define VIA_IDE_CONFIG		0x41
#define VIA_FIFO_CONFIG		0x43
#define VIA_MISC_1		0x44
#define VIA_MISC_2		0x45
#define VIA_MISC_3		0x46
#define VIA_DRIVE_TIMING	0x48
#define VIA_8BIT_TIMING		0x4e
#define VIA_ADDRESS_SETUP	0x4c
#define VIA_UDMA_TIMING		0x50

#define VIA_BAD_PREQ		0x01 /* Crashes if PREQ# till DDACK# set */
#define VIA_BAD_CLK66		0x02 /* 66 MHz clock doesn't work correctly */
#define VIA_SET_FIFO		0x04 /* Needs to have FIFO split set */
#define VIA_NO_UNMASK		0x08 /* Doesn't work with IRQ unmasking on */
#define VIA_BAD_ID		0x10 /* Has wrong vendor ID (0x1107) */
#define VIA_BAD_AST		0x20 /* Don't touch Address Setup Timing */
#define VIA_SATA_PATA		0x80 /* SATA/PATA combined configuration */

enum {
	VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */
};

/*
 * VIA SouthBridge chips.
 */

static struct via_isa_bridge {
	char *name;
	u16 id;
	u8 rev_min;
	u8 rev_max;
	u8 udma_mask;
	u8 flags;
} via_isa_bridges[] = {
	{ "vx855",	PCI_DEVICE_ID_VIA_VX855,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
	{ "vx800",	PCI_DEVICE_ID_VIA_VX800,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
	{ "cx700",	PCI_DEVICE_ID_VIA_CX700,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
	{ "vt8261",	PCI_DEVICE_ID_VIA_8261,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237s",	PCI_DEVICE_ID_VIA_8237S,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt6415",	PCI_DEVICE_ID_VIA_6410,     0x00, 0xff, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8251",	PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237a",	PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233a",	PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233c",	PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, ATA_UDMA5, },
	{ "vt8233",	PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, ATA_UDMA5, },
	{ "vt8231",	PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, ATA_UDMA5, },
	{ "vt82c686b",	PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, ATA_UDMA5, },
	{ "vt82c686a",	PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c686",	PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c596b",	PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c596a",	PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586a",	PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586",	PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f,      0x00, VIA_SET_FIFO },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
	{ "vtxxxx",	PCI_DEVICE_ID_VIA_ANON,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ NULL }
};

static unsigned int via_clock;
static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };

struct via82cxxx_dev
{
	struct via_isa_bridge *via_config;
	unsigned int via_80w;
	u8 cached_device[2];
};

/**
 *	via_set_speed			-	write timing registers
 *	@dev: PCI device
 *	@dn: device
 *	@timing: IDE timing data to use
 *
 *	via_set_speed writes timing values to the chipset registers
 */

static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	struct ide_host *host = pci_get_drvdata(dev);
	struct via82cxxx_dev *vdev = host->host_priv;
	u8 t;

	if (~vdev->via_config->flags & VIA_BAD_AST) {
		pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
		t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
		pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	}

	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
		((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
		((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
	case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break;
	case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
	case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
	default: return;
	}

	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
}

/**
 *	via_set_drive		-	configure transfer mode
 *	@drive: Drive to set up
 *	@speed: desired speed
 *
 *	via_set_drive() computes timing values configures the chipset to
 *	a desired transfer mode.  It also can be called by upper layers.
 */

static void via_set_drive(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif = drive->hwif;
	ide_drive_t *peer = ide_get_pair_dev(drive);
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	struct ide_host *host = pci_get_drvdata(dev);
	struct via82cxxx_dev *vdev = host->host_priv;
	struct ide_timing t, p;
	unsigned int T, UT;

	T = 1000000000 / via_clock;

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: UT = T;   break;
	case ATA_UDMA4: UT = T/2; break;
	case ATA_UDMA5: UT = T/3; break;
	case ATA_UDMA6: UT = T/4; break;
	default:	UT = T;
	}

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer) {
		ide_timing_compute(peer, peer->current_speed, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	via_set_speed(hwif, drive->dn, &t);
}

/**
 *	via_set_pio_mode	-	set host controller for PIO mode
 *	@drive: drive
 *	@pio: PIO mode number
 *
 *	A callback from the upper layers for PIO-only tuning.
 */

static void via_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	via_set_drive(drive, XFER_PIO_0 + pio);
}

static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
{
	struct via_isa_bridge *via_config;

	for (via_config = via_isa_bridges;
	     via_config->id != PCI_DEVICE_ID_VIA_ANON; via_config++)
		if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
			!!(via_config->flags & VIA_BAD_ID),
			via_config->id, NULL))) {

			if ((*isa)->revision >= via_config->rev_min &&
			    (*isa)->revision <= via_config->rev_max)
				break;
			pci_dev_put(*isa);
		}

	return via_config;
}

/*
 * Check and handle 80-wire cable presence
 */
static void via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
{
	int i;

	switch (vdev->via_config->udma_mask) {
		case ATA_UDMA4:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> (i & 16)) & 8) &&
				    ((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 2)) {
					/*
					 * 2x PCI clock and
					 * UDMA w/ < 3T/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA5:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 4))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA6:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 6))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;
	}
}

/**
 *	init_chipset_via82cxxx	-	initialization handler
 *	@dev: PCI device
 *
 *	The initialization callback. Here we determine the IDE chip type
 *	and initialize its drive independent registers.
 */

static int init_chipset_via82cxxx(struct pci_dev *dev)
{
	struct ide_host *host = pci_get_drvdata(dev);
	struct via82cxxx_dev *vdev = host->host_priv;
	struct via_isa_bridge *via_config = vdev->via_config;
	u8 t, v;
	u32 u;

	/*
	 * Detect cable and configure Clk66
	 */
	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);

	via_cable_detect(vdev, u);

	if (via_config->udma_mask == ATA_UDMA4) {
		/* Enable Clk66 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
	} else if (via_config->flags & VIA_BAD_CLK66) {
		/* Would cause trouble on 596a and 686 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	}

	/*
	 * Check whether interfaces are enabled.
	 */

	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);

	/*
	 * Set up FIFO sizes and thresholds.
	 */

	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);

	/* Disable PREQ# till DDACK# */
	if (via_config->flags & VIA_BAD_PREQ) {
		/* Would crash on 586b rev 41 */
		t &= 0x7f;
	}

	/* Fix FIFO split between channels */
	if (via_config->flags & VIA_SET_FIFO) {
		t &= (t & 0x9f);
		switch (v & 3) {
			case 2: t |= 0x00; break;	/* 16 on primary */
			case 1: t |= 0x60; break;	/* 16 on secondary */
			case 3: t |= 0x20; break;	/* 8 pri 8 sec */
		}
	}

	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);

	return 0;
}

/*
 *	Cable special cases
 */

static const struct dmi_system_id cable_dmi_table[] = {
	{
		.ident = "Acer Ferrari 3400",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
			DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
		},
	},
	{ }
};

static int via_cable_override(struct pci_dev *pdev)
{
	/* Systems by DMI */
	if (dmi_check_system(cable_dmi_table))
		return 1;

	/* Arima W730-K8/Targa Visionary 811/... */
	if (pdev->subsystem_vendor == 0x161F &&
	    pdev->subsystem_device == 0x2032)
		return 1;

	return 0;
}

static u8 via82cxxx_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	struct ide_host *host = pci_get_drvdata(pdev);
	struct via82cxxx_dev *vdev = host->host_priv;

	if (via_cable_override(pdev))
		return ATA_CBL_PATA40_SHORT;

	if ((vdev->via_config->flags & VIA_SATA_PATA) && hwif->channel == 0)
		return ATA_CBL_SATA;

	if ((vdev->via_80w >> hwif->channel) & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static const struct ide_port_ops via_port_ops = {
	.set_pio_mode		= via_set_pio_mode,
	.set_dma_mode		= via_set_drive,
	.cable_detect		= via82cxxx_cable_detect,
};

static void via_write_devctl(ide_hwif_t *hwif, u8 ctl)
{
	struct via82cxxx_dev *vdev = hwif->host->host_priv;

	outb(ctl, hwif->io_ports.ctl_addr);
	outb(vdev->cached_device[hwif->channel], hwif->io_ports.device_addr);
}

static void __via_dev_select(ide_drive_t *drive, u8 select)
{
	ide_hwif_t *hwif = drive->hwif;
	struct via82cxxx_dev *vdev = hwif->host->host_priv;

	outb(select, hwif->io_ports.device_addr);
	vdev->cached_device[hwif->channel] = select;
}

static void via_dev_select(ide_drive_t *drive)
{
	__via_dev_select(drive, drive->select | ATA_DEVICE_OBS);
}

static void via_tf_load(ide_drive_t *drive, struct ide_taskfile *tf, u8 valid)
{
	ide_hwif_t *hwif = drive->hwif;
	struct ide_io_ports *io_ports = &hwif->io_ports;

	if (valid & IDE_VALID_FEATURE)
		outb(tf->feature, io_ports->feature_addr);
	if (valid & IDE_VALID_NSECT)
		outb(tf->nsect, io_ports->nsect_addr);
	if (valid & IDE_VALID_LBAL)
		outb(tf->lbal, io_ports->lbal_addr);
	if (valid & IDE_VALID_LBAM)
		outb(tf->lbam, io_ports->lbam_addr);
	if (valid & IDE_VALID_LBAH)
		outb(tf->lbah, io_ports->lbah_addr);
	if (valid & IDE_VALID_DEVICE)
		__via_dev_select(drive, tf->device);
}

const struct ide_tp_ops via_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= ide_read_status,
	.read_altstatus		= ide_read_altstatus,
	.write_devctl		= via_write_devctl,

	.dev_select		= via_dev_select,
	.tf_load		= via_tf_load,
	.tf_read		= ide_tf_read,

	.input_data		= ide_input_data,
	.output_data		= ide_output_data,
};

static const struct ide_port_info via82cxxx_chipset __devinitdata = {
	.name		= DRV_NAME,
	.init_chipset	= init_chipset_via82cxxx,
	.enablebits	= { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
	.tp_ops		= &via_tp_ops,
	.port_ops	= &via_port_ops,
	.host_flags	= IDE_HFLAG_PIO_NO_BLACKLIST |
			  IDE_HFLAG_POST_SET_MODE |
			  IDE_HFLAG_IO_32BIT,
	.pio_mask	= ATA_PIO5,
	.swdma_mask	= ATA_SWDMA2,
	.mwdma_mask	= ATA_MWDMA2,
};

static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct pci_dev *isa = NULL;
	struct via_isa_bridge *via_config;
	struct via82cxxx_dev *vdev;
	int rc;
	u8 idx = id->driver_data;
	struct ide_port_info d;

	d = via82cxxx_chipset;

	/*
	 * Find the ISA bridge and check we know what it is.
	 */
	via_config = via_config_find(&isa);

	/*
	 * Print the boot message.
	 */
	printk(KERN_INFO DRV_NAME " %s: VIA %s (rev %02x) IDE %sDMA%s\n",
		pci_name(dev), via_config->name, isa->revision,
		via_config->udma_mask ? "U" : "MW",
		via_dma[via_config->udma_mask ?
			(fls(via_config->udma_mask) - 1) : 0]);

	pci_dev_put(isa);

	/*
	 * Determine system bus clock.
	 */
	via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;

	switch (via_clock) {
	case 33000: via_clock = 33333; break;
	case 37000: via_clock = 37500; break;
	case 41000: via_clock = 41666; break;
	}

	if (via_clock < 20000 || via_clock > 50000) {
		printk(KERN_WARNING DRV_NAME ": User given PCI clock speed "
			"impossible (%d), using 33 MHz instead.\n", via_clock);
		via_clock = 33333;
	}

	if (idx == 1)
		d.enablebits[1].reg = d.enablebits[0].reg = 0;
	else
		d.host_flags |= IDE_HFLAG_NO_AUTODMA;

	if (idx == VIA_IDFLAG_SINGLE)
		d.host_flags |= IDE_HFLAG_SINGLE;

	if ((via_config->flags & VIA_NO_UNMASK) == 0)
		d.host_flags |= IDE_HFLAG_UNMASK_IRQS;

	d.udma_mask = via_config->udma_mask;

	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
	if (!vdev) {
		printk(KERN_ERR DRV_NAME " %s: out of memory :(\n",
			pci_name(dev));
		return -ENOMEM;
	}

	vdev->via_config = via_config;

	rc = ide_pci_init_one(dev, &d, vdev);
	if (rc)
		kfree(vdev);

	return rc;
}

static void __devexit via_remove(struct pci_dev *dev)
{
	struct ide_host *host = pci_get_drvdata(dev);
	struct via82cxxx_dev *vdev = host->host_priv;

	ide_pci_remove(dev);
	kfree(vdev);
}

static const struct pci_device_id via_pci_tbl[] = {
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1),  0 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1),  0 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410),      1 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6415),      1 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, via_pci_tbl);

static struct pci_driver via_pci_driver = {
	.name 		= "VIA_IDE",
	.id_table 	= via_pci_tbl,
	.probe 		= via_init_one,
	.remove		= __devexit_p(via_remove),
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init via_ide_init(void)
{
	return ide_pci_register_driver(&via_pci_driver);
}

static void __exit via_ide_exit(void)
{
	pci_unregister_driver(&via_pci_driver);
}

module_init(via_ide_init);
module_exit(via_ide_exit);

MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for VIA IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* VIA IDE driver for Linux. Supported southbridges:
	3	*
	4	* vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
	5	* vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
a7dec1e0	6	* vt8235, vt8237, vt8237a
1da177e4 LT	7	*
1da177e4 LT	8	* Copyright (c) 2000-2002 Vojtech Pavlik
42036c85	9	* Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
1da177e4 LT	10	*
	11	* Based on the work of:
	12	* Michel Aubry
	13	* Jeff Garzik
	14	* Andre Hedrick
	15	*
	16	* Documentation:
	17	* Obsolete device documentation publically available from via.com.tw
	18	* Current device documentation available under NDA only
	19	*/
	20
	21	/*
	22	* This program is free software; you can redistribute it and/or modify it
	23	* under the terms of the GNU General Public License version 2 as published by
	24	* the Free Software Foundation.
	25	*/
	26
1da177e4 LT	27	#include <linux/module.h>
1da177e4 LT	28	#include <linux/kernel.h>
1da177e4 LT	29	#include <linux/pci.h>
	30	#include <linux/init.h>
	31	#include <linux/ide.h>
bdab00b7 BZ	32	#include <linux/dmi.h>
bdab00b7 BZ	33
74a9d5f1	34	#ifdef CONFIG_PPC_CHRP
1da177e4 LT	35	#include <asm/processor.h>
	36	#endif
	37
ced3ec8a BZ	38	#define DRV_NAME "via82cxxx"
ced3ec8a BZ	39
1da177e4 LT	40	#define VIA_IDE_ENABLE 0x40
	41	#define VIA_IDE_CONFIG 0x41
	42	#define VIA_FIFO_CONFIG 0x43
	43	#define VIA_MISC_1 0x44
	44	#define VIA_MISC_2 0x45
	45	#define VIA_MISC_3 0x46
	46	#define VIA_DRIVE_TIMING 0x48
	47	#define VIA_8BIT_TIMING 0x4e
	48	#define VIA_ADDRESS_SETUP 0x4c
	49	#define VIA_UDMA_TIMING 0x50
	50
75b1d975 BZ	51	#define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
	52	#define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
	53	#define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
	54	#define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
	55	#define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
	56	#define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
a13e4865	57	#define VIA_SATA_PATA 0x80 /* SATA/PATA combined configuration */
1da177e4	58
42036c85 BZ	59	enum {
	60	VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */
	61	};
	62
1da177e4 LT	63	/*
	64	* VIA SouthBridge chips.
	65	*/
	66
	67	static struct via_isa_bridge {
	68	char *name;
	69	u16 id;
	70	u8 rev_min;
	71	u8 rev_max;
75b1d975 BZ	72	u8 udma_mask;
75b1d975 BZ	73	u8 flags;
1da177e4	74	} via_isa_bridges[] = {
a13e4865 BZ	75	{ "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST \| VIA_SATA_PATA },
	76	{ "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST \| VIA_SATA_PATA },
	77	{ "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST \| VIA_SATA_PATA },
5b6c82ea	78	{ "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
75b1d975 BZ	79	{ "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
75b1d975 BZ	80	{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
a354ae87	81	{ "vt6415", PCI_DEVICE_ID_VIA_6410, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST },
75b1d975 BZ	82	{ "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	83	{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	84	{ "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	85	{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	86	{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	87	{ "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
	88	{ "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
	89	{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
	90	{ "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
	91	{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
	92	{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	93	{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
	94	{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	95	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	96	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO \| VIA_BAD_PREQ },
	97	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	98	{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	99	{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
	100	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK },
	101	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK \| VIA_BAD_ID },
5b6c82ea	102	{ "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
1da177e4 LT	103	{ NULL }
	104	};
	105
1da177e4	106	static unsigned int via_clock;
75b1d975	107	static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
1da177e4	108
7462cbff DD	109	struct via82cxxx_dev
	110	{
	111	struct via_isa_bridge *via_config;
	112	unsigned int via_80w;
f931a5d5	113	u8 cached_device[2];
7462cbff DD	114	};
7462cbff DD	115
1da177e4 LT	116	/**
	117	* via_set_speed - write timing registers
	118	* @dev: PCI device
	119	* @dn: device
	120	* @timing: IDE timing data to use
	121	*
	122	* via_set_speed writes timing values to the chipset registers
	123	*/
	124
7462cbff	125	static void via_set_speed(ide_hwif_t hwif, u8 dn, struct ide_timing timing)
1da177e4	126	{
36501650	127	struct pci_dev *dev = to_pci_dev(hwif->dev);
ee77325b BZ	128	struct ide_host *host = pci_get_drvdata(dev);
ee77325b BZ	129	struct via82cxxx_dev *vdev = host->host_priv;
1da177e4 LT	130	u8 t;
1da177e4 LT	131
7462cbff	132	if (~vdev->via_config->flags & VIA_BAD_AST) {
1da177e4	133	pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
d6cddd3c	134	t = (t & ~(3 << ((3 - dn) << 1))) \| ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
1da177e4 LT	135	pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	136	}
	137
	138	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
d6cddd3c	139	((clamp_val(timing->act8b, 1, 16) - 1) << 4) \| (clamp_val(timing->rec8b, 1, 16) - 1));
1da177e4 LT	140
1da177e4 LT	141	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
d6cddd3c	142	((clamp_val(timing->active, 1, 16) - 1) << 4) \| (clamp_val(timing->recover, 1, 16) - 1));
1da177e4	143
75b1d975	144	switch (vdev->via_config->udma_mask) {
d6cddd3c HH	145	case ATA_UDMA2: t = timing->udma ? (0xe0 \| (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
	146	case ATA_UDMA4: t = timing->udma ? (0xe8 \| (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break;
	147	case ATA_UDMA5: t = timing->udma ? (0xe0 \| (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
	148	case ATA_UDMA6: t = timing->udma ? (0xe0 \| (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
75b1d975	149	default: return;
1da177e4 LT	150	}
	151
	152	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
	153	}
	154
	155	/**
	156	* via_set_drive - configure transfer mode
	157	* @drive: Drive to set up
	158	* @speed: desired speed
	159	*
88b2b32b BZ	160	* via_set_drive() computes timing values configures the chipset to
88b2b32b BZ	161	* a desired transfer mode. It also can be called by upper layers.
1da177e4 LT	162	*/
1da177e4 LT	163
88b2b32b	164	static void via_set_drive(ide_drive_t *drive, const u8 speed)
1da177e4	165	{
36501650	166	ide_hwif_t *hwif = drive->hwif;
7e59ea21	167	ide_drive_t *peer = ide_get_pair_dev(drive);
36501650	168	struct pci_dev *dev = to_pci_dev(hwif->dev);
ee77325b BZ	169	struct ide_host *host = pci_get_drvdata(dev);
ee77325b BZ	170	struct via82cxxx_dev *vdev = host->host_priv;
1da177e4 LT	171	struct ide_timing t, p;
	172	unsigned int T, UT;
	173
1da177e4 LT	174	T = 1000000000 / via_clock;
1da177e4 LT	175
75b1d975 BZ	176	switch (vdev->via_config->udma_mask) {
	177	case ATA_UDMA2: UT = T; break;
	178	case ATA_UDMA4: UT = T/2; break;
	179	case ATA_UDMA5: UT = T/3; break;
	180	case ATA_UDMA6: UT = T/4; break;
	181	default: UT = T;
1da177e4 LT	182	}
	183
	184	ide_timing_compute(drive, speed, &t, T, UT);
	185
7e59ea21	186	if (peer) {
1da177e4 LT	187	ide_timing_compute(peer, peer->current_speed, &p, T, UT);
	188	ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	189	}
	190
898ec223	191	via_set_speed(hwif, drive->dn, &t);
1da177e4 LT	192	}
	193
	194	/**
88b2b32b	195	* via_set_pio_mode - set host controller for PIO mode
26bcb879 BZ	196	* @drive: drive
26bcb879 BZ	197	* @pio: PIO mode number
1da177e4 LT	198	*
	199	* A callback from the upper layers for PIO-only tuning.
	200	*/
	201
26bcb879	202	static void via_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	203	{
26bcb879	204	via_set_drive(drive, XFER_PIO_0 + pio);
1da177e4 LT	205	}
1da177e4 LT	206
7462cbff DD	207	static struct via_isa_bridge via_config_find(struct pci_dev *isa)
	208	{
	209	struct via_isa_bridge *via_config;
7462cbff	210
5b6c82ea BZ	211	for (via_config = via_isa_bridges;
5b6c82ea BZ	212	via_config->id != PCI_DEVICE_ID_VIA_ANON; via_config++)
652aa162	213	if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
7462cbff DD	214	!!(via_config->flags & VIA_BAD_ID),
	215	via_config->id, NULL))) {
	216
44c10138 AK	217	if ((*isa)->revision >= via_config->rev_min &&
44c10138 AK	218	(*isa)->revision <= via_config->rev_max)
7462cbff	219	break;
652aa162	220	pci_dev_put(*isa);
7462cbff DD	221	}
	222
	223	return via_config;
1da177e4 LT	224	}
1da177e4 LT	225
cd36beec BZ	226	/*
	227	* Check and handle 80-wire cable presence
	228	*/
feb22b7f	229	static void via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
cd36beec BZ	230	{
	231	int i;
	232
75b1d975 BZ	233	switch (vdev->via_config->udma_mask) {
75b1d975 BZ	234	case ATA_UDMA4:
cd36beec BZ	235	for (i = 24; i >= 0; i -= 8)
	236	if (((u >> (i & 16)) & 8) &&
	237	((u >> i) & 0x20) &&
	238	(((u >> i) & 7) < 2)) {
	239	/*
	240	* 2x PCI clock and
	241	* UDMA w/ < 3T/cycle
	242	*/
	243	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	244	}
	245	break;
	246
75b1d975	247	case ATA_UDMA5:
cd36beec BZ	248	for (i = 24; i >= 0; i -= 8)
	249	if (((u >> i) & 0x10) \|\|
	250	(((u >> i) & 0x20) &&
	251	(((u >> i) & 7) < 4))) {
	252	/* BIOS 80-wire bit or
	253	* UDMA w/ < 60ns/cycle
	254	*/
	255	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	256	}
	257	break;
	258
75b1d975	259	case ATA_UDMA6:
cd36beec BZ	260	for (i = 24; i >= 0; i -= 8)
	261	if (((u >> i) & 0x10) \|\|
	262	(((u >> i) & 0x20) &&
	263	(((u >> i) & 7) < 6))) {
	264	/* BIOS 80-wire bit or
	265	* UDMA w/ < 60ns/cycle
	266	*/
	267	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	268	}
	269	break;
	270	}
	271	}
	272
1da177e4 LT	273	/**
	274	* init_chipset_via82cxxx - initialization handler
	275	* @dev: PCI device
1da177e4 LT	276	*
	277	* The initialization callback. Here we determine the IDE chip type
	278	* and initialize its drive independent registers.
	279	*/
	280
2ed0ef54	281	static int init_chipset_via82cxxx(struct pci_dev *dev)
1da177e4	282	{
ee77325b BZ	283	struct ide_host *host = pci_get_drvdata(dev);
ee77325b BZ	284	struct via82cxxx_dev *vdev = host->host_priv;
37525beb	285	struct via_isa_bridge *via_config = vdev->via_config;
1da177e4	286	u8 t, v;
cd36beec BZ	287	u32 u;
cd36beec BZ	288
1da177e4	289	/*
cd36beec	290	* Detect cable and configure Clk66
1da177e4	291	*/
cd36beec BZ	292	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
	293
	294	via_cable_detect(vdev, u);
1da177e4	295
75b1d975	296	if (via_config->udma_mask == ATA_UDMA4) {
7462cbff	297	/* Enable Clk66 */
7462cbff DD	298	pci_write_config_dword(dev, VIA_UDMA_TIMING, u\|0x80008);
7462cbff DD	299	} else if (via_config->flags & VIA_BAD_CLK66) {
1da177e4	300	/* Would cause trouble on 596a and 686 */
1da177e4 LT	301	pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	302	}
	303
	304	/*
	305	* Check whether interfaces are enabled.
	306	*/
	307
	308	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
	309
	310	/*
	311	* Set up FIFO sizes and thresholds.
	312	*/
	313
	314	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
	315
	316	/* Disable PREQ# till DDACK# */
	317	if (via_config->flags & VIA_BAD_PREQ) {
	318	/* Would crash on 586b rev 41 */
	319	t &= 0x7f;
	320	}
	321
	322	/* Fix FIFO split between channels */
	323	if (via_config->flags & VIA_SET_FIFO) {
	324	t &= (t & 0x9f);
	325	switch (v & 3) {
	326	case 2: t \|= 0x00; break; /* 16 on primary */
	327	case 1: t \|= 0x60; break; /* 16 on secondary */
	328	case 3: t \|= 0x20; break; /* 8 pri 8 sec */
	329	}
	330	}
	331
	332	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
	333
1da177e4 LT	334	return 0;
	335	}
	336
bdab00b7 BZ	337	/*
	338	* Cable special cases
	339	*/
	340
1855256c	341	static const struct dmi_system_id cable_dmi_table[] = {
bdab00b7 BZ	342	{
	343	.ident = "Acer Ferrari 3400",
	344	.matches = {
	345	DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
	346	DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
	347	},
	348	},
	349	{ }
	350	};
	351
58e47bb1	352	static int via_cable_override(struct pci_dev *pdev)
bdab00b7 BZ	353	{
	354	/* Systems by DMI */
	355	if (dmi_check_system(cable_dmi_table))
	356	return 1;
58e47bb1 BZ	357
	358	/* Arima W730-K8/Targa Visionary 811/... */
	359	if (pdev->subsystem_vendor == 0x161F &&
	360	pdev->subsystem_device == 0x2032)
	361	return 1;
	362
bdab00b7 BZ	363	return 0;
	364	}
	365
f454cbe8	366	static u8 via82cxxx_cable_detect(ide_hwif_t *hwif)
bdab00b7	367	{
36501650	368	struct pci_dev *pdev = to_pci_dev(hwif->dev);
ee77325b BZ	369	struct ide_host *host = pci_get_drvdata(pdev);
ee77325b BZ	370	struct via82cxxx_dev *vdev = host->host_priv;
bdab00b7	371
58e47bb1	372	if (via_cable_override(pdev))
bdab00b7 BZ	373	return ATA_CBL_PATA40_SHORT;
bdab00b7 BZ	374
a13e4865 BZ	375	if ((vdev->via_config->flags & VIA_SATA_PATA) && hwif->channel == 0)
	376	return ATA_CBL_SATA;
	377
bdab00b7 BZ	378	if ((vdev->via_80w >> hwif->channel) & 1)
	379	return ATA_CBL_PATA80;
	380	else
	381	return ATA_CBL_PATA40;
	382	}
	383
ac95beed BZ	384	static const struct ide_port_ops via_port_ops = {
	385	.set_pio_mode = via_set_pio_mode,
	386	.set_dma_mode = via_set_drive,
	387	.cable_detect = via82cxxx_cable_detect,
	388	};
1da177e4	389
f931a5d5 BZ	390	static void via_write_devctl(ide_hwif_t *hwif, u8 ctl)
	391	{
	392	struct via82cxxx_dev *vdev = hwif->host->host_priv;
	393
	394	outb(ctl, hwif->io_ports.ctl_addr);
	395	outb(vdev->cached_device[hwif->channel], hwif->io_ports.device_addr);
	396	}
	397
	398	static void __via_dev_select(ide_drive_t *drive, u8 select)
	399	{
	400	ide_hwif_t *hwif = drive->hwif;
	401	struct via82cxxx_dev *vdev = hwif->host->host_priv;
	402
	403	outb(select, hwif->io_ports.device_addr);
	404	vdev->cached_device[hwif->channel] = select;
	405	}
	406
	407	static void via_dev_select(ide_drive_t *drive)
	408	{
	409	__via_dev_select(drive, drive->select \| ATA_DEVICE_OBS);
	410	}
	411
	412	static void via_tf_load(ide_drive_t drive, struct ide_taskfile tf, u8 valid)
	413	{
	414	ide_hwif_t *hwif = drive->hwif;
	415	struct ide_io_ports *io_ports = &hwif->io_ports;
	416
	417	if (valid & IDE_VALID_FEATURE)
	418	outb(tf->feature, io_ports->feature_addr);
	419	if (valid & IDE_VALID_NSECT)
	420	outb(tf->nsect, io_ports->nsect_addr);
	421	if (valid & IDE_VALID_LBAL)
	422	outb(tf->lbal, io_ports->lbal_addr);
	423	if (valid & IDE_VALID_LBAM)
	424	outb(tf->lbam, io_ports->lbam_addr);
	425	if (valid & IDE_VALID_LBAH)
	426	outb(tf->lbah, io_ports->lbah_addr);
	427	if (valid & IDE_VALID_DEVICE)
	428	__via_dev_select(drive, tf->device);
	429	}
	430
	431	const struct ide_tp_ops via_tp_ops = {
	432	.exec_command = ide_exec_command,
	433	.read_status = ide_read_status,
	434	.read_altstatus = ide_read_altstatus,
	435	.write_devctl = via_write_devctl,
	436
	437	.dev_select = via_dev_select,
	438	.tf_load = via_tf_load,
	439	.tf_read = ide_tf_read,
	440
	441	.input_data = ide_input_data,
	442	.output_data = ide_output_data,
	443	};
	444
85620436	445	static const struct ide_port_info via82cxxx_chipset __devinitdata = {
ced3ec8a	446	.name = DRV_NAME,
6157332e	447	.init_chipset = init_chipset_via82cxxx,
6157332e	448	.enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
f931a5d5	449	.tp_ops = &via_tp_ops,
ac95beed	450	.port_ops = &via_port_ops,
6157332e	451	.host_flags = IDE_HFLAG_PIO_NO_BLACKLIST \|
6157332e	452	IDE_HFLAG_POST_SET_MODE \|
5e71d9c5	453	IDE_HFLAG_IO_32BIT,
6157332e BZ	454	.pio_mask = ATA_PIO5,
	455	.swdma_mask = ATA_SWDMA2,
	456	.mwdma_mask = ATA_MWDMA2,
1da177e4 LT	457	};
	458
	459	static int __devinit via_init_one(struct pci_dev dev, const struct pci_device_id id)
	460	{
23a1b2a7 AC	461	struct pci_dev *isa = NULL;
23a1b2a7 AC	462	struct via_isa_bridge *via_config;
ee77325b BZ	463	struct via82cxxx_dev *vdev;
ee77325b BZ	464	int rc;
6157332e	465	u8 idx = id->driver_data;
039788e1	466	struct ide_port_info d;
6157332e BZ	467
6157332e BZ	468	d = via82cxxx_chipset;
8acf28c0	469
23a1b2a7 AC	470	/*
	471	* Find the ISA bridge and check we know what it is.
	472	*/
	473	via_config = via_config_find(&isa);
8acf28c0	474
37525beb BZ	475	/*
	476	* Print the boot message.
	477	*/
ced3ec8a	478	printk(KERN_INFO DRV_NAME " %s: VIA %s (rev %02x) IDE %sDMA%s\n",
28cfd8af	479	pci_name(dev), via_config->name, isa->revision,
37525beb BZ	480	via_config->udma_mask ? "U" : "MW",
37525beb BZ	481	via_dma[via_config->udma_mask ?
28cfd8af	482	(fls(via_config->udma_mask) - 1) : 0]);
37525beb BZ	483
	484	pci_dev_put(isa);
	485
	486	/*
	487	* Determine system bus clock.
	488	*/
	489	via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;
	490
	491	switch (via_clock) {
	492	case 33000: via_clock = 33333; break;
	493	case 37000: via_clock = 37500; break;
	494	case 41000: via_clock = 41666; break;
	495	}
	496
	497	if (via_clock < 20000 \|\| via_clock > 50000) {
ced3ec8a	498	printk(KERN_WARNING DRV_NAME ": User given PCI clock speed "
37525beb	499	"impossible (%d), using 33 MHz instead.\n", via_clock);
37525beb BZ	500	via_clock = 33333;
	501	}
	502
42036c85	503	if (idx == 1)
6157332e	504	d.enablebits[1].reg = d.enablebits[0].reg = 0;
42036c85 BZ	505	else
	506	d.host_flags \|= IDE_HFLAG_NO_AUTODMA;
	507
	508	if (idx == VIA_IDFLAG_SINGLE)
	509	d.host_flags \|= IDE_HFLAG_SINGLE;
6157332e BZ	510
	511	if ((via_config->flags & VIA_NO_UNMASK) == 0)
	512	d.host_flags \|= IDE_HFLAG_UNMASK_IRQS;
caea7602	513
6157332e	514	d.udma_mask = via_config->udma_mask;
8acf28c0	515
ee77325b BZ	516	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
ee77325b BZ	517	if (!vdev) {
ced3ec8a BZ	518	printk(KERN_ERR DRV_NAME " %s: out of memory :(\n",
ced3ec8a BZ	519	pci_name(dev));
ee77325b BZ	520	return -ENOMEM;
	521	}
	522
37525beb BZ	523	vdev->via_config = via_config;
37525beb BZ	524
ee77325b BZ	525	rc = ide_pci_init_one(dev, &d, vdev);
	526	if (rc)
	527	kfree(vdev);
	528
	529	return rc;
1da177e4 LT	530	}
1da177e4 LT	531
585f67e7 BZ	532	static void __devexit via_remove(struct pci_dev *dev)
	533	{
	534	struct ide_host *host = pci_get_drvdata(dev);
	535	struct via82cxxx_dev *vdev = host->host_priv;
	536
	537	ide_pci_remove(dev);
	538	kfree(vdev);
	539	}
	540
9cbcc5e3 BZ	541	static const struct pci_device_id via_pci_tbl[] = {
	542	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 },
	543	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 },
84f7e451	544	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 },
42036c85	545	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE },
9cbcc5e3	546	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 },
a354ae87	547	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6415), 1 },
9cbcc5e3	548	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
1da177e4 LT	549	{ 0, },
	550	};
	551	MODULE_DEVICE_TABLE(pci, via_pci_tbl);
	552
a9ab09e2	553	static struct pci_driver via_pci_driver = {
1da177e4 LT	554	.name = "VIA_IDE",
	555	.id_table = via_pci_tbl,
	556	.probe = via_init_one,
a69999e2	557	.remove = __devexit_p(via_remove),
feb22b7f BZ	558	.suspend = ide_pci_suspend,
feb22b7f BZ	559	.resume = ide_pci_resume,
1da177e4 LT	560	};
1da177e4 LT	561
82ab1eec	562	static int __init via_ide_init(void)
1da177e4	563	{
a9ab09e2	564	return ide_pci_register_driver(&via_pci_driver);
1da177e4 LT	565	}
1da177e4 LT	566
585f67e7 BZ	567	static void __exit via_ide_exit(void)
585f67e7 BZ	568	{
a9ab09e2	569	pci_unregister_driver(&via_pci_driver);
585f67e7 BZ	570	}
585f67e7 BZ	571
1da177e4	572	module_init(via_ide_init);
585f67e7	573	module_exit(via_ide_exit);
1da177e4	574
42036c85	575	MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick");
1da177e4 LT	576	MODULE_DESCRIPTION("PCI driver module for VIA IDE");
1da177e4 LT	577	MODULE_LICENSE("GPL");