Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> |
ccd32e22 | 3 | * Copyright (C) 2003 Red Hat |
7b255436 | 4 | * Copyright (C) 2007-2008 MontaVista Software, Inc. |
165701d9 | 5 | * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
6 | * |
7 | * May be copied or modified under the terms of the GNU General Public License | |
8 | * | |
bf4c796d JG |
9 | * Documentation for CMD680: |
10 | * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 | |
11 | * | |
12 | * Documentation for SiI 3112: | |
13 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
14 | * | |
15 | * Errata and other documentation only available under NDA. | |
1da177e4 LT |
16 | * |
17 | * | |
18 | * FAQ Items: | |
19 | * If you are using Marvell SATA-IDE adapters with Maxtor drives | |
7b255436 | 20 | * ensure the system is set up for ATA100/UDMA5, not UDMA6. |
1da177e4 LT |
21 | * |
22 | * If you are using WD drives with SATA bridges you must set the | |
7b255436 | 23 | * drive to "Single". "Master" will hang. |
1da177e4 LT |
24 | * |
25 | * If you have strange problems with nVidia chipset systems please | |
26 | * see the SI support documentation and update your system BIOS | |
3a4fa0a2 | 27 | * if necessary |
8693d3e4 AC |
28 | * |
29 | * The Dell DRAC4 has some interesting features including effectively hot | |
30 | * unplugging/replugging the virtual CD interface when the DRAC is reset. | |
31 | * This often causes drivers/ide/siimage to panic but is ok with the rather | |
32 | * smarter code in libata. | |
328dcbb6 BZ |
33 | * |
34 | * TODO: | |
328dcbb6 | 35 | * - VDMA support |
1da177e4 LT |
36 | */ |
37 | ||
1da177e4 LT |
38 | #include <linux/types.h> |
39 | #include <linux/module.h> | |
40 | #include <linux/pci.h> | |
1da177e4 LT |
41 | #include <linux/ide.h> |
42 | #include <linux/init.h> | |
7b255436 | 43 | #include <linux/io.h> |
1da177e4 | 44 | |
ced3ec8a BZ |
45 | #define DRV_NAME "siimage" |
46 | ||
1da177e4 LT |
47 | /** |
48 | * pdev_is_sata - check if device is SATA | |
49 | * @pdev: PCI device to check | |
7b255436 | 50 | * |
1da177e4 LT |
51 | * Returns true if this is a SATA controller |
52 | */ | |
7b255436 | 53 | |
1da177e4 LT |
54 | static int pdev_is_sata(struct pci_dev *pdev) |
55 | { | |
438c4702 | 56 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
7b255436 SS |
57 | switch (pdev->device) { |
58 | case PCI_DEVICE_ID_SII_3112: | |
59 | case PCI_DEVICE_ID_SII_1210SA: | |
60 | return 1; | |
61 | case PCI_DEVICE_ID_SII_680: | |
62 | return 0; | |
1da177e4 LT |
63 | } |
64 | BUG(); | |
438c4702 | 65 | #endif |
1da177e4 LT |
66 | return 0; |
67 | } | |
438c4702 | 68 | |
1da177e4 LT |
69 | /** |
70 | * is_sata - check if hwif is SATA | |
71 | * @hwif: interface to check | |
7b255436 | 72 | * |
1da177e4 LT |
73 | * Returns true if this is a SATA controller |
74 | */ | |
7b255436 | 75 | |
1da177e4 LT |
76 | static inline int is_sata(ide_hwif_t *hwif) |
77 | { | |
36501650 | 78 | return pdev_is_sata(to_pci_dev(hwif->dev)); |
1da177e4 LT |
79 | } |
80 | ||
81 | /** | |
82 | * siimage_selreg - return register base | |
83 | * @hwif: interface | |
84 | * @r: config offset | |
85 | * | |
86 | * Turn a config register offset into the right address in either | |
87 | * PCI space or MMIO space to access the control register in question | |
7b255436 SS |
88 | * Thankfully this is a configuration operation, so isn't performance |
89 | * critical. | |
1da177e4 | 90 | */ |
7b255436 | 91 | |
1da177e4 LT |
92 | static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) |
93 | { | |
94 | unsigned long base = (unsigned long)hwif->hwif_data; | |
7b255436 | 95 | |
1da177e4 | 96 | base += 0xA0 + r; |
13572144 | 97 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
7b255436 | 98 | base += hwif->channel << 6; |
1da177e4 | 99 | else |
7b255436 | 100 | base += hwif->channel << 4; |
1da177e4 LT |
101 | return base; |
102 | } | |
7b255436 | 103 | |
1da177e4 LT |
104 | /** |
105 | * siimage_seldev - return register base | |
106 | * @hwif: interface | |
107 | * @r: config offset | |
108 | * | |
109 | * Turn a config register offset into the right address in either | |
110 | * PCI space or MMIO space to access the control register in question | |
111 | * including accounting for the unit shift. | |
112 | */ | |
7b255436 | 113 | |
1da177e4 LT |
114 | static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) |
115 | { | |
898ec223 | 116 | ide_hwif_t *hwif = drive->hwif; |
7b255436 | 117 | unsigned long base = (unsigned long)hwif->hwif_data; |
123995b9 | 118 | u8 unit = drive->dn & 1; |
7b255436 | 119 | |
1da177e4 | 120 | base += 0xA0 + r; |
13572144 | 121 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
7b255436 | 122 | base += hwif->channel << 6; |
1da177e4 | 123 | else |
7b255436 | 124 | base += hwif->channel << 4; |
123995b9 | 125 | base |= unit << unit; |
1da177e4 LT |
126 | return base; |
127 | } | |
128 | ||
165701d9 BZ |
129 | static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr) |
130 | { | |
4c674235 | 131 | struct ide_host *host = pci_get_drvdata(dev); |
165701d9 BZ |
132 | u8 tmp = 0; |
133 | ||
4c674235 | 134 | if (host->host_priv) |
165701d9 BZ |
135 | tmp = readb((void __iomem *)addr); |
136 | else | |
137 | pci_read_config_byte(dev, addr, &tmp); | |
138 | ||
139 | return tmp; | |
140 | } | |
141 | ||
142 | static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr) | |
143 | { | |
4c674235 | 144 | struct ide_host *host = pci_get_drvdata(dev); |
165701d9 BZ |
145 | u16 tmp = 0; |
146 | ||
4c674235 | 147 | if (host->host_priv) |
165701d9 BZ |
148 | tmp = readw((void __iomem *)addr); |
149 | else | |
150 | pci_read_config_word(dev, addr, &tmp); | |
151 | ||
152 | return tmp; | |
153 | } | |
154 | ||
155 | static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr) | |
156 | { | |
4c674235 BZ |
157 | struct ide_host *host = pci_get_drvdata(dev); |
158 | ||
159 | if (host->host_priv) | |
165701d9 BZ |
160 | writeb(val, (void __iomem *)addr); |
161 | else | |
162 | pci_write_config_byte(dev, addr, val); | |
163 | } | |
164 | ||
165 | static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr) | |
166 | { | |
4c674235 BZ |
167 | struct ide_host *host = pci_get_drvdata(dev); |
168 | ||
169 | if (host->host_priv) | |
165701d9 BZ |
170 | writew(val, (void __iomem *)addr); |
171 | else | |
172 | pci_write_config_word(dev, addr, val); | |
173 | } | |
174 | ||
175 | static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr) | |
176 | { | |
4c674235 BZ |
177 | struct ide_host *host = pci_get_drvdata(dev); |
178 | ||
179 | if (host->host_priv) | |
165701d9 BZ |
180 | writel(val, (void __iomem *)addr); |
181 | else | |
182 | pci_write_config_dword(dev, addr, val); | |
183 | } | |
184 | ||
1da177e4 | 185 | /** |
2d5eaa6d BZ |
186 | * sil_udma_filter - compute UDMA mask |
187 | * @drive: IDE device | |
188 | * | |
189 | * Compute the available UDMA speeds for the device on the interface. | |
1da177e4 | 190 | * |
1da177e4 | 191 | * For the CMD680 this depends on the clocking mode (scsc), for the |
2d5eaa6d | 192 | * SI3112 SATA controller life is a bit simpler. |
1da177e4 | 193 | */ |
2d5eaa6d | 194 | |
438c4702 | 195 | static u8 sil_pata_udma_filter(ide_drive_t *drive) |
1da177e4 | 196 | { |
7b255436 SS |
197 | ide_hwif_t *hwif = drive->hwif; |
198 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
199 | unsigned long base = (unsigned long)hwif->hwif_data; | |
200 | u8 scsc, mask = 0; | |
1da177e4 | 201 | |
13572144 BZ |
202 | base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A; |
203 | ||
204 | scsc = sil_ioread8(dev, base); | |
1da177e4 | 205 | |
7b255436 SS |
206 | switch (scsc & 0x30) { |
207 | case 0x10: /* 133 */ | |
438c4702 | 208 | mask = ATA_UDMA6; |
7b255436 SS |
209 | break; |
210 | case 0x20: /* 2xPCI */ | |
438c4702 | 211 | mask = ATA_UDMA6; |
7b255436 SS |
212 | break; |
213 | case 0x00: /* 100 */ | |
438c4702 | 214 | mask = ATA_UDMA5; |
7b255436 SS |
215 | break; |
216 | default: /* Disabled ? */ | |
1da177e4 | 217 | BUG(); |
7b255436 | 218 | } |
438c4702 | 219 | |
2d5eaa6d | 220 | return mask; |
1da177e4 LT |
221 | } |
222 | ||
438c4702 BZ |
223 | static u8 sil_sata_udma_filter(ide_drive_t *drive) |
224 | { | |
4dde4492 BZ |
225 | char *m = (char *)&drive->id[ATA_ID_PROD]; |
226 | ||
227 | return strstr(m, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6; | |
438c4702 BZ |
228 | } |
229 | ||
1da177e4 | 230 | /** |
88b2b32b | 231 | * sil_set_pio_mode - set host controller for PIO mode |
e085b3ca | 232 | * @hwif: port |
88b2b32b | 233 | * @drive: drive |
1da177e4 LT |
234 | * |
235 | * Load the timing settings for this device mode into the | |
c9ef59ff | 236 | * controller. |
1da177e4 | 237 | */ |
328dcbb6 | 238 | |
e085b3ca | 239 | static void sil_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
1da177e4 | 240 | { |
7b255436 SS |
241 | static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; |
242 | static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; | |
328dcbb6 | 243 | |
165701d9 | 244 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
7e59ea21 | 245 | ide_drive_t *pair = ide_get_pair_dev(drive); |
1da177e4 LT |
246 | u32 speedt = 0; |
247 | u16 speedp = 0; | |
248 | unsigned long addr = siimage_seldev(drive, 0x04); | |
7b255436 | 249 | unsigned long tfaddr = siimage_selreg(hwif, 0x02); |
ffe5415c | 250 | unsigned long base = (unsigned long)hwif->hwif_data; |
e085b3ca | 251 | const u8 pio = drive->pio_mode - XFER_PIO_0; |
328dcbb6 | 252 | u8 tf_pio = pio; |
13572144 BZ |
253 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; |
254 | u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) | |
255 | : (mmio ? 0xB4 : 0x80); | |
ffe5415c | 256 | u8 mode = 0; |
123995b9 | 257 | u8 unit = drive->dn & 1; |
328dcbb6 BZ |
258 | |
259 | /* trim *taskfile* PIO to the slowest of the master/slave */ | |
7e59ea21 | 260 | if (pair) { |
bb430611 | 261 | u8 pair_pio = pair->pio_mode - XFER_PIO_0; |
328dcbb6 BZ |
262 | |
263 | if (pair_pio < tf_pio) | |
264 | tf_pio = pair_pio; | |
1da177e4 | 265 | } |
075cb655 | 266 | |
328dcbb6 BZ |
267 | /* cheat for now and use the docs */ |
268 | speedp = data_speed[pio]; | |
269 | speedt = tf_speed[tf_pio]; | |
270 | ||
165701d9 BZ |
271 | sil_iowrite16(dev, speedp, addr); |
272 | sil_iowrite16(dev, speedt, tfaddr); | |
273 | ||
274 | /* now set up IORDY */ | |
275 | speedp = sil_ioread16(dev, tfaddr - 2); | |
276 | speedp &= ~0x200; | |
165701d9 BZ |
277 | |
278 | mode = sil_ioread8(dev, base + addr_mask); | |
279 | mode &= ~(unit ? 0x30 : 0x03); | |
c9ef59ff BZ |
280 | |
281 | if (ide_pio_need_iordy(drive, pio)) { | |
282 | speedp |= 0x200; | |
283 | mode |= unit ? 0x10 : 0x01; | |
284 | } | |
285 | ||
286 | sil_iowrite16(dev, speedp, tfaddr - 2); | |
165701d9 | 287 | sil_iowrite8(dev, mode, base + addr_mask); |
1da177e4 LT |
288 | } |
289 | ||
1da177e4 | 290 | /** |
88b2b32b | 291 | * sil_set_dma_mode - set host controller for DMA mode |
8776168c | 292 | * @hwif: port |
88b2b32b | 293 | * @drive: drive |
1da177e4 | 294 | * |
88b2b32b | 295 | * Tune the SiI chipset for the desired DMA mode. |
1da177e4 | 296 | */ |
f212ff28 | 297 | |
8776168c | 298 | static void sil_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
1da177e4 | 299 | { |
7b255436 SS |
300 | static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; |
301 | static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; | |
302 | static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; | |
1da177e4 | 303 | |
36501650 | 304 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 305 | unsigned long base = (unsigned long)hwif->hwif_data; |
123995b9 BZ |
306 | u16 ultra = 0, multi = 0; |
307 | u8 mode = 0, unit = drive->dn & 1; | |
13572144 BZ |
308 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; |
309 | u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) | |
310 | : (mmio ? 0xB4 : 0x80); | |
1da177e4 LT |
311 | unsigned long ma = siimage_seldev(drive, 0x08); |
312 | unsigned long ua = siimage_seldev(drive, 0x0C); | |
8776168c | 313 | const u8 speed = drive->dma_mode; |
1da177e4 | 314 | |
13572144 | 315 | scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A)); |
7b255436 | 316 | mode = sil_ioread8 (dev, base + addr_mask); |
165701d9 BZ |
317 | multi = sil_ioread16(dev, ma); |
318 | ultra = sil_ioread16(dev, ua); | |
1da177e4 | 319 | |
7b255436 | 320 | mode &= ~(unit ? 0x30 : 0x03); |
1da177e4 LT |
321 | ultra &= ~0x3F; |
322 | scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; | |
323 | ||
324 | scsc = is_sata(hwif) ? 1 : scsc; | |
325 | ||
4db90a14 | 326 | if (speed >= XFER_UDMA_0) { |
7b255436 SS |
327 | multi = dma[2]; |
328 | ultra |= scsc ? ultra6[speed - XFER_UDMA_0] : | |
329 | ultra5[speed - XFER_UDMA_0]; | |
330 | mode |= unit ? 0x30 : 0x03; | |
4db90a14 BZ |
331 | } else { |
332 | multi = dma[speed - XFER_MW_DMA_0]; | |
7b255436 | 333 | mode |= unit ? 0x20 : 0x02; |
1da177e4 LT |
334 | } |
335 | ||
7b255436 | 336 | sil_iowrite8 (dev, mode, base + addr_mask); |
165701d9 BZ |
337 | sil_iowrite16(dev, multi, ma); |
338 | sil_iowrite16(dev, ultra, ua); | |
1da177e4 LT |
339 | } |
340 | ||
ec053e4e SS |
341 | static int sil_test_irq(ide_hwif_t *hwif) |
342 | { | |
343 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
344 | unsigned long addr = siimage_selreg(hwif, 1); | |
345 | u8 val = sil_ioread8(dev, addr); | |
346 | ||
347 | /* Return 1 if INTRQ asserted */ | |
348 | return (val & 8) ? 1 : 0; | |
349 | } | |
350 | ||
1da177e4 | 351 | /** |
5e37bdc0 | 352 | * siimage_mmio_dma_test_irq - check we caused an IRQ |
1da177e4 LT |
353 | * @drive: drive we are testing |
354 | * | |
355 | * Check if we caused an IDE DMA interrupt. We may also have caused | |
356 | * SATA status interrupts, if so we clean them up and continue. | |
357 | */ | |
5e37bdc0 BZ |
358 | |
359 | static int siimage_mmio_dma_test_irq(ide_drive_t *drive) | |
1da177e4 | 360 | { |
898ec223 | 361 | ide_hwif_t *hwif = drive->hwif; |
835457de BZ |
362 | void __iomem *sata_error_addr |
363 | = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET]; | |
1da177e4 | 364 | |
835457de | 365 | if (sata_error_addr) { |
7b255436 SS |
366 | unsigned long base = (unsigned long)hwif->hwif_data; |
367 | u32 ext_stat = readl((void __iomem *)(base + 0x10)); | |
368 | u8 watchdog = 0; | |
835457de | 369 | |
1da177e4 | 370 | if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { |
835457de BZ |
371 | u32 sata_error = readl(sata_error_addr); |
372 | ||
373 | writel(sata_error, sata_error_addr); | |
1da177e4 | 374 | watchdog = (sata_error & 0x00680000) ? 1 : 0; |
1da177e4 LT |
375 | printk(KERN_WARNING "%s: sata_error = 0x%08x, " |
376 | "watchdog = %d, %s\n", | |
7b255436 SS |
377 | drive->name, sata_error, watchdog, __func__); |
378 | } else | |
1da177e4 | 379 | watchdog = (ext_stat & 0x8000) ? 1 : 0; |
1da177e4 | 380 | |
7b255436 | 381 | ext_stat >>= 16; |
1da177e4 LT |
382 | if (!(ext_stat & 0x0404) && !watchdog) |
383 | return 0; | |
384 | } | |
385 | ||
386 | /* return 1 if INTR asserted */ | |
cab7f8ed | 387 | if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4) |
1da177e4 LT |
388 | return 1; |
389 | ||
1da177e4 LT |
390 | return 0; |
391 | } | |
392 | ||
5e37bdc0 BZ |
393 | static int siimage_dma_test_irq(ide_drive_t *drive) |
394 | { | |
13572144 | 395 | if (drive->hwif->host_flags & IDE_HFLAG_MMIO) |
5e37bdc0 BZ |
396 | return siimage_mmio_dma_test_irq(drive); |
397 | else | |
74414a91 | 398 | return ide_dma_test_irq(drive); |
5e37bdc0 BZ |
399 | } |
400 | ||
1da177e4 | 401 | /** |
438c4702 | 402 | * sil_sata_reset_poll - wait for SATA reset |
1da177e4 LT |
403 | * @drive: drive we are resetting |
404 | * | |
405 | * Poll the SATA phy and see whether it has come back from the dead | |
406 | * yet. | |
407 | */ | |
438c4702 BZ |
408 | |
409 | static int sil_sata_reset_poll(ide_drive_t *drive) | |
1da177e4 | 410 | { |
835457de BZ |
411 | ide_hwif_t *hwif = drive->hwif; |
412 | void __iomem *sata_status_addr | |
413 | = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET]; | |
414 | ||
415 | if (sata_status_addr) { | |
416 | /* SATA Status is available only when in MMIO mode */ | |
417 | u32 sata_stat = readl(sata_status_addr); | |
1da177e4 | 418 | |
835457de | 419 | if ((sata_stat & 0x03) != 0x03) { |
1da177e4 | 420 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", |
835457de | 421 | hwif->name, sata_stat); |
64a8f00f | 422 | return -ENXIO; |
1da177e4 | 423 | } |
1da177e4 | 424 | } |
438c4702 BZ |
425 | |
426 | return 0; | |
1da177e4 LT |
427 | } |
428 | ||
429 | /** | |
438c4702 | 430 | * sil_sata_pre_reset - reset hook |
1da177e4 LT |
431 | * @drive: IDE device being reset |
432 | * | |
433 | * For the SATA devices we need to handle recalibration/geometry | |
434 | * differently | |
435 | */ | |
1da177e4 | 436 | |
438c4702 BZ |
437 | static void sil_sata_pre_reset(ide_drive_t *drive) |
438 | { | |
439 | if (drive->media == ide_disk) { | |
ca1b96e0 BZ |
440 | drive->special_flags &= |
441 | ~(IDE_SFLAG_SET_GEOMETRY | IDE_SFLAG_RECALIBRATE); | |
1da177e4 LT |
442 | } |
443 | } | |
444 | ||
1da177e4 LT |
445 | /** |
446 | * init_chipset_siimage - set up an SI device | |
447 | * @dev: PCI device | |
1da177e4 LT |
448 | * |
449 | * Perform the initial PCI set up for this device. Attempt to switch | |
7b255436 | 450 | * to 133 MHz clocking if the system isn't already set up to do it. |
1da177e4 LT |
451 | */ |
452 | ||
2ed0ef54 | 453 | static int init_chipset_siimage(struct pci_dev *dev) |
1da177e4 | 454 | { |
4c674235 BZ |
455 | struct ide_host *host = pci_get_drvdata(dev); |
456 | void __iomem *ioaddr = host->host_priv; | |
165701d9 | 457 | unsigned long base, scsc_addr; |
4c674235 | 458 | u8 rev = dev->revision, tmp; |
1da177e4 | 459 | |
fc212bb1 | 460 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255); |
1da177e4 | 461 | |
4c674235 BZ |
462 | if (ioaddr) |
463 | pci_set_master(dev); | |
165701d9 BZ |
464 | |
465 | base = (unsigned long)ioaddr; | |
466 | ||
467 | if (ioaddr && pdev_is_sata(dev)) { | |
468 | u32 tmp32, irq_mask; | |
469 | ||
470 | /* make sure IDE0/1 interrupts are not masked */ | |
471 | irq_mask = (1 << 22) | (1 << 23); | |
472 | tmp32 = readl(ioaddr + 0x48); | |
473 | if (tmp32 & irq_mask) { | |
474 | tmp32 &= ~irq_mask; | |
475 | writel(tmp32, ioaddr + 0x48); | |
476 | readl(ioaddr + 0x48); /* flush */ | |
1da177e4 | 477 | } |
165701d9 BZ |
478 | writel(0, ioaddr + 0x148); |
479 | writel(0, ioaddr + 0x1C8); | |
1da177e4 LT |
480 | } |
481 | ||
165701d9 BZ |
482 | sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80); |
483 | sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84); | |
484 | ||
485 | scsc_addr = base ? (base + 0x4A) : 0x8A; | |
486 | tmp = sil_ioread8(dev, scsc_addr); | |
487 | ||
488 | switch (tmp & 0x30) { | |
489 | case 0x00: | |
7b255436 | 490 | /* On 100 MHz clocking, try and switch to 133 MHz */ |
165701d9 BZ |
491 | sil_iowrite8(dev, tmp | 0x10, scsc_addr); |
492 | break; | |
493 | case 0x30: | |
494 | /* Clocking is disabled, attempt to force 133MHz clocking. */ | |
495 | sil_iowrite8(dev, tmp & ~0x20, scsc_addr); | |
496 | case 0x10: | |
497 | /* On 133Mhz clocking. */ | |
498 | break; | |
499 | case 0x20: | |
500 | /* On PCIx2 clocking. */ | |
501 | break; | |
1da177e4 LT |
502 | } |
503 | ||
165701d9 | 504 | tmp = sil_ioread8(dev, scsc_addr); |
1da177e4 | 505 | |
7b255436 | 506 | sil_iowrite8 (dev, 0x72, base + 0xA1); |
165701d9 BZ |
507 | sil_iowrite16(dev, 0x328A, base + 0xA2); |
508 | sil_iowrite32(dev, 0x62DD62DD, base + 0xA4); | |
509 | sil_iowrite32(dev, 0x43924392, base + 0xA8); | |
510 | sil_iowrite32(dev, 0x40094009, base + 0xAC); | |
7b255436 | 511 | sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1); |
165701d9 BZ |
512 | sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2); |
513 | sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4); | |
514 | sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8); | |
515 | sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC); | |
516 | ||
517 | if (base && pdev_is_sata(dev)) { | |
518 | writel(0xFFFF0000, ioaddr + 0x108); | |
519 | writel(0xFFFF0000, ioaddr + 0x188); | |
520 | writel(0x00680000, ioaddr + 0x148); | |
521 | writel(0x00680000, ioaddr + 0x1C8); | |
522 | } | |
523 | ||
24cc434a BZ |
524 | /* report the clocking mode of the controller */ |
525 | if (!pdev_is_sata(dev)) { | |
526 | static const char *clk_str[] = | |
527 | { "== 100", "== 133", "== 2X PCI", "DISABLED!" }; | |
528 | ||
529 | tmp >>= 4; | |
a326b02b BZ |
530 | printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n", |
531 | pci_name(dev), clk_str[tmp & 3]); | |
24cc434a | 532 | } |
1da177e4 | 533 | |
1da177e4 LT |
534 | return 0; |
535 | } | |
536 | ||
537 | /** | |
538 | * init_mmio_iops_siimage - set up the iops for MMIO | |
539 | * @hwif: interface to set up | |
540 | * | |
541 | * The basic setup here is fairly simple, we can use standard MMIO | |
542 | * operations. However we do have to set the taskfile register offsets | |
7b255436 | 543 | * by hand as there isn't a standard defined layout for them this time. |
1da177e4 LT |
544 | * |
545 | * The hardware supports buffered taskfiles and also some rather nice | |
19c1ef5f | 546 | * extended PRD tables. For better SI3112 support use the libata driver |
1da177e4 LT |
547 | */ |
548 | ||
549 | static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) | |
550 | { | |
36501650 | 551 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
4c674235 BZ |
552 | struct ide_host *host = pci_get_drvdata(dev); |
553 | void *addr = host->host_priv; | |
1da177e4 | 554 | u8 ch = hwif->channel; |
4c3032d8 | 555 | struct ide_io_ports *io_ports = &hwif->io_ports; |
7b255436 | 556 | unsigned long base; |
4c3032d8 | 557 | |
1da177e4 | 558 | /* |
7b255436 | 559 | * Fill in the basic hwif bits |
1da177e4 | 560 | */ |
c5dd43ec | 561 | hwif->host_flags |= IDE_HFLAG_MMIO; |
761052e6 | 562 | |
7b255436 | 563 | hwif->hwif_data = addr; |
1da177e4 LT |
564 | |
565 | /* | |
7b255436 SS |
566 | * Now set up the hw. We have to do this ourselves as the |
567 | * MMIO layout isn't the same as the standard port based I/O. | |
1da177e4 | 568 | */ |
4c3032d8 | 569 | memset(io_ports, 0, sizeof(*io_ports)); |
1da177e4 LT |
570 | |
571 | base = (unsigned long)addr; | |
572 | if (ch) | |
573 | base += 0xC0; | |
574 | else | |
575 | base += 0x80; | |
576 | ||
577 | /* | |
7b255436 SS |
578 | * The buffered task file doesn't have status/control, so we |
579 | * can't currently use it sanely since we want to use LBA48 mode. | |
580 | */ | |
4c3032d8 BZ |
581 | io_ports->data_addr = base; |
582 | io_ports->error_addr = base + 1; | |
583 | io_ports->nsect_addr = base + 2; | |
584 | io_ports->lbal_addr = base + 3; | |
585 | io_ports->lbam_addr = base + 4; | |
586 | io_ports->lbah_addr = base + 5; | |
587 | io_ports->device_addr = base + 6; | |
588 | io_ports->status_addr = base + 7; | |
589 | io_ports->ctl_addr = base + 10; | |
1da177e4 LT |
590 | |
591 | if (pdev_is_sata(dev)) { | |
592 | base = (unsigned long)addr; | |
593 | if (ch) | |
594 | base += 0x80; | |
595 | hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; | |
596 | hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; | |
597 | hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; | |
1da177e4 LT |
598 | } |
599 | ||
9239b333 | 600 | hwif->irq = dev->irq; |
1da177e4 | 601 | |
9239b333 | 602 | hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00); |
1da177e4 LT |
603 | } |
604 | ||
605 | static int is_dev_seagate_sata(ide_drive_t *drive) | |
606 | { | |
4dde4492 BZ |
607 | const char *s = (const char *)&drive->id[ATA_ID_PROD]; |
608 | unsigned len = strnlen(s, ATA_ID_PROD_LEN); | |
1da177e4 | 609 | |
7b255436 | 610 | if ((len > 4) && (!memcmp(s, "ST", 2))) |
1da177e4 LT |
611 | if ((!memcmp(s + len - 2, "AS", 2)) || |
612 | (!memcmp(s + len - 3, "ASL", 3))) { | |
613 | printk(KERN_INFO "%s: applying pessimistic Seagate " | |
614 | "errata fix\n", drive->name); | |
615 | return 1; | |
616 | } | |
7b255436 | 617 | |
1da177e4 LT |
618 | return 0; |
619 | } | |
620 | ||
621 | /** | |
f01393e4 BZ |
622 | * sil_quirkproc - post probe fixups |
623 | * @drive: drive | |
1da177e4 LT |
624 | * |
625 | * Called after drive probe we use this to decide whether the | |
626 | * Seagate fixup must be applied. This used to be in init_iops but | |
627 | * that can occur before we know what drives are present. | |
628 | */ | |
629 | ||
36de9948 | 630 | static void sil_quirkproc(ide_drive_t *drive) |
1da177e4 | 631 | { |
f01393e4 BZ |
632 | ide_hwif_t *hwif = drive->hwif; |
633 | ||
7b255436 | 634 | /* Try and rise the rqsize */ |
f01393e4 | 635 | if (!is_sata(hwif) || !is_dev_seagate_sata(drive)) |
1da177e4 LT |
636 | hwif->rqsize = 128; |
637 | } | |
638 | ||
639 | /** | |
640 | * init_iops_siimage - set up iops | |
641 | * @hwif: interface to set up | |
642 | * | |
643 | * Do the basic setup for the SIIMAGE hardware interface | |
644 | * and then do the MMIO setup if we can. This is the first | |
645 | * look in we get for setting up the hwif so that we | |
646 | * can get the iops right before using them. | |
647 | */ | |
648 | ||
649 | static void __devinit init_iops_siimage(ide_hwif_t *hwif) | |
650 | { | |
36501650 | 651 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
4c674235 | 652 | struct ide_host *host = pci_get_drvdata(dev); |
36501650 | 653 | |
1da177e4 LT |
654 | hwif->hwif_data = NULL; |
655 | ||
656 | /* Pessimal until we finish probing */ | |
657 | hwif->rqsize = 15; | |
658 | ||
4c674235 BZ |
659 | if (host->host_priv) |
660 | init_mmio_iops_siimage(hwif); | |
1da177e4 LT |
661 | } |
662 | ||
663 | /** | |
ac95beed | 664 | * sil_cable_detect - cable detection |
1da177e4 LT |
665 | * @hwif: interface to check |
666 | * | |
7b255436 | 667 | * Check for the presence of an ATA66 capable cable on the interface. |
1da177e4 LT |
668 | */ |
669 | ||
f454cbe8 | 670 | static u8 sil_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 671 | { |
7b255436 SS |
672 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
673 | unsigned long addr = siimage_selreg(hwif, 0); | |
674 | u8 ata66 = sil_ioread8(dev, addr); | |
1da177e4 | 675 | |
49521f97 | 676 | return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
1da177e4 LT |
677 | } |
678 | ||
ac95beed BZ |
679 | static const struct ide_port_ops sil_pata_port_ops = { |
680 | .set_pio_mode = sil_set_pio_mode, | |
681 | .set_dma_mode = sil_set_dma_mode, | |
682 | .quirkproc = sil_quirkproc, | |
ec053e4e | 683 | .test_irq = sil_test_irq, |
ac95beed BZ |
684 | .udma_filter = sil_pata_udma_filter, |
685 | .cable_detect = sil_cable_detect, | |
686 | }; | |
687 | ||
688 | static const struct ide_port_ops sil_sata_port_ops = { | |
689 | .set_pio_mode = sil_set_pio_mode, | |
690 | .set_dma_mode = sil_set_dma_mode, | |
691 | .reset_poll = sil_sata_reset_poll, | |
692 | .pre_reset = sil_sata_pre_reset, | |
693 | .quirkproc = sil_quirkproc, | |
ec053e4e | 694 | .test_irq = sil_test_irq, |
ac95beed BZ |
695 | .udma_filter = sil_sata_udma_filter, |
696 | .cable_detect = sil_cable_detect, | |
697 | }; | |
698 | ||
b26b0c59 BH |
699 | static const struct ide_dma_ops sil_dma_ops = { |
700 | .dma_host_set = ide_dma_host_set, | |
701 | .dma_setup = ide_dma_setup, | |
b26b0c59 | 702 | .dma_start = ide_dma_start, |
653bcf52 | 703 | .dma_end = ide_dma_end, |
5e37bdc0 | 704 | .dma_test_irq = siimage_dma_test_irq, |
22117d6e | 705 | .dma_timer_expiry = ide_dma_sff_timer_expiry, |
b26b0c59 | 706 | .dma_lost_irq = ide_dma_lost_irq, |
592b5315 | 707 | .dma_sff_read_status = ide_dma_sff_read_status, |
5e37bdc0 BZ |
708 | }; |
709 | ||
ced3ec8a | 710 | #define DECLARE_SII_DEV(p_ops) \ |
1da177e4 | 711 | { \ |
ced3ec8a | 712 | .name = DRV_NAME, \ |
1da177e4 LT |
713 | .init_chipset = init_chipset_siimage, \ |
714 | .init_iops = init_iops_siimage, \ | |
ac95beed | 715 | .port_ops = p_ops, \ |
5e37bdc0 | 716 | .dma_ops = &sil_dma_ops, \ |
4099d143 | 717 | .pio_mask = ATA_PIO4, \ |
5f8b6c34 BZ |
718 | .mwdma_mask = ATA_MWDMA2, \ |
719 | .udma_mask = ATA_UDMA6, \ | |
1da177e4 LT |
720 | } |
721 | ||
85620436 | 722 | static const struct ide_port_info siimage_chipsets[] __devinitdata = { |
ced3ec8a BZ |
723 | /* 0: SiI680 */ DECLARE_SII_DEV(&sil_pata_port_ops), |
724 | /* 1: SiI3112 */ DECLARE_SII_DEV(&sil_sata_port_ops) | |
1da177e4 LT |
725 | }; |
726 | ||
727 | /** | |
7b255436 | 728 | * siimage_init_one - PCI layer discovery entry |
1da177e4 LT |
729 | * @dev: PCI device |
730 | * @id: ident table entry | |
731 | * | |
7b255436 | 732 | * Called by the PCI code when it finds an SiI680 or SiI3112 controller. |
1da177e4 LT |
733 | * We then use the IDE PCI generic helper to do most of the work. |
734 | */ | |
7b255436 SS |
735 | |
736 | static int __devinit siimage_init_one(struct pci_dev *dev, | |
737 | const struct pci_device_id *id) | |
1da177e4 | 738 | { |
4c674235 BZ |
739 | void __iomem *ioaddr = NULL; |
740 | resource_size_t bar5 = pci_resource_start(dev, 5); | |
741 | unsigned long barsize = pci_resource_len(dev, 5); | |
742 | int rc; | |
5e37bdc0 BZ |
743 | struct ide_port_info d; |
744 | u8 idx = id->driver_data; | |
4c674235 | 745 | u8 BA5_EN; |
5e37bdc0 BZ |
746 | |
747 | d = siimage_chipsets[idx]; | |
748 | ||
749 | if (idx) { | |
750 | static int first = 1; | |
751 | ||
752 | if (first) { | |
ced3ec8a | 753 | printk(KERN_INFO DRV_NAME ": For full SATA support you " |
5e37bdc0 BZ |
754 | "should use the libata sata_sil module.\n"); |
755 | first = 0; | |
756 | } | |
757 | ||
758 | d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA; | |
759 | } | |
760 | ||
4c674235 BZ |
761 | rc = pci_enable_device(dev); |
762 | if (rc) | |
763 | return rc; | |
764 | ||
765 | pci_read_config_byte(dev, 0x8A, &BA5_EN); | |
766 | if ((BA5_EN & 0x01) || bar5) { | |
767 | /* | |
768 | * Drop back to PIO if we can't map the MMIO. Some systems | |
769 | * seem to get terminally confused in the PCI spaces. | |
770 | */ | |
771 | if (!request_mem_region(bar5, barsize, d.name)) { | |
ced3ec8a | 772 | printk(KERN_WARNING DRV_NAME " %s: MMIO ports not " |
28cfd8af | 773 | "available\n", pci_name(dev)); |
4c674235 | 774 | } else { |
1f1ab274 | 775 | ioaddr = pci_ioremap_bar(dev, 5); |
4c674235 BZ |
776 | if (ioaddr == NULL) |
777 | release_mem_region(bar5, barsize); | |
778 | } | |
779 | } | |
780 | ||
781 | rc = ide_pci_init_one(dev, &d, ioaddr); | |
782 | if (rc) { | |
783 | if (ioaddr) { | |
784 | iounmap(ioaddr); | |
785 | release_mem_region(bar5, barsize); | |
786 | } | |
787 | pci_disable_device(dev); | |
788 | } | |
789 | ||
790 | return rc; | |
1da177e4 LT |
791 | } |
792 | ||
fe382580 BZ |
793 | static void __devexit siimage_remove(struct pci_dev *dev) |
794 | { | |
795 | struct ide_host *host = pci_get_drvdata(dev); | |
796 | void __iomem *ioaddr = host->host_priv; | |
797 | ||
798 | ide_pci_remove(dev); | |
799 | ||
800 | if (ioaddr) { | |
801 | resource_size_t bar5 = pci_resource_start(dev, 5); | |
802 | unsigned long barsize = pci_resource_len(dev, 5); | |
803 | ||
804 | iounmap(ioaddr); | |
805 | release_mem_region(bar5, barsize); | |
806 | } | |
807 | ||
808 | pci_disable_device(dev); | |
809 | } | |
810 | ||
9cbcc5e3 BZ |
811 | static const struct pci_device_id siimage_pci_tbl[] = { |
812 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 }, | |
1da177e4 | 813 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
9cbcc5e3 | 814 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 }, |
ced3ec8a | 815 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 1 }, |
1da177e4 LT |
816 | #endif |
817 | { 0, }, | |
818 | }; | |
819 | MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); | |
820 | ||
a9ab09e2 | 821 | static struct pci_driver siimage_pci_driver = { |
1da177e4 LT |
822 | .name = "SiI_IDE", |
823 | .id_table = siimage_pci_tbl, | |
824 | .probe = siimage_init_one, | |
a69999e2 | 825 | .remove = __devexit_p(siimage_remove), |
feb22b7f BZ |
826 | .suspend = ide_pci_suspend, |
827 | .resume = ide_pci_resume, | |
1da177e4 LT |
828 | }; |
829 | ||
82ab1eec | 830 | static int __init siimage_ide_init(void) |
1da177e4 | 831 | { |
a9ab09e2 | 832 | return ide_pci_register_driver(&siimage_pci_driver); |
1da177e4 LT |
833 | } |
834 | ||
fe382580 BZ |
835 | static void __exit siimage_ide_exit(void) |
836 | { | |
a9ab09e2 | 837 | pci_unregister_driver(&siimage_pci_driver); |
fe382580 BZ |
838 | } |
839 | ||
1da177e4 | 840 | module_init(siimage_ide_init); |
fe382580 | 841 | module_exit(siimage_ide_exit); |
1da177e4 LT |
842 | |
843 | MODULE_AUTHOR("Andre Hedrick, Alan Cox"); | |
844 | MODULE_DESCRIPTION("PCI driver module for SiI IDE"); | |
845 | MODULE_LICENSE("GPL"); |