ide: add ->fixup method to ide_hwif_t
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / setup-pci.c
CommitLineData
1da177e4
LT
1/*
2 * linux/drivers/ide/setup-pci.c Version 1.10 2002/08/19
3 *
4 * Copyright (c) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 *
6 * Copyright (c) 1995-1998 Mark Lord
7 * May be copied or modified under the terms of the GNU General Public License
1da177e4
LT
8 */
9
10/*
11 * This module provides support for automatic detection and
12 * configuration of all PCI IDE interfaces present in a system.
13 */
14
1da177e4
LT
15#include <linux/module.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/timer.h>
21#include <linux/mm.h>
22#include <linux/interrupt.h>
23#include <linux/ide.h>
24#include <linux/dma-mapping.h>
25
26#include <asm/io.h>
27#include <asm/irq.h>
28
29
30/**
31 * ide_match_hwif - match a PCI IDE against an ide_hwif
32 * @io_base: I/O base of device
33 * @bootable: set if its bootable
34 * @name: name of device
35 *
36 * Match a PCI IDE port against an entry in ide_hwifs[],
37 * based on io_base port if possible. Return the matching hwif,
38 * or a new hwif. If we find an error (clashing, out of devices, etc)
39 * return NULL
40 *
41 * FIXME: we need to handle mmio matches here too
42 */
43
44static ide_hwif_t *ide_match_hwif(unsigned long io_base, u8 bootable, const char *name)
45{
46 int h;
47 ide_hwif_t *hwif;
48
49 /*
50 * Look for a hwif with matching io_base specified using
51 * parameters to ide_setup().
52 */
53 for (h = 0; h < MAX_HWIFS; ++h) {
54 hwif = &ide_hwifs[h];
55 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
56 if (hwif->chipset == ide_forced)
57 return hwif; /* a perfect match */
58 }
59 }
60 /*
61 * Look for a hwif with matching io_base default value.
62 * If chipset is "ide_unknown", then claim that hwif slot.
63 * Otherwise, some other chipset has already claimed it.. :(
64 */
65 for (h = 0; h < MAX_HWIFS; ++h) {
66 hwif = &ide_hwifs[h];
67 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
68 if (hwif->chipset == ide_unknown)
69 return hwif; /* match */
70 printk(KERN_ERR "%s: port 0x%04lx already claimed by %s\n",
71 name, io_base, hwif->name);
72 return NULL; /* already claimed */
73 }
74 }
75 /*
76 * Okay, there is no hwif matching our io_base,
77 * so we'll just claim an unassigned slot.
78 * Give preference to claiming other slots before claiming ide0/ide1,
79 * just in case there's another interface yet-to-be-scanned
80 * which uses ports 1f0/170 (the ide0/ide1 defaults).
81 *
82 * Unless there is a bootable card that does not use the standard
83 * ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag.
84 */
85 if (bootable) {
86 for (h = 0; h < MAX_HWIFS; ++h) {
87 hwif = &ide_hwifs[h];
88 if (hwif->chipset == ide_unknown)
89 return hwif; /* pick an unused entry */
90 }
91 } else {
92 for (h = 2; h < MAX_HWIFS; ++h) {
93 hwif = ide_hwifs + h;
94 if (hwif->chipset == ide_unknown)
95 return hwif; /* pick an unused entry */
96 }
97 }
83d7dbc4 98 for (h = 0; h < 2 && h < MAX_HWIFS; ++h) {
1da177e4
LT
99 hwif = ide_hwifs + h;
100 if (hwif->chipset == ide_unknown)
101 return hwif; /* pick an unused entry */
102 }
103 printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", name);
104 return NULL;
105}
106
107/**
108 * ide_setup_pci_baseregs - place a PCI IDE controller native
109 * @dev: PCI device of interface to switch native
110 * @name: Name of interface
111 *
112 * We attempt to place the PCI interface into PCI native mode. If
113 * we succeed the BARs are ok and the controller is in PCI mode.
114 * Returns 0 on success or an errno code.
115 *
116 * FIXME: if we program the interface and then fail to set the BARS
117 * we don't switch it back to legacy mode. Do we actually care ??
118 */
119
120static int ide_setup_pci_baseregs (struct pci_dev *dev, const char *name)
121{
122 u8 progif = 0;
123
124 /*
125 * Place both IDE interfaces into PCI "native" mode:
126 */
127 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
128 (progif & 5) != 5) {
129 if ((progif & 0xa) != 0xa) {
130 printk(KERN_INFO "%s: device not capable of full "
131 "native PCI mode\n", name);
132 return -EOPNOTSUPP;
133 }
134 printk("%s: placing both ports into native PCI mode\n", name);
135 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
136 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
137 (progif & 5) != 5) {
138 printk(KERN_ERR "%s: rewrite of PROGIF failed, wanted "
139 "0x%04x, got 0x%04x\n",
140 name, progif|5, progif);
141 return -EOPNOTSUPP;
142 }
143 }
144 return 0;
145}
146
147#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
1da177e4
LT
148/**
149 * ide_get_or_set_dma_base - setup BMIBA
9ffcf364 150 * @d: IDE pci device data
1da177e4
LT
151 * @hwif: Interface
152 *
c58e79dd
BZ
153 * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space.
154 * Where a device has a partner that is already in DMA mode we check
155 * and enforce IDE simplex rules.
1da177e4
LT
156 */
157
9ffcf364 158static unsigned long ide_get_or_set_dma_base(ide_pci_device_t *d, ide_hwif_t *hwif)
1da177e4
LT
159{
160 unsigned long dma_base = 0;
161 struct pci_dev *dev = hwif->pci_dev;
162
1da177e4
LT
163 if (hwif->mmio)
164 return hwif->dma_base;
165
166 if (hwif->mate && hwif->mate->dma_base) {
167 dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8);
168 } else {
9ffcf364
BZ
169 u8 baridx = (d->host_flags & IDE_HFLAG_CS5520) ? 2 : 4;
170
171 dma_base = pci_resource_start(dev, baridx);
172
173 if (dma_base == 0)
174 printk(KERN_ERR "%s: DMA base is invalid\n", d->name);
1da177e4
LT
175 }
176
9ffcf364 177 if ((d->host_flags & IDE_HFLAG_CS5520) == 0 && dma_base) {
1da177e4
LT
178 u8 simplex_stat = 0;
179 dma_base += hwif->channel ? 8 : 0;
180
181 switch(dev->device) {
182 case PCI_DEVICE_ID_AL_M5219:
183 case PCI_DEVICE_ID_AL_M5229:
184 case PCI_DEVICE_ID_AMD_VIPER_7409:
185 case PCI_DEVICE_ID_CMD_643:
186 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
2f09a7f4 187 case PCI_DEVICE_ID_REVOLUTION:
31e8a465
BZ
188 simplex_stat = inb(dma_base + 2);
189 outb(simplex_stat & 0x60, dma_base + 2);
190 simplex_stat = inb(dma_base + 2);
1da177e4
LT
191 if (simplex_stat & 0x80) {
192 printk(KERN_INFO "%s: simplex device: "
9ffcf364
BZ
193 "DMA forced\n",
194 d->name);
1da177e4
LT
195 }
196 break;
197 default:
198 /*
199 * If the device claims "simplex" DMA,
200 * this means only one of the two interfaces
201 * can be trusted with DMA at any point in time.
202 * So we should enable DMA only on one of the
203 * two interfaces.
204 */
205 simplex_stat = hwif->INB(dma_base + 2);
206 if (simplex_stat & 0x80) {
207 /* simplex device? */
208/*
209 * At this point we haven't probed the drives so we can't make the
210 * appropriate decision. Really we should defer this problem
211 * until we tune the drive then try to grab DMA ownership if we want
212 * to be the DMA end. This has to be become dynamic to handle hot
213 * plug.
214 */
215 if (hwif->mate && hwif->mate->dma_base) {
216 printk(KERN_INFO "%s: simplex device: "
9ffcf364
BZ
217 "DMA disabled\n",
218 d->name);
1da177e4
LT
219 dma_base = 0;
220 }
221 }
222 }
223 }
224 return dma_base;
225}
226#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
227
228void ide_setup_pci_noise (struct pci_dev *dev, ide_pci_device_t *d)
229{
230 printk(KERN_INFO "%s: IDE controller at PCI slot %s\n",
231 d->name, pci_name(dev));
232}
233
234EXPORT_SYMBOL_GPL(ide_setup_pci_noise);
235
236
237/**
238 * ide_pci_enable - do PCI enables
239 * @dev: PCI device
240 * @d: IDE pci device data
241 *
242 * Enable the IDE PCI device. We attempt to enable the device in full
243 * but if that fails then we only need BAR4 so we will enable that.
244 *
245 * Returns zero on success or an error code
246 */
247
248static int ide_pci_enable(struct pci_dev *dev, ide_pci_device_t *d)
249{
250 int ret;
251
252 if (pci_enable_device(dev)) {
253 ret = pci_enable_device_bars(dev, 1 << 4);
254 if (ret < 0) {
255 printk(KERN_WARNING "%s: (ide_setup_pci_device:) "
256 "Could not enable device.\n", d->name);
257 goto out;
258 }
259 printk(KERN_WARNING "%s: BIOS configuration fixed.\n", d->name);
260 }
261
262 /*
263 * assume all devices can do 32-bit dma for now. we can add a
264 * dma mask field to the ide_pci_device_t if we need it (or let
265 * lower level driver set the dma mask)
266 */
267 ret = pci_set_dma_mask(dev, DMA_32BIT_MASK);
268 if (ret < 0) {
269 printk(KERN_ERR "%s: can't set dma mask\n", d->name);
270 goto out;
271 }
272
273 /* FIXME: Temporary - until we put in the hotplug interface logic
274 Check that the bits we want are not in use by someone else. */
275 ret = pci_request_region(dev, 4, "ide_tmp");
276 if (ret < 0)
277 goto out;
278
279 pci_release_region(dev, 4);
280out:
281 return ret;
282}
283
284/**
285 * ide_pci_configure - configure an unconfigured device
286 * @dev: PCI device
287 * @d: IDE pci device data
288 *
289 * Enable and configure the PCI device we have been passed.
290 * Returns zero on success or an error code.
291 */
292
293static int ide_pci_configure(struct pci_dev *dev, ide_pci_device_t *d)
294{
295 u16 pcicmd = 0;
296 /*
297 * PnP BIOS was *supposed* to have setup this device, but we
298 * can do it ourselves, so long as the BIOS has assigned an IRQ
299 * (or possibly the device is using a "legacy header" for IRQs).
300 * Maybe the user deliberately *disabled* the device,
301 * but we'll eventually ignore it again if no drives respond.
302 */
303 if (ide_setup_pci_baseregs(dev, d->name) || pci_write_config_word(dev, PCI_COMMAND, pcicmd|PCI_COMMAND_IO))
304 {
305 printk(KERN_INFO "%s: device disabled (BIOS)\n", d->name);
306 return -ENODEV;
307 }
308 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) {
309 printk(KERN_ERR "%s: error accessing PCI regs\n", d->name);
310 return -EIO;
311 }
312 if (!(pcicmd & PCI_COMMAND_IO)) {
313 printk(KERN_ERR "%s: unable to enable IDE controller\n", d->name);
314 return -ENXIO;
315 }
316 return 0;
317}
318
319/**
320 * ide_pci_check_iomem - check a register is I/O
321 * @dev: pci device
322 * @d: ide_pci_device
323 * @bar: bar number
324 *
325 * Checks if a BAR is configured and points to MMIO space. If so
326 * print an error and return an error code. Otherwise return 0
327 */
328
329static int ide_pci_check_iomem(struct pci_dev *dev, ide_pci_device_t *d, int bar)
330{
331 ulong flags = pci_resource_flags(dev, bar);
332
333 /* Unconfigured ? */
334 if (!flags || pci_resource_len(dev, bar) == 0)
335 return 0;
336
337 /* I/O space */
338 if(flags & PCI_BASE_ADDRESS_IO_MASK)
339 return 0;
340
341 /* Bad */
342 printk(KERN_ERR "%s: IO baseregs (BIOS) are reported "
343 "as MEM, report to "
344 "<andre@linux-ide.org>.\n", d->name);
345 return -EINVAL;
346}
347
348/**
349 * ide_hwif_configure - configure an IDE interface
350 * @dev: PCI device holding interface
351 * @d: IDE pci data
352 * @mate: Paired interface if any
353 *
354 * Perform the initial set up for the hardware interface structure. This
355 * is done per interface port rather than per PCI device. There may be
356 * more than one port per device.
357 *
358 * Returns the new hardware interface structure, or NULL on a failure
359 */
360
361static ide_hwif_t *ide_hwif_configure(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *mate, int port, int irq)
362{
363 unsigned long ctl = 0, base = 0;
364 ide_hwif_t *hwif;
7cab14a7 365 u8 bootable = (d->host_flags & IDE_HFLAG_BOOTABLE) ? 1 : 0;
1da177e4 366
a5d8c5c8 367 if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) {
1da177e4
LT
368 /* Possibly we should fail if these checks report true */
369 ide_pci_check_iomem(dev, d, 2*port);
370 ide_pci_check_iomem(dev, d, 2*port+1);
371
372 ctl = pci_resource_start(dev, 2*port+1);
373 base = pci_resource_start(dev, 2*port);
374 if ((ctl && !base) || (base && !ctl)) {
375 printk(KERN_ERR "%s: inconsistent baseregs (BIOS) "
376 "for port %d, skipping\n", d->name, port);
377 return NULL;
378 }
379 }
380 if (!ctl)
381 {
382 /* Use default values */
383 ctl = port ? 0x374 : 0x3f4;
384 base = port ? 0x170 : 0x1f0;
385 }
7cab14a7 386 if ((hwif = ide_match_hwif(base, bootable, d->name)) == NULL)
1da177e4
LT
387 return NULL; /* no room in ide_hwifs[] */
388 if (hwif->io_ports[IDE_DATA_OFFSET] != base ||
389 hwif->io_ports[IDE_CONTROL_OFFSET] != (ctl | 2)) {
390 memset(&hwif->hw, 0, sizeof(hwif->hw));
391#ifndef IDE_ARCH_OBSOLETE_INIT
392 ide_std_init_ports(&hwif->hw, base, (ctl | 2));
393 hwif->hw.io_ports[IDE_IRQ_OFFSET] = 0;
394#else
395 ide_init_hwif_ports(&hwif->hw, base, (ctl | 2), NULL);
396#endif
397 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
398 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
399 }
528a572d 400 hwif->chipset = d->chipset ? d->chipset : ide_pci;
1da177e4
LT
401 hwif->pci_dev = dev;
402 hwif->cds = (struct ide_pci_device_s *) d;
403 hwif->channel = port;
404
405 if (!hwif->irq)
406 hwif->irq = irq;
407 if (mate) {
408 hwif->mate = mate;
409 mate->mate = hwif;
410 }
411 return hwif;
412}
413
414/**
415 * ide_hwif_setup_dma - configure DMA interface
416 * @dev: PCI device
417 * @d: IDE pci data
418 * @hwif: Hardware interface we are configuring
419 *
420 * Set up the DMA base for the interface. Enable the master bits as
421 * necessary and attempt to bring the device DMA into a ready to use
422 * state
423 */
424
425#ifndef CONFIG_BLK_DEV_IDEDMA_PCI
426static void ide_hwif_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
427{
428}
429#else
430static void ide_hwif_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
431{
432 u16 pcicmd;
47b68788 433
1da177e4
LT
434 pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
435
47b68788 436 if ((d->host_flags & IDE_HFLAG_NO_AUTODMA) == 0 ||
1da177e4
LT
437 ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
438 (dev->class & 0x80))) {
9ffcf364 439 unsigned long dma_base = ide_get_or_set_dma_base(d, hwif);
1da177e4
LT
440 if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) {
441 /*
442 * Set up BM-DMA capability
443 * (PnP BIOS should have done this)
444 */
1da177e4
LT
445 pci_set_master(dev);
446 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) {
447 printk(KERN_ERR "%s: %s error updating PCICMD\n",
448 hwif->name, d->name);
449 dma_base = 0;
450 }
451 }
452 if (dma_base) {
453 if (d->init_dma) {
454 d->init_dma(hwif, dma_base);
455 } else {
456 ide_setup_dma(hwif, dma_base, 8);
457 }
458 } else {
459 printk(KERN_INFO "%s: %s Bus-Master DMA disabled "
460 "(BIOS)\n", hwif->name, d->name);
461 }
462 }
463}
1da177e4
LT
464#endif /* CONFIG_BLK_DEV_IDEDMA_PCI*/
465
466/**
467 * ide_setup_pci_controller - set up IDE PCI
468 * @dev: PCI device
469 * @d: IDE PCI data
470 * @noisy: verbose flag
471 * @config: returned as 1 if we configured the hardware
472 *
473 * Set up the PCI and controller side of the IDE interface. This brings
474 * up the PCI side of the device, checks that the device is enabled
475 * and enables it if need be
476 */
477
478static int ide_setup_pci_controller(struct pci_dev *dev, ide_pci_device_t *d, int noisy, int *config)
479{
480 int ret;
1da177e4
LT
481 u16 pcicmd;
482
483 if (noisy)
484 ide_setup_pci_noise(dev, d);
485
486 ret = ide_pci_enable(dev, d);
487 if (ret < 0)
488 goto out;
489
490 ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
491 if (ret < 0) {
492 printk(KERN_ERR "%s: error accessing PCI regs\n", d->name);
493 goto out;
494 }
495 if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */
496 ret = ide_pci_configure(dev, d);
497 if (ret < 0)
498 goto out;
499 *config = 1;
500 printk(KERN_INFO "%s: device enabled (Linux)\n", d->name);
501 }
502
1da177e4 503 if (noisy)
fc212bb1
BZ
504 printk(KERN_INFO "%s: chipset revision %d\n",
505 d->name, dev->revision);
1da177e4
LT
506out:
507 return ret;
508}
509
510/**
511 * ide_pci_setup_ports - configure ports/devices on PCI IDE
512 * @dev: PCI device
513 * @d: IDE pci device info
514 * @pciirq: IRQ line
515 * @index: ata index to update
516 *
517 * Scan the interfaces attached to this device and do any
518 * necessary per port setup. Attach the devices and ask the
519 * generic DMA layer to do its work for us.
520 *
521 * Normally called automaticall from do_ide_pci_setup_device,
522 * but is also used directly as a helper function by some controllers
523 * where the chipset setup is not the default PCI IDE one.
524 */
525
526void ide_pci_setup_ports(struct pci_dev *dev, ide_pci_device_t *d, int pciirq, ata_index_t *index)
527{
a5d8c5c8 528 int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port;
1da177e4 529 ide_hwif_t *hwif, *mate = NULL;
1da177e4
LT
530 u8 tmp;
531
532 index->all = 0xf0f0;
533
534 /*
535 * Set up the IDE ports
536 */
cf6e854e 537
a5d8c5c8 538 for (port = 0; port < channels; ++port) {
1da177e4
LT
539 ide_pci_enablebit_t *e = &(d->enablebits[port]);
540
1da177e4 541 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
cf6e854e
BZ
542 (tmp & e->mask) != e->val)) {
543 printk(KERN_INFO "%s: IDE port disabled\n", d->name);
1da177e4 544 continue; /* port not enabled */
cf6e854e 545 }
1da177e4 546
1da177e4
LT
547 if ((hwif = ide_hwif_configure(dev, d, mate, port, pciirq)) == NULL)
548 continue;
549
550 /* setup proper ancestral information */
551 hwif->gendev.parent = &dev->dev;
552
553 if (hwif->channel) {
554 index->b.high = hwif->index;
555 } else {
556 index->b.low = hwif->index;
557 }
558
559
560 if (d->init_iops)
561 d->init_iops(hwif);
562
9ffcf364 563 if ((d->host_flags & IDE_HFLAG_NO_DMA) == 0)
1da177e4 564 ide_hwif_setup_dma(dev, d, hwif);
9ffcf364 565
8acf28c0
BZ
566 if ((!hwif->irq && (d->host_flags & IDE_HFLAG_LEGACY_IRQS)) ||
567 (d->host_flags & IDE_HFLAG_FORCE_LEGACY_IRQS))
3985ee3b
BZ
568 hwif->irq = port ? 15 : 14;
569
fd9bb539
BZ
570 hwif->fixup = d->fixup;
571
6a824c92 572 hwif->host_flags = d->host_flags;
4099d143 573 hwif->pio_mask = d->pio_mask;
6a824c92 574
1c51361a
BZ
575 if ((d->host_flags & IDE_HFLAG_SERIALIZE) && hwif->mate)
576 hwif->mate->serialized = hwif->serialized = 1;
577
caea7602
BZ
578 if (d->host_flags & IDE_HFLAG_IO_32BIT) {
579 hwif->drives[0].io_32bit = 1;
580 hwif->drives[1].io_32bit = 1;
581 }
582
583 if (d->host_flags & IDE_HFLAG_UNMASK_IRQS) {
584 hwif->drives[0].unmask = 1;
585 hwif->drives[1].unmask = 1;
586 }
587
5f8b6c34
BZ
588 if (hwif->dma_base) {
589 hwif->swdma_mask = d->swdma_mask;
590 hwif->mwdma_mask = d->mwdma_mask;
591 hwif->ultra_mask = d->udma_mask;
592 }
593
85ad93ad
BZ
594 hwif->drives[0].autotune = 1;
595 hwif->drives[1].autotune = 1;
596
272a3709
BZ
597 if (d->host_flags & IDE_HFLAG_RQSIZE_256)
598 hwif->rqsize = 256;
599
1da177e4
LT
600 if (d->init_hwif)
601 /* Call chipset-specific routine
602 * for each enabled hwif
603 */
604 d->init_hwif(hwif);
605
606 mate = hwif;
1da177e4 607 }
1da177e4
LT
608}
609
610EXPORT_SYMBOL_GPL(ide_pci_setup_ports);
611
612/*
613 * ide_setup_pci_device() looks at the primary/secondary interfaces
614 * on a PCI IDE device and, if they are enabled, prepares the IDE driver
615 * for use with them. This generic code works for most PCI chipsets.
616 *
617 * One thing that is not standardized is the location of the
618 * primary/secondary interface "enable/disable" bits. For chipsets that
619 * we "know" about, this information is in the ide_pci_device_t struct;
620 * for all other chipsets, we just assume both interfaces are enabled.
621 */
622static int do_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t *d,
623 ata_index_t *index, u8 noisy)
624{
625 static ata_index_t ata_index = { .b = { .low = 0xff, .high = 0xff } };
626 int tried_config = 0;
627 int pciirq, ret;
628
629 ret = ide_setup_pci_controller(dev, d, noisy, &tried_config);
630 if (ret < 0)
631 goto out;
632
633 /*
634 * Can we trust the reported IRQ?
635 */
636 pciirq = dev->irq;
637
638 /* Is it an "IDE storage" device in non-PCI mode? */
639 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) {
640 if (noisy)
641 printk(KERN_INFO "%s: not 100%% native mode: "
642 "will probe irqs later\n", d->name);
643 /*
644 * This allows offboard ide-pci cards the enable a BIOS,
645 * verify interrupt settings of split-mirror pci-config
646 * space, place chipset into init-mode, and/or preserve
647 * an interrupt if the card is not native ide support.
648 */
649 ret = d->init_chipset ? d->init_chipset(dev, d->name) : 0;
650 if (ret < 0)
651 goto out;
652 pciirq = ret;
653 } else if (tried_config) {
654 if (noisy)
655 printk(KERN_INFO "%s: will probe irqs later\n", d->name);
656 pciirq = 0;
657 } else if (!pciirq) {
658 if (noisy)
659 printk(KERN_WARNING "%s: bad irq (%d): will probe later\n",
660 d->name, pciirq);
661 pciirq = 0;
662 } else {
663 if (d->init_chipset) {
664 ret = d->init_chipset(dev, d->name);
665 if (ret < 0)
666 goto out;
667 }
668 if (noisy)
1da177e4
LT
669 printk(KERN_INFO "%s: 100%% native mode on irq %d\n",
670 d->name, pciirq);
1da177e4
LT
671 }
672
673 /* FIXME: silent failure can happen */
674
675 *index = ata_index;
676 ide_pci_setup_ports(dev, d, pciirq, index);
677out:
678 return ret;
679}
680
681int ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t *d)
682{
5cbf79cd 683 ide_hwif_t *hwif = NULL, *mate = NULL;
1da177e4
LT
684 ata_index_t index_list;
685 int ret;
686
687 ret = do_ide_setup_pci_device(dev, d, &index_list, 1);
688 if (ret < 0)
689 goto out;
690
691 if ((index_list.b.low & 0xf0) != 0xf0)
5cbf79cd 692 hwif = &ide_hwifs[index_list.b.low];
1da177e4 693 if ((index_list.b.high & 0xf0) != 0xf0)
5cbf79cd 694 mate = &ide_hwifs[index_list.b.high];
1da177e4 695
5cbf79cd 696 if (hwif)
fd9bb539 697 probe_hwif_init(hwif);
5cbf79cd 698 if (mate)
fd9bb539 699 probe_hwif_init(mate);
5cbf79cd
BZ
700
701 if (hwif)
702 ide_proc_register_port(hwif);
703 if (mate)
704 ide_proc_register_port(mate);
1da177e4
LT
705out:
706 return ret;
707}
708
709EXPORT_SYMBOL_GPL(ide_setup_pci_device);
710
711int ide_setup_pci_devices(struct pci_dev *dev1, struct pci_dev *dev2,
712 ide_pci_device_t *d)
713{
714 struct pci_dev *pdev[] = { dev1, dev2 };
715 ata_index_t index_list[2];
716 int ret, i;
717
718 for (i = 0; i < 2; i++) {
719 ret = do_ide_setup_pci_device(pdev[i], d, index_list + i, !i);
720 /*
721 * FIXME: Mom, mom, they stole me the helper function to undo
722 * do_ide_setup_pci_device() on the first device!
723 */
724 if (ret < 0)
725 goto out;
726 }
727
728 for (i = 0; i < 2; i++) {
729 u8 idx[2] = { index_list[i].b.low, index_list[i].b.high };
730 int j;
731
732 for (j = 0; j < 2; j++) {
733 if ((idx[j] & 0xf0) != 0xf0)
734 probe_hwif_init(ide_hwifs + idx[j]);
735 }
736 }
737
5cbf79cd
BZ
738 for (i = 0; i < 2; i++) {
739 u8 idx[2] = { index_list[i].b.low, index_list[i].b.high };
740 int j;
741
742 for (j = 0; j < 2; j++) {
743 if ((idx[j] & 0xf0) != 0xf0)
744 ide_proc_register_port(ide_hwifs + idx[j]);
745 }
746 }
1da177e4
LT
747out:
748 return ret;
749}
750
751EXPORT_SYMBOL_GPL(ide_setup_pci_devices);
752
6d208b39 753#ifdef CONFIG_IDEPCI_PCIBUS_ORDER
1da177e4
LT
754/*
755 * Module interfaces
756 */
757
758static int pre_init = 1; /* Before first ordered IDE scan */
759static LIST_HEAD(ide_pci_drivers);
760
761/*
c37ea218 762 * __ide_pci_register_driver - attach IDE driver
1da177e4 763 * @driver: pci driver
863b18f4 764 * @module: owner module of the driver
1da177e4
LT
765 *
766 * Registers a driver with the IDE layer. The IDE layer arranges that
767 * boot time setup is done in the expected device order and then
768 * hands the controllers off to the core PCI code to do the rest of
769 * the work.
770 *
771 * The driver_data of the driver table must point to an ide_pci_device_t
772 * describing the interface.
773 *
774 * Returns are the same as for pci_register_driver
775 */
776
725522b5
GKH
777int __ide_pci_register_driver(struct pci_driver *driver, struct module *module,
778 const char *mod_name)
1da177e4
LT
779{
780 if(!pre_init)
725522b5 781 return __pci_register_driver(driver, module, mod_name);
863b18f4 782 driver->driver.owner = module;
1da177e4
LT
783 list_add_tail(&driver->node, &ide_pci_drivers);
784 return 0;
785}
786
863b18f4 787EXPORT_SYMBOL_GPL(__ide_pci_register_driver);
1da177e4 788
1da177e4
LT
789/**
790 * ide_scan_pcidev - find an IDE driver for a device
791 * @dev: PCI device to check
792 *
793 * Look for an IDE driver to handle the device we are considering.
794 * This is only used during boot up to get the ordering correct. After
795 * boot up the pci layer takes over the job.
796 */
797
798static int __init ide_scan_pcidev(struct pci_dev *dev)
799{
800 struct list_head *l;
801 struct pci_driver *d;
802
0505b55f 803 list_for_each(l, &ide_pci_drivers) {
1da177e4 804 d = list_entry(l, struct pci_driver, node);
0505b55f
SS
805 if (d->id_table) {
806 const struct pci_device_id *id = pci_match_id(d->id_table,
807 dev);
808 if (id != NULL && d->probe(dev, id) >= 0) {
809 dev->driver = d;
810 pci_dev_get(dev);
811 return 1;
1da177e4
LT
812 }
813 }
814 }
815 return 0;
816}
817
818/**
819 * ide_scan_pcibus - perform the initial IDE driver scan
820 * @scan_direction: set for reverse order scanning
821 *
822 * Perform the initial bus rather than driver ordered scan of the
823 * PCI drivers. After this all IDE pci handling becomes standard
824 * module ordering not traditionally ordered.
825 */
826
827void __init ide_scan_pcibus (int scan_direction)
828{
829 struct pci_dev *dev = NULL;
830 struct pci_driver *d;
831 struct list_head *l, *n;
832
833 pre_init = 0;
0505b55f
SS
834 if (!scan_direction)
835 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
1da177e4 836 ide_scan_pcidev(dev);
0505b55f
SS
837 else
838 while ((dev = pci_get_device_reverse(PCI_ANY_ID, PCI_ANY_ID, dev))
839 != NULL)
1da177e4 840 ide_scan_pcidev(dev);
1da177e4
LT
841
842 /*
843 * Hand the drivers over to the PCI layer now we
844 * are post init.
845 */
846
d61bcce9 847 list_for_each_safe(l, n, &ide_pci_drivers) {
1da177e4
LT
848 list_del(l);
849 d = list_entry(l, struct pci_driver, node);
0505b55f
SS
850 if (__pci_register_driver(d, d->driver.owner, d->driver.mod_name))
851 printk(KERN_ERR "%s: failed to register driver for %s\n",
852 __FUNCTION__, d->driver.mod_name);
1da177e4
LT
853 }
854}
6d208b39 855#endif