ide: don't set hwif->dma_ops in init_dma() method
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / setup-pci.c
CommitLineData
1da177e4 1/*
59bca8cc
BZ
2 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 1995-1998 Mark Lord
4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
58f189fc 5 *
1da177e4 6 * May be copied or modified under the terms of the GNU General Public License
1da177e4
LT
7 */
8
1da177e4
LT
9#include <linux/types.h>
10#include <linux/kernel.h>
11#include <linux/pci.h>
12#include <linux/init.h>
1da177e4
LT
13#include <linux/interrupt.h>
14#include <linux/ide.h>
15#include <linux/dma-mapping.h>
16
17#include <asm/io.h>
1da177e4 18
1da177e4
LT
19/**
20 * ide_setup_pci_baseregs - place a PCI IDE controller native
21 * @dev: PCI device of interface to switch native
22 * @name: Name of interface
23 *
24 * We attempt to place the PCI interface into PCI native mode. If
25 * we succeed the BARs are ok and the controller is in PCI mode.
846bb88a 26 * Returns 0 on success or an errno code.
1da177e4
LT
27 *
28 * FIXME: if we program the interface and then fail to set the BARS
29 * we don't switch it back to legacy mode. Do we actually care ??
30 */
846bb88a
PC
31
32static int ide_setup_pci_baseregs(struct pci_dev *dev, const char *name)
1da177e4
LT
33{
34 u8 progif = 0;
35
36 /*
37 * Place both IDE interfaces into PCI "native" mode:
38 */
39 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
40 (progif & 5) != 5) {
41 if ((progif & 0xa) != 0xa) {
28cfd8af
BZ
42 printk(KERN_INFO "%s %s: device not capable of full "
43 "native PCI mode\n", name, pci_name(dev));
1da177e4
LT
44 return -EOPNOTSUPP;
45 }
28cfd8af
BZ
46 printk(KERN_INFO "%s %s: placing both ports into native PCI "
47 "mode\n", name, pci_name(dev));
1da177e4
LT
48 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
49 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
50 (progif & 5) != 5) {
28cfd8af
BZ
51 printk(KERN_ERR "%s %s: rewrite of PROGIF failed, "
52 "wanted 0x%04x, got 0x%04x\n",
53 name, pci_name(dev), progif | 5, progif);
1da177e4
LT
54 return -EOPNOTSUPP;
55 }
56 }
57 return 0;
58}
59
60#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
28cfd8af 61static int ide_pci_clear_simplex(unsigned long dma_base, const char *name)
8ac2b42a
BZ
62{
63 u8 dma_stat = inb(dma_base + 2);
64
65 outb(dma_stat & 0x60, dma_base + 2);
66 dma_stat = inb(dma_base + 2);
28cfd8af
BZ
67
68 return (dma_stat & 0x80) ? 1 : 0;
8ac2b42a
BZ
69}
70
1da177e4 71/**
b123f56e 72 * ide_pci_dma_base - setup BMIBA
039788e1 73 * @hwif: IDE interface
b123f56e 74 * @d: IDE port info
1da177e4 75 *
c58e79dd 76 * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space.
1da177e4
LT
77 */
78
b123f56e 79unsigned long ide_pci_dma_base(ide_hwif_t *hwif, const struct ide_port_info *d)
1da177e4 80{
36501650
BZ
81 struct pci_dev *dev = to_pci_dev(hwif->dev);
82 unsigned long dma_base = 0;
1da177e4 83
13572144 84 if (hwif->host_flags & IDE_HFLAG_MMIO)
1da177e4
LT
85 return hwif->dma_base;
86
87 if (hwif->mate && hwif->mate->dma_base) {
88 dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8);
89 } else {
9ffcf364
BZ
90 u8 baridx = (d->host_flags & IDE_HFLAG_CS5520) ? 2 : 4;
91
92 dma_base = pci_resource_start(dev, baridx);
93
aea5d375 94 if (dma_base == 0) {
28cfd8af
BZ
95 printk(KERN_ERR "%s %s: DMA base is invalid\n",
96 d->name, pci_name(dev));
aea5d375
BZ
97 return 0;
98 }
1da177e4
LT
99 }
100
aea5d375
BZ
101 if (hwif->channel)
102 dma_base += 8;
103
ebb00fb5
BZ
104 return dma_base;
105}
106EXPORT_SYMBOL_GPL(ide_pci_dma_base);
107
108int ide_pci_check_simplex(ide_hwif_t *hwif, const struct ide_port_info *d)
109{
28cfd8af 110 struct pci_dev *dev = to_pci_dev(hwif->dev);
ebb00fb5
BZ
111 u8 dma_stat;
112
113 if (d->host_flags & (IDE_HFLAG_MMIO | IDE_HFLAG_CS5520))
8ac2b42a
BZ
114 goto out;
115
116 if (d->host_flags & IDE_HFLAG_CLEAR_SIMPLEX) {
28cfd8af
BZ
117 if (ide_pci_clear_simplex(hwif->dma_base, d->name))
118 printk(KERN_INFO "%s %s: simplex device: DMA forced\n",
119 d->name, pci_name(dev));
8ac2b42a
BZ
120 goto out;
121 }
122
123 /*
124 * If the device claims "simplex" DMA, this means that only one of
125 * the two interfaces can be trusted with DMA at any point in time
126 * (so we should enable DMA only on one of the two interfaces).
127 *
128 * FIXME: At this point we haven't probed the drives so we can't make
129 * the appropriate decision. Really we should defer this problem until
130 * we tune the drive then try to grab DMA ownership if we want to be
131 * the DMA end. This has to be become dynamic to handle hot-plug.
132 */
374e042c 133 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
8ac2b42a 134 if ((dma_stat & 0x80) && hwif->mate && hwif->mate->dma_base) {
28cfd8af
BZ
135 printk(KERN_INFO "%s %s: simplex device: DMA disabled\n",
136 d->name, pci_name(dev));
ebb00fb5 137 return -1;
1da177e4 138 }
8ac2b42a 139out:
ebb00fb5 140 return 0;
1da177e4 141}
ebb00fb5 142EXPORT_SYMBOL_GPL(ide_pci_check_simplex);
d54452fb
BZ
143
144/*
145 * Set up BM-DMA capability (PnP BIOS should have done this)
146 */
b123f56e 147int ide_pci_set_master(struct pci_dev *dev, const char *name)
d54452fb
BZ
148{
149 u16 pcicmd;
150
151 pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
152
153 if ((pcicmd & PCI_COMMAND_MASTER) == 0) {
154 pci_set_master(dev);
155
156 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) ||
157 (pcicmd & PCI_COMMAND_MASTER) == 0) {
28cfd8af
BZ
158 printk(KERN_ERR "%s %s: error updating PCICMD\n",
159 name, pci_name(dev));
d54452fb
BZ
160 return -EIO;
161 }
162 }
163
164 return 0;
165}
b123f56e 166EXPORT_SYMBOL_GPL(ide_pci_set_master);
1da177e4
LT
167#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
168
85620436 169void ide_setup_pci_noise(struct pci_dev *dev, const struct ide_port_info *d)
1da177e4 170{
28cfd8af
BZ
171 printk(KERN_INFO "%s %s: IDE controller (0x%04x:0x%04x rev 0x%02x)\n",
172 d->name, pci_name(dev),
173 dev->vendor, dev->device, dev->revision);
1da177e4 174}
1da177e4
LT
175EXPORT_SYMBOL_GPL(ide_setup_pci_noise);
176
177
178/**
179 * ide_pci_enable - do PCI enables
180 * @dev: PCI device
039788e1 181 * @d: IDE port info
1da177e4
LT
182 *
183 * Enable the IDE PCI device. We attempt to enable the device in full
09483916
BH
184 * but if that fails then we only need IO space. The PCI code should
185 * have setup the proper resources for us already for controllers in
186 * legacy mode.
846bb88a 187 *
1da177e4
LT
188 * Returns zero on success or an error code
189 */
039788e1 190
85620436 191static int ide_pci_enable(struct pci_dev *dev, const struct ide_port_info *d)
1da177e4 192{
0d1bad21 193 int ret, bars;
1da177e4
LT
194
195 if (pci_enable_device(dev)) {
09483916 196 ret = pci_enable_device_io(dev);
1da177e4 197 if (ret < 0) {
28cfd8af
BZ
198 printk(KERN_WARNING "%s %s: couldn't enable device\n",
199 d->name, pci_name(dev));
1da177e4
LT
200 goto out;
201 }
28cfd8af
BZ
202 printk(KERN_WARNING "%s %s: BIOS configuration fixed\n",
203 d->name, pci_name(dev));
1da177e4
LT
204 }
205
206 /*
039788e1
BZ
207 * assume all devices can do 32-bit DMA for now, we can add
208 * a DMA mask field to the struct ide_port_info if we need it
209 * (or let lower level driver set the DMA mask)
1da177e4
LT
210 */
211 ret = pci_set_dma_mask(dev, DMA_32BIT_MASK);
212 if (ret < 0) {
28cfd8af
BZ
213 printk(KERN_ERR "%s %s: can't set DMA mask\n",
214 d->name, pci_name(dev));
1da177e4
LT
215 goto out;
216 }
217
0d1bad21
BZ
218 if (d->host_flags & IDE_HFLAG_SINGLE)
219 bars = (1 << 2) - 1;
220 else
221 bars = (1 << 4) - 1;
1da177e4 222
0d1bad21
BZ
223 if ((d->host_flags & IDE_HFLAG_NO_DMA) == 0) {
224 if (d->host_flags & IDE_HFLAG_CS5520)
225 bars |= (1 << 2);
226 else
227 bars |= (1 << 4);
228 }
229
230 ret = pci_request_selected_regions(dev, bars, d->name);
231 if (ret < 0)
28cfd8af
BZ
232 printk(KERN_ERR "%s %s: can't reserve resources\n",
233 d->name, pci_name(dev));
1da177e4
LT
234out:
235 return ret;
236}
237
238/**
239 * ide_pci_configure - configure an unconfigured device
240 * @dev: PCI device
039788e1 241 * @d: IDE port info
1da177e4
LT
242 *
243 * Enable and configure the PCI device we have been passed.
244 * Returns zero on success or an error code.
245 */
039788e1 246
85620436 247static int ide_pci_configure(struct pci_dev *dev, const struct ide_port_info *d)
1da177e4
LT
248{
249 u16 pcicmd = 0;
250 /*
251 * PnP BIOS was *supposed* to have setup this device, but we
252 * can do it ourselves, so long as the BIOS has assigned an IRQ
253 * (or possibly the device is using a "legacy header" for IRQs).
254 * Maybe the user deliberately *disabled* the device,
255 * but we'll eventually ignore it again if no drives respond.
256 */
846bb88a
PC
257 if (ide_setup_pci_baseregs(dev, d->name) ||
258 pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) {
28cfd8af
BZ
259 printk(KERN_INFO "%s %s: device disabled (BIOS)\n",
260 d->name, pci_name(dev));
1da177e4
LT
261 return -ENODEV;
262 }
263 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) {
28cfd8af
BZ
264 printk(KERN_ERR "%s %s: error accessing PCI regs\n",
265 d->name, pci_name(dev));
1da177e4
LT
266 return -EIO;
267 }
268 if (!(pcicmd & PCI_COMMAND_IO)) {
28cfd8af
BZ
269 printk(KERN_ERR "%s %s: unable to enable IDE controller\n",
270 d->name, pci_name(dev));
1da177e4
LT
271 return -ENXIO;
272 }
273 return 0;
274}
275
276/**
277 * ide_pci_check_iomem - check a register is I/O
039788e1
BZ
278 * @dev: PCI device
279 * @d: IDE port info
280 * @bar: BAR number
1da177e4 281 *
1baccff8
SS
282 * Checks if a BAR is configured and points to MMIO space. If so,
283 * return an error code. Otherwise return 0
1da177e4 284 */
039788e1 285
1baccff8
SS
286static int ide_pci_check_iomem(struct pci_dev *dev, const struct ide_port_info *d,
287 int bar)
1da177e4
LT
288{
289 ulong flags = pci_resource_flags(dev, bar);
846bb88a 290
1da177e4
LT
291 /* Unconfigured ? */
292 if (!flags || pci_resource_len(dev, bar) == 0)
293 return 0;
294
1baccff8
SS
295 /* I/O space */
296 if (flags & IORESOURCE_IO)
1da177e4 297 return 0;
846bb88a 298
1da177e4 299 /* Bad */
1da177e4
LT
300 return -EINVAL;
301}
302
303/**
48c3c107 304 * ide_hw_configure - configure a hw_regs_t instance
1da177e4 305 * @dev: PCI device holding interface
039788e1 306 * @d: IDE port info
1ebf7493
BZ
307 * @port: port number
308 * @irq: PCI IRQ
c97c6aca 309 * @hw: hw_regs_t instance corresponding to this port
1da177e4
LT
310 *
311 * Perform the initial set up for the hardware interface structure. This
312 * is done per interface port rather than per PCI device. There may be
313 * more than one port per device.
314 *
48c3c107 315 * Returns zero on success or an error code.
1da177e4 316 */
039788e1 317
48c3c107
BZ
318static int ide_hw_configure(struct pci_dev *dev, const struct ide_port_info *d,
319 unsigned int port, int irq, hw_regs_t *hw)
1da177e4
LT
320{
321 unsigned long ctl = 0, base = 0;
1da177e4 322
a5d8c5c8 323 if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) {
1baccff8
SS
324 if (ide_pci_check_iomem(dev, d, 2 * port) ||
325 ide_pci_check_iomem(dev, d, 2 * port + 1)) {
28cfd8af
BZ
326 printk(KERN_ERR "%s %s: I/O baseregs (BIOS) are "
327 "reported as MEM for port %d!\n",
328 d->name, pci_name(dev), port);
48c3c107 329 return -EINVAL;
1baccff8 330 }
846bb88a 331
1da177e4
LT
332 ctl = pci_resource_start(dev, 2*port+1);
333 base = pci_resource_start(dev, 2*port);
c1da678b 334 } else {
1da177e4
LT
335 /* Use default values */
336 ctl = port ? 0x374 : 0x3f4;
337 base = port ? 0x170 : 0x1f0;
338 }
bad7c825 339
c1da678b 340 if (!base || !ctl) {
28cfd8af
BZ
341 printk(KERN_ERR "%s %s: bad PCI BARs for port %d, skipping\n",
342 d->name, pci_name(dev), port);
48c3c107 343 return -EINVAL;
c1da678b
BZ
344 }
345
c97c6aca
BZ
346 memset(hw, 0, sizeof(*hw));
347 hw->irq = irq;
348 hw->dev = &dev->dev;
349 hw->chipset = d->chipset ? d->chipset : ide_pci;
350 ide_std_init_ports(hw, base, ctl | 2);
351
48c3c107 352 return 0;
1da177e4
LT
353}
354
c413b9b9 355#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
1da177e4
LT
356/**
357 * ide_hwif_setup_dma - configure DMA interface
039788e1 358 * @hwif: IDE interface
c413b9b9 359 * @d: IDE port info
1da177e4
LT
360 *
361 * Set up the DMA base for the interface. Enable the master bits as
362 * necessary and attempt to bring the device DMA into a ready to use
363 * state
364 */
039788e1 365
b123f56e 366int ide_hwif_setup_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
1da177e4 367{
c413b9b9 368 struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 369
47b68788 370 if ((d->host_flags & IDE_HFLAG_NO_AUTODMA) == 0 ||
1da177e4
LT
371 ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
372 (dev->class & 0x80))) {
b123f56e 373 unsigned long base = ide_pci_dma_base(hwif, d);
d54452fb 374
ebb00fb5
BZ
375 if (base == 0)
376 return -1;
377
378 hwif->dma_base = base;
379
380 if (ide_pci_check_simplex(hwif, d) < 0)
381 return -1;
382
383 if (ide_pci_set_master(dev, d->name) < 0)
b123f56e 384 return -1;
d54452fb 385
13572144 386 if (hwif->host_flags & IDE_HFLAG_MMIO)
63158d5c
BZ
387 printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
388 else
389 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
390 hwif->name, base, base + 7);
391
392 hwif->extra_base = base + (hwif->channel ? 8 : 16);
393
b123f56e
BZ
394 if (ide_allocate_dma_engine(hwif))
395 return -1;
d54452fb 396
81e8d5a3 397 hwif->dma_ops = &sff_dma_ops;
b123f56e 398 }
d54452fb 399
b123f56e 400 return 0;
039788e1 401}
c413b9b9 402#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
1da177e4
LT
403
404/**
405 * ide_setup_pci_controller - set up IDE PCI
406 * @dev: PCI device
039788e1 407 * @d: IDE port info
1da177e4 408 * @noisy: verbose flag
1da177e4
LT
409 *
410 * Set up the PCI and controller side of the IDE interface. This brings
411 * up the PCI side of the device, checks that the device is enabled
412 * and enables it if need be
413 */
039788e1 414
a95925a3
BZ
415static int ide_setup_pci_controller(struct pci_dev *dev,
416 const struct ide_port_info *d, int noisy)
1da177e4
LT
417{
418 int ret;
1da177e4
LT
419 u16 pcicmd;
420
421 if (noisy)
422 ide_setup_pci_noise(dev, d);
423
424 ret = ide_pci_enable(dev, d);
425 if (ret < 0)
426 goto out;
427
428 ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
429 if (ret < 0) {
28cfd8af
BZ
430 printk(KERN_ERR "%s %s: error accessing PCI regs\n",
431 d->name, pci_name(dev));
1da177e4
LT
432 goto out;
433 }
434 if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */
435 ret = ide_pci_configure(dev, d);
436 if (ret < 0)
437 goto out;
28cfd8af
BZ
438 printk(KERN_INFO "%s %s: device enabled (Linux)\n",
439 d->name, pci_name(dev));
1da177e4
LT
440 }
441
1da177e4
LT
442out:
443 return ret;
444}
445
446/**
447 * ide_pci_setup_ports - configure ports/devices on PCI IDE
448 * @dev: PCI device
039788e1 449 * @d: IDE port info
1da177e4 450 * @pciirq: IRQ line
c97c6aca
BZ
451 * @hw: hw_regs_t instances corresponding to this PCI IDE device
452 * @hws: hw_regs_t pointers table to update
1da177e4
LT
453 *
454 * Scan the interfaces attached to this device and do any
455 * necessary per port setup. Attach the devices and ask the
456 * generic DMA layer to do its work for us.
457 *
458 * Normally called automaticall from do_ide_pci_setup_device,
459 * but is also used directly as a helper function by some controllers
460 * where the chipset setup is not the default PCI IDE one.
461 */
8447d9d5 462
c97c6aca 463void ide_pci_setup_ports(struct pci_dev *dev, const struct ide_port_info *d,
48c3c107 464 int pciirq, hw_regs_t *hw, hw_regs_t **hws)
1da177e4 465{
a5d8c5c8 466 int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port;
1da177e4
LT
467 u8 tmp;
468
1da177e4
LT
469 /*
470 * Set up the IDE ports
471 */
cf6e854e 472
a5d8c5c8 473 for (port = 0; port < channels; ++port) {
c0ae5023 474 const struct ide_pci_enablebit *e = &d->enablebits[port];
85620436 475
1da177e4 476 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
cf6e854e 477 (tmp & e->mask) != e->val)) {
28cfd8af
BZ
478 printk(KERN_INFO "%s %s: IDE port disabled\n",
479 d->name, pci_name(dev));
1da177e4 480 continue; /* port not enabled */
cf6e854e 481 }
1da177e4 482
48c3c107 483 if (ide_hw_configure(dev, d, port, pciirq, hw + port))
1da177e4
LT
484 continue;
485
c97c6aca 486 *(hws + port) = hw + port;
1ebf7493 487 }
1da177e4 488}
1da177e4
LT
489EXPORT_SYMBOL_GPL(ide_pci_setup_ports);
490
491/*
492 * ide_setup_pci_device() looks at the primary/secondary interfaces
493 * on a PCI IDE device and, if they are enabled, prepares the IDE driver
494 * for use with them. This generic code works for most PCI chipsets.
495 *
496 * One thing that is not standardized is the location of the
497 * primary/secondary interface "enable/disable" bits. For chipsets that
039788e1 498 * we "know" about, this information is in the struct ide_port_info;
1da177e4
LT
499 * for all other chipsets, we just assume both interfaces are enabled.
500 */
039788e1 501static int do_ide_setup_pci_device(struct pci_dev *dev,
85620436 502 const struct ide_port_info *d,
51d87ed0 503 u8 noisy)
1da177e4 504{
1da177e4
LT
505 int pciirq, ret;
506
1da177e4
LT
507 /*
508 * Can we trust the reported IRQ?
509 */
510 pciirq = dev->irq;
511
708e5f9e
BZ
512 /*
513 * This allows offboard ide-pci cards the enable a BIOS,
514 * verify interrupt settings of split-mirror pci-config
515 * space, place chipset into init-mode, and/or preserve
516 * an interrupt if the card is not native ide support.
517 */
a326b02b 518 ret = d->init_chipset ? d->init_chipset(dev) : 0;
708e5f9e
BZ
519 if (ret < 0)
520 goto out;
521
8c6de94c 522 if (ide_pci_is_in_compatibility_mode(dev)) {
1da177e4 523 if (noisy)
28cfd8af
BZ
524 printk(KERN_INFO "%s %s: not 100%% native mode: will "
525 "probe irqs later\n", d->name, pci_name(dev));
1da177e4 526 pciirq = ret;
28cfd8af
BZ
527 } else if (!pciirq && noisy) {
528 printk(KERN_WARNING "%s %s: bad irq (%d): will probe later\n",
529 d->name, pci_name(dev), pciirq);
530 } else if (noisy) {
531 printk(KERN_INFO "%s %s: 100%% native mode on irq %d\n",
532 d->name, pci_name(dev), pciirq);
1da177e4
LT
533 }
534
51d87ed0 535 ret = pciirq;
1da177e4
LT
536out:
537 return ret;
538}
539
6cdf6eb3
BZ
540int ide_pci_init_one(struct pci_dev *dev, const struct ide_port_info *d,
541 void *priv)
1da177e4 542{
6cdf6eb3 543 struct ide_host *host;
c97c6aca 544 hw_regs_t hw[4], *hws[] = { NULL, NULL, NULL, NULL };
1da177e4
LT
545 int ret;
546
a742d6cf
BZ
547 ret = ide_setup_pci_controller(dev, d, 1);
548 if (ret < 0)
549 goto out;
550
8c2eece5
BZ
551 ide_pci_setup_ports(dev, d, 0, &hw[0], &hws[0]);
552
6cdf6eb3
BZ
553 host = ide_host_alloc(d, hws);
554 if (host == NULL) {
555 ret = -ENOMEM;
556 goto out;
557 }
558
559 host->dev[0] = &dev->dev;
560
561 host->host_priv = priv;
562
ef0b0427 563 pci_set_drvdata(dev, host);
6cdf6eb3 564
51d87ed0 565 ret = do_ide_setup_pci_device(dev, d, 1);
8c2eece5
BZ
566 if (ret < 0)
567 goto out;
51d87ed0 568
8c2eece5
BZ
569 /* fixup IRQ */
570 hw[1].irq = hw[0].irq = ret;
1da177e4 571
6cdf6eb3
BZ
572 ret = ide_host_register(host, d, hws);
573 if (ret)
574 ide_host_free(host);
a742d6cf 575out:
1da177e4
LT
576 return ret;
577}
6cdf6eb3 578EXPORT_SYMBOL_GPL(ide_pci_init_one);
1da177e4 579
6cdf6eb3
BZ
580int ide_pci_init_two(struct pci_dev *dev1, struct pci_dev *dev2,
581 const struct ide_port_info *d, void *priv)
1da177e4
LT
582{
583 struct pci_dev *pdev[] = { dev1, dev2 };
6cdf6eb3 584 struct ide_host *host;
1da177e4 585 int ret, i;
c97c6aca 586 hw_regs_t hw[4], *hws[] = { NULL, NULL, NULL, NULL };
1da177e4
LT
587
588 for (i = 0; i < 2; i++) {
a742d6cf
BZ
589 ret = ide_setup_pci_controller(pdev[i], d, !i);
590 if (ret < 0)
591 goto out;
592
8c2eece5 593 ide_pci_setup_ports(pdev[i], d, 0, &hw[i*2], &hws[i*2]);
6cdf6eb3 594 }
8c2eece5 595
6cdf6eb3
BZ
596 host = ide_host_alloc(d, hws);
597 if (host == NULL) {
598 ret = -ENOMEM;
599 goto out;
600 }
601
602 host->dev[0] = &dev1->dev;
603 host->dev[1] = &dev2->dev;
604
605 host->host_priv = priv;
606
ef0b0427
BZ
607 pci_set_drvdata(pdev[0], host);
608 pci_set_drvdata(pdev[1], host);
6cdf6eb3
BZ
609
610 for (i = 0; i < 2; i++) {
51d87ed0
BZ
611 ret = do_ide_setup_pci_device(pdev[i], d, !i);
612
1da177e4
LT
613 /*
614 * FIXME: Mom, mom, they stole me the helper function to undo
615 * do_ide_setup_pci_device() on the first device!
616 */
617 if (ret < 0)
618 goto out;
51d87ed0 619
8c2eece5
BZ
620 /* fixup IRQ */
621 hw[i*2 + 1].irq = hw[i*2].irq = ret;
1da177e4
LT
622 }
623
6cdf6eb3
BZ
624 ret = ide_host_register(host, d, hws);
625 if (ret)
626 ide_host_free(host);
1da177e4
LT
627out:
628 return ret;
629}
6cdf6eb3 630EXPORT_SYMBOL_GPL(ide_pci_init_two);
ef0b0427
BZ
631
632void ide_pci_remove(struct pci_dev *dev)
633{
634 struct ide_host *host = pci_get_drvdata(dev);
635 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
636 int bars;
637
638 if (host->host_flags & IDE_HFLAG_SINGLE)
639 bars = (1 << 2) - 1;
640 else
641 bars = (1 << 4) - 1;
642
643 if ((host->host_flags & IDE_HFLAG_NO_DMA) == 0) {
644 if (host->host_flags & IDE_HFLAG_CS5520)
645 bars |= (1 << 2);
646 else
647 bars |= (1 << 4);
648 }
649
650 ide_host_remove(host);
651
652 if (dev2)
653 pci_release_selected_regions(dev2, bars);
654 pci_release_selected_regions(dev, bars);
655
656 if (dev2)
657 pci_disable_device(dev2);
658 pci_disable_device(dev);
659}
660EXPORT_SYMBOL_GPL(ide_pci_remove);
feb22b7f
BZ
661
662#ifdef CONFIG_PM
663int ide_pci_suspend(struct pci_dev *dev, pm_message_t state)
664{
665 pci_save_state(dev);
666 pci_disable_device(dev);
667 pci_set_power_state(dev, pci_choose_state(dev, state));
668
669 return 0;
670}
671EXPORT_SYMBOL_GPL(ide_pci_suspend);
672
673int ide_pci_resume(struct pci_dev *dev)
674{
675 struct ide_host *host = pci_get_drvdata(dev);
676 int rc;
677
678 pci_set_power_state(dev, PCI_D0);
679
680 rc = pci_enable_device(dev);
681 if (rc)
682 return rc;
683
684 pci_restore_state(dev);
685 pci_set_master(dev);
686
687 if (host->init_chipset)
688 host->init_chipset(dev);
689
690 return 0;
691}
692EXPORT_SYMBOL_GPL(ide_pci_resume);
693#endif