Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
59bca8cc BZ |
2 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
3 | * Copyright (C) 1995-1998 Mark Lord | |
4 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz | |
58f189fc | 5 | * |
1da177e4 | 6 | * May be copied or modified under the terms of the GNU General Public License |
1da177e4 LT |
7 | */ |
8 | ||
1da177e4 LT |
9 | #include <linux/module.h> |
10 | #include <linux/types.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/timer.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/ide.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | ||
20 | #include <asm/io.h> | |
21 | #include <asm/irq.h> | |
22 | ||
23 | ||
24 | /** | |
25 | * ide_match_hwif - match a PCI IDE against an ide_hwif | |
26 | * @io_base: I/O base of device | |
27 | * @bootable: set if its bootable | |
28 | * @name: name of device | |
29 | * | |
30 | * Match a PCI IDE port against an entry in ide_hwifs[], | |
31 | * based on io_base port if possible. Return the matching hwif, | |
32 | * or a new hwif. If we find an error (clashing, out of devices, etc) | |
33 | * return NULL | |
34 | * | |
35 | * FIXME: we need to handle mmio matches here too | |
36 | */ | |
37 | ||
38 | static ide_hwif_t *ide_match_hwif(unsigned long io_base, u8 bootable, const char *name) | |
39 | { | |
40 | int h; | |
41 | ide_hwif_t *hwif; | |
42 | ||
1da177e4 LT |
43 | /* |
44 | * Look for a hwif with matching io_base default value. | |
45 | * If chipset is "ide_unknown", then claim that hwif slot. | |
46 | * Otherwise, some other chipset has already claimed it.. :( | |
47 | */ | |
48 | for (h = 0; h < MAX_HWIFS; ++h) { | |
49 | hwif = &ide_hwifs[h]; | |
50 | if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) { | |
51 | if (hwif->chipset == ide_unknown) | |
52 | return hwif; /* match */ | |
53 | printk(KERN_ERR "%s: port 0x%04lx already claimed by %s\n", | |
54 | name, io_base, hwif->name); | |
55 | return NULL; /* already claimed */ | |
56 | } | |
57 | } | |
58 | /* | |
59 | * Okay, there is no hwif matching our io_base, | |
60 | * so we'll just claim an unassigned slot. | |
61 | * Give preference to claiming other slots before claiming ide0/ide1, | |
62 | * just in case there's another interface yet-to-be-scanned | |
63 | * which uses ports 1f0/170 (the ide0/ide1 defaults). | |
64 | * | |
65 | * Unless there is a bootable card that does not use the standard | |
66 | * ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag. | |
67 | */ | |
68 | if (bootable) { | |
69 | for (h = 0; h < MAX_HWIFS; ++h) { | |
70 | hwif = &ide_hwifs[h]; | |
71 | if (hwif->chipset == ide_unknown) | |
72 | return hwif; /* pick an unused entry */ | |
73 | } | |
74 | } else { | |
75 | for (h = 2; h < MAX_HWIFS; ++h) { | |
76 | hwif = ide_hwifs + h; | |
77 | if (hwif->chipset == ide_unknown) | |
78 | return hwif; /* pick an unused entry */ | |
79 | } | |
80 | } | |
83d7dbc4 | 81 | for (h = 0; h < 2 && h < MAX_HWIFS; ++h) { |
1da177e4 LT |
82 | hwif = ide_hwifs + h; |
83 | if (hwif->chipset == ide_unknown) | |
84 | return hwif; /* pick an unused entry */ | |
85 | } | |
86 | printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", name); | |
87 | return NULL; | |
88 | } | |
89 | ||
90 | /** | |
91 | * ide_setup_pci_baseregs - place a PCI IDE controller native | |
92 | * @dev: PCI device of interface to switch native | |
93 | * @name: Name of interface | |
94 | * | |
95 | * We attempt to place the PCI interface into PCI native mode. If | |
96 | * we succeed the BARs are ok and the controller is in PCI mode. | |
97 | * Returns 0 on success or an errno code. | |
98 | * | |
99 | * FIXME: if we program the interface and then fail to set the BARS | |
100 | * we don't switch it back to legacy mode. Do we actually care ?? | |
101 | */ | |
102 | ||
103 | static int ide_setup_pci_baseregs (struct pci_dev *dev, const char *name) | |
104 | { | |
105 | u8 progif = 0; | |
106 | ||
107 | /* | |
108 | * Place both IDE interfaces into PCI "native" mode: | |
109 | */ | |
110 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
111 | (progif & 5) != 5) { | |
112 | if ((progif & 0xa) != 0xa) { | |
113 | printk(KERN_INFO "%s: device not capable of full " | |
114 | "native PCI mode\n", name); | |
115 | return -EOPNOTSUPP; | |
116 | } | |
117 | printk("%s: placing both ports into native PCI mode\n", name); | |
118 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); | |
119 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
120 | (progif & 5) != 5) { | |
121 | printk(KERN_ERR "%s: rewrite of PROGIF failed, wanted " | |
122 | "0x%04x, got 0x%04x\n", | |
123 | name, progif|5, progif); | |
124 | return -EOPNOTSUPP; | |
125 | } | |
126 | } | |
127 | return 0; | |
128 | } | |
129 | ||
130 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
8ac2b42a BZ |
131 | static void ide_pci_clear_simplex(unsigned long dma_base, const char *name) |
132 | { | |
133 | u8 dma_stat = inb(dma_base + 2); | |
134 | ||
135 | outb(dma_stat & 0x60, dma_base + 2); | |
136 | dma_stat = inb(dma_base + 2); | |
137 | if (dma_stat & 0x80) | |
138 | printk(KERN_INFO "%s: simplex device: DMA forced\n", name); | |
139 | } | |
140 | ||
1da177e4 LT |
141 | /** |
142 | * ide_get_or_set_dma_base - setup BMIBA | |
039788e1 BZ |
143 | * @d: IDE port info |
144 | * @hwif: IDE interface | |
1da177e4 | 145 | * |
c58e79dd BZ |
146 | * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space. |
147 | * Where a device has a partner that is already in DMA mode we check | |
148 | * and enforce IDE simplex rules. | |
1da177e4 LT |
149 | */ |
150 | ||
85620436 | 151 | static unsigned long ide_get_or_set_dma_base(const struct ide_port_info *d, ide_hwif_t *hwif) |
1da177e4 | 152 | { |
36501650 BZ |
153 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
154 | unsigned long dma_base = 0; | |
8ac2b42a | 155 | u8 dma_stat = 0; |
1da177e4 | 156 | |
1da177e4 LT |
157 | if (hwif->mmio) |
158 | return hwif->dma_base; | |
159 | ||
160 | if (hwif->mate && hwif->mate->dma_base) { | |
161 | dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8); | |
162 | } else { | |
9ffcf364 BZ |
163 | u8 baridx = (d->host_flags & IDE_HFLAG_CS5520) ? 2 : 4; |
164 | ||
165 | dma_base = pci_resource_start(dev, baridx); | |
166 | ||
aea5d375 | 167 | if (dma_base == 0) { |
9ffcf364 | 168 | printk(KERN_ERR "%s: DMA base is invalid\n", d->name); |
aea5d375 BZ |
169 | return 0; |
170 | } | |
1da177e4 LT |
171 | } |
172 | ||
aea5d375 BZ |
173 | if (hwif->channel) |
174 | dma_base += 8; | |
175 | ||
8ac2b42a BZ |
176 | if (d->host_flags & IDE_HFLAG_CS5520) |
177 | goto out; | |
178 | ||
179 | if (d->host_flags & IDE_HFLAG_CLEAR_SIMPLEX) { | |
180 | ide_pci_clear_simplex(dma_base, d->name); | |
181 | goto out; | |
182 | } | |
183 | ||
184 | /* | |
185 | * If the device claims "simplex" DMA, this means that only one of | |
186 | * the two interfaces can be trusted with DMA at any point in time | |
187 | * (so we should enable DMA only on one of the two interfaces). | |
188 | * | |
189 | * FIXME: At this point we haven't probed the drives so we can't make | |
190 | * the appropriate decision. Really we should defer this problem until | |
191 | * we tune the drive then try to grab DMA ownership if we want to be | |
192 | * the DMA end. This has to be become dynamic to handle hot-plug. | |
193 | */ | |
194 | dma_stat = hwif->INB(dma_base + 2); | |
195 | if ((dma_stat & 0x80) && hwif->mate && hwif->mate->dma_base) { | |
196 | printk(KERN_INFO "%s: simplex device: DMA disabled\n", d->name); | |
197 | dma_base = 0; | |
1da177e4 | 198 | } |
8ac2b42a | 199 | out: |
1da177e4 LT |
200 | return dma_base; |
201 | } | |
202 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ | |
203 | ||
85620436 | 204 | void ide_setup_pci_noise(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 205 | { |
bde07e5e BZ |
206 | printk(KERN_INFO "%s: IDE controller (0x%04x:0x%04x rev 0x%02x) at " |
207 | " PCI slot %s\n", d->name, dev->vendor, dev->device, | |
208 | dev->revision, pci_name(dev)); | |
1da177e4 LT |
209 | } |
210 | ||
211 | EXPORT_SYMBOL_GPL(ide_setup_pci_noise); | |
212 | ||
213 | ||
214 | /** | |
215 | * ide_pci_enable - do PCI enables | |
216 | * @dev: PCI device | |
039788e1 | 217 | * @d: IDE port info |
1da177e4 LT |
218 | * |
219 | * Enable the IDE PCI device. We attempt to enable the device in full | |
09483916 BH |
220 | * but if that fails then we only need IO space. The PCI code should |
221 | * have setup the proper resources for us already for controllers in | |
222 | * legacy mode. | |
1da177e4 LT |
223 | * |
224 | * Returns zero on success or an error code | |
225 | */ | |
039788e1 | 226 | |
85620436 | 227 | static int ide_pci_enable(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 LT |
228 | { |
229 | int ret; | |
230 | ||
231 | if (pci_enable_device(dev)) { | |
09483916 | 232 | ret = pci_enable_device_io(dev); |
1da177e4 LT |
233 | if (ret < 0) { |
234 | printk(KERN_WARNING "%s: (ide_setup_pci_device:) " | |
235 | "Could not enable device.\n", d->name); | |
236 | goto out; | |
237 | } | |
238 | printk(KERN_WARNING "%s: BIOS configuration fixed.\n", d->name); | |
239 | } | |
240 | ||
241 | /* | |
039788e1 BZ |
242 | * assume all devices can do 32-bit DMA for now, we can add |
243 | * a DMA mask field to the struct ide_port_info if we need it | |
244 | * (or let lower level driver set the DMA mask) | |
1da177e4 LT |
245 | */ |
246 | ret = pci_set_dma_mask(dev, DMA_32BIT_MASK); | |
247 | if (ret < 0) { | |
248 | printk(KERN_ERR "%s: can't set dma mask\n", d->name); | |
249 | goto out; | |
250 | } | |
251 | ||
252 | /* FIXME: Temporary - until we put in the hotplug interface logic | |
253 | Check that the bits we want are not in use by someone else. */ | |
254 | ret = pci_request_region(dev, 4, "ide_tmp"); | |
255 | if (ret < 0) | |
256 | goto out; | |
257 | ||
258 | pci_release_region(dev, 4); | |
259 | out: | |
260 | return ret; | |
261 | } | |
262 | ||
263 | /** | |
264 | * ide_pci_configure - configure an unconfigured device | |
265 | * @dev: PCI device | |
039788e1 | 266 | * @d: IDE port info |
1da177e4 LT |
267 | * |
268 | * Enable and configure the PCI device we have been passed. | |
269 | * Returns zero on success or an error code. | |
270 | */ | |
039788e1 | 271 | |
85620436 | 272 | static int ide_pci_configure(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 LT |
273 | { |
274 | u16 pcicmd = 0; | |
275 | /* | |
276 | * PnP BIOS was *supposed* to have setup this device, but we | |
277 | * can do it ourselves, so long as the BIOS has assigned an IRQ | |
278 | * (or possibly the device is using a "legacy header" for IRQs). | |
279 | * Maybe the user deliberately *disabled* the device, | |
280 | * but we'll eventually ignore it again if no drives respond. | |
281 | */ | |
282 | if (ide_setup_pci_baseregs(dev, d->name) || pci_write_config_word(dev, PCI_COMMAND, pcicmd|PCI_COMMAND_IO)) | |
283 | { | |
284 | printk(KERN_INFO "%s: device disabled (BIOS)\n", d->name); | |
285 | return -ENODEV; | |
286 | } | |
287 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) { | |
288 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
289 | return -EIO; | |
290 | } | |
291 | if (!(pcicmd & PCI_COMMAND_IO)) { | |
292 | printk(KERN_ERR "%s: unable to enable IDE controller\n", d->name); | |
293 | return -ENXIO; | |
294 | } | |
295 | return 0; | |
296 | } | |
297 | ||
298 | /** | |
299 | * ide_pci_check_iomem - check a register is I/O | |
039788e1 BZ |
300 | * @dev: PCI device |
301 | * @d: IDE port info | |
302 | * @bar: BAR number | |
1da177e4 | 303 | * |
1baccff8 SS |
304 | * Checks if a BAR is configured and points to MMIO space. If so, |
305 | * return an error code. Otherwise return 0 | |
1da177e4 | 306 | */ |
039788e1 | 307 | |
1baccff8 SS |
308 | static int ide_pci_check_iomem(struct pci_dev *dev, const struct ide_port_info *d, |
309 | int bar) | |
1da177e4 LT |
310 | { |
311 | ulong flags = pci_resource_flags(dev, bar); | |
312 | ||
313 | /* Unconfigured ? */ | |
314 | if (!flags || pci_resource_len(dev, bar) == 0) | |
315 | return 0; | |
316 | ||
1baccff8 SS |
317 | /* I/O space */ |
318 | if (flags & IORESOURCE_IO) | |
1da177e4 LT |
319 | return 0; |
320 | ||
321 | /* Bad */ | |
1da177e4 LT |
322 | return -EINVAL; |
323 | } | |
324 | ||
325 | /** | |
326 | * ide_hwif_configure - configure an IDE interface | |
327 | * @dev: PCI device holding interface | |
039788e1 | 328 | * @d: IDE port info |
1ebf7493 BZ |
329 | * @port: port number |
330 | * @irq: PCI IRQ | |
1da177e4 LT |
331 | * |
332 | * Perform the initial set up for the hardware interface structure. This | |
333 | * is done per interface port rather than per PCI device. There may be | |
334 | * more than one port per device. | |
335 | * | |
336 | * Returns the new hardware interface structure, or NULL on a failure | |
337 | */ | |
039788e1 | 338 | |
1ebf7493 BZ |
339 | static ide_hwif_t *ide_hwif_configure(struct pci_dev *dev, |
340 | const struct ide_port_info *d, | |
341 | unsigned int port, int irq) | |
1da177e4 LT |
342 | { |
343 | unsigned long ctl = 0, base = 0; | |
344 | ide_hwif_t *hwif; | |
7cab14a7 | 345 | u8 bootable = (d->host_flags & IDE_HFLAG_BOOTABLE) ? 1 : 0; |
79127c37 | 346 | struct hw_regs_s hw; |
1da177e4 | 347 | |
a5d8c5c8 | 348 | if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) { |
1baccff8 SS |
349 | if (ide_pci_check_iomem(dev, d, 2 * port) || |
350 | ide_pci_check_iomem(dev, d, 2 * port + 1)) { | |
351 | printk(KERN_ERR "%s: I/O baseregs (BIOS) are reported " | |
352 | "as MEM for port %d!\n", d->name, port); | |
353 | return NULL; | |
354 | } | |
1da177e4 LT |
355 | |
356 | ctl = pci_resource_start(dev, 2*port+1); | |
357 | base = pci_resource_start(dev, 2*port); | |
358 | if ((ctl && !base) || (base && !ctl)) { | |
359 | printk(KERN_ERR "%s: inconsistent baseregs (BIOS) " | |
360 | "for port %d, skipping\n", d->name, port); | |
361 | return NULL; | |
362 | } | |
363 | } | |
364 | if (!ctl) | |
365 | { | |
366 | /* Use default values */ | |
367 | ctl = port ? 0x374 : 0x3f4; | |
368 | base = port ? 0x170 : 0x1f0; | |
369 | } | |
7cab14a7 | 370 | if ((hwif = ide_match_hwif(base, bootable, d->name)) == NULL) |
1da177e4 | 371 | return NULL; /* no room in ide_hwifs[] */ |
79127c37 BZ |
372 | |
373 | memset(&hw, 0, sizeof(hw)); | |
aab8ad9e | 374 | hw.irq = irq; |
79127c37 BZ |
375 | hw.dev = &dev->dev; |
376 | hw.chipset = d->chipset ? d->chipset : ide_pci; | |
377 | ide_std_init_ports(&hw, base, ctl | 2); | |
378 | ||
79127c37 BZ |
379 | ide_init_port_hw(hwif, &hw); |
380 | ||
36501650 | 381 | hwif->dev = &dev->dev; |
039788e1 | 382 | hwif->cds = d; |
1da177e4 | 383 | |
1da177e4 LT |
384 | return hwif; |
385 | } | |
386 | ||
c413b9b9 | 387 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
1da177e4 LT |
388 | /** |
389 | * ide_hwif_setup_dma - configure DMA interface | |
039788e1 | 390 | * @hwif: IDE interface |
c413b9b9 | 391 | * @d: IDE port info |
1da177e4 LT |
392 | * |
393 | * Set up the DMA base for the interface. Enable the master bits as | |
394 | * necessary and attempt to bring the device DMA into a ready to use | |
395 | * state | |
396 | */ | |
039788e1 | 397 | |
c413b9b9 | 398 | void ide_hwif_setup_dma(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 399 | { |
c413b9b9 | 400 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 401 | u16 pcicmd; |
47b68788 | 402 | |
1da177e4 LT |
403 | pci_read_config_word(dev, PCI_COMMAND, &pcicmd); |
404 | ||
47b68788 | 405 | if ((d->host_flags & IDE_HFLAG_NO_AUTODMA) == 0 || |
1da177e4 LT |
406 | ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && |
407 | (dev->class & 0x80))) { | |
9ffcf364 | 408 | unsigned long dma_base = ide_get_or_set_dma_base(d, hwif); |
1da177e4 LT |
409 | if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) { |
410 | /* | |
411 | * Set up BM-DMA capability | |
412 | * (PnP BIOS should have done this) | |
413 | */ | |
1da177e4 LT |
414 | pci_set_master(dev); |
415 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) { | |
416 | printk(KERN_ERR "%s: %s error updating PCICMD\n", | |
417 | hwif->name, d->name); | |
418 | dma_base = 0; | |
419 | } | |
420 | } | |
421 | if (dma_base) { | |
422 | if (d->init_dma) { | |
423 | d->init_dma(hwif, dma_base); | |
424 | } else { | |
ecf32796 | 425 | ide_setup_dma(hwif, dma_base); |
1da177e4 LT |
426 | } |
427 | } else { | |
428 | printk(KERN_INFO "%s: %s Bus-Master DMA disabled " | |
429 | "(BIOS)\n", hwif->name, d->name); | |
430 | } | |
431 | } | |
039788e1 | 432 | } |
c413b9b9 | 433 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
1da177e4 LT |
434 | |
435 | /** | |
436 | * ide_setup_pci_controller - set up IDE PCI | |
437 | * @dev: PCI device | |
039788e1 | 438 | * @d: IDE port info |
1da177e4 LT |
439 | * @noisy: verbose flag |
440 | * @config: returned as 1 if we configured the hardware | |
441 | * | |
442 | * Set up the PCI and controller side of the IDE interface. This brings | |
443 | * up the PCI side of the device, checks that the device is enabled | |
444 | * and enables it if need be | |
445 | */ | |
039788e1 | 446 | |
85620436 | 447 | static int ide_setup_pci_controller(struct pci_dev *dev, const struct ide_port_info *d, int noisy, int *config) |
1da177e4 LT |
448 | { |
449 | int ret; | |
1da177e4 LT |
450 | u16 pcicmd; |
451 | ||
452 | if (noisy) | |
453 | ide_setup_pci_noise(dev, d); | |
454 | ||
455 | ret = ide_pci_enable(dev, d); | |
456 | if (ret < 0) | |
457 | goto out; | |
458 | ||
459 | ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
460 | if (ret < 0) { | |
461 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
462 | goto out; | |
463 | } | |
464 | if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */ | |
465 | ret = ide_pci_configure(dev, d); | |
466 | if (ret < 0) | |
467 | goto out; | |
468 | *config = 1; | |
469 | printk(KERN_INFO "%s: device enabled (Linux)\n", d->name); | |
470 | } | |
471 | ||
1da177e4 LT |
472 | out: |
473 | return ret; | |
474 | } | |
475 | ||
476 | /** | |
477 | * ide_pci_setup_ports - configure ports/devices on PCI IDE | |
478 | * @dev: PCI device | |
039788e1 | 479 | * @d: IDE port info |
1da177e4 | 480 | * @pciirq: IRQ line |
8447d9d5 | 481 | * @idx: ATA index table to update |
1da177e4 LT |
482 | * |
483 | * Scan the interfaces attached to this device and do any | |
484 | * necessary per port setup. Attach the devices and ask the | |
485 | * generic DMA layer to do its work for us. | |
486 | * | |
487 | * Normally called automaticall from do_ide_pci_setup_device, | |
488 | * but is also used directly as a helper function by some controllers | |
489 | * where the chipset setup is not the default PCI IDE one. | |
490 | */ | |
8447d9d5 | 491 | |
85620436 | 492 | void ide_pci_setup_ports(struct pci_dev *dev, const struct ide_port_info *d, int pciirq, u8 *idx) |
1da177e4 | 493 | { |
a5d8c5c8 | 494 | int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port; |
c413b9b9 | 495 | ide_hwif_t *hwif; |
1da177e4 LT |
496 | u8 tmp; |
497 | ||
1da177e4 LT |
498 | /* |
499 | * Set up the IDE ports | |
500 | */ | |
cf6e854e | 501 | |
a5d8c5c8 | 502 | for (port = 0; port < channels; ++port) { |
85620436 BZ |
503 | const ide_pci_enablebit_t *e = &(d->enablebits[port]); |
504 | ||
1da177e4 | 505 | if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || |
cf6e854e BZ |
506 | (tmp & e->mask) != e->val)) { |
507 | printk(KERN_INFO "%s: IDE port disabled\n", d->name); | |
1da177e4 | 508 | continue; /* port not enabled */ |
cf6e854e | 509 | } |
1da177e4 | 510 | |
1ebf7493 BZ |
511 | hwif = ide_hwif_configure(dev, d, port, pciirq); |
512 | if (hwif == NULL) | |
1da177e4 LT |
513 | continue; |
514 | ||
8447d9d5 | 515 | *(idx + port) = hwif->index; |
1ebf7493 | 516 | } |
1da177e4 LT |
517 | } |
518 | ||
519 | EXPORT_SYMBOL_GPL(ide_pci_setup_ports); | |
520 | ||
521 | /* | |
522 | * ide_setup_pci_device() looks at the primary/secondary interfaces | |
523 | * on a PCI IDE device and, if they are enabled, prepares the IDE driver | |
524 | * for use with them. This generic code works for most PCI chipsets. | |
525 | * | |
526 | * One thing that is not standardized is the location of the | |
527 | * primary/secondary interface "enable/disable" bits. For chipsets that | |
039788e1 | 528 | * we "know" about, this information is in the struct ide_port_info; |
1da177e4 LT |
529 | * for all other chipsets, we just assume both interfaces are enabled. |
530 | */ | |
039788e1 | 531 | static int do_ide_setup_pci_device(struct pci_dev *dev, |
85620436 | 532 | const struct ide_port_info *d, |
8447d9d5 | 533 | u8 *idx, u8 noisy) |
1da177e4 | 534 | { |
1da177e4 LT |
535 | int tried_config = 0; |
536 | int pciirq, ret; | |
537 | ||
538 | ret = ide_setup_pci_controller(dev, d, noisy, &tried_config); | |
539 | if (ret < 0) | |
540 | goto out; | |
541 | ||
542 | /* | |
543 | * Can we trust the reported IRQ? | |
544 | */ | |
545 | pciirq = dev->irq; | |
546 | ||
547 | /* Is it an "IDE storage" device in non-PCI mode? */ | |
548 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) { | |
549 | if (noisy) | |
550 | printk(KERN_INFO "%s: not 100%% native mode: " | |
551 | "will probe irqs later\n", d->name); | |
552 | /* | |
553 | * This allows offboard ide-pci cards the enable a BIOS, | |
554 | * verify interrupt settings of split-mirror pci-config | |
555 | * space, place chipset into init-mode, and/or preserve | |
556 | * an interrupt if the card is not native ide support. | |
557 | */ | |
558 | ret = d->init_chipset ? d->init_chipset(dev, d->name) : 0; | |
559 | if (ret < 0) | |
560 | goto out; | |
561 | pciirq = ret; | |
562 | } else if (tried_config) { | |
563 | if (noisy) | |
564 | printk(KERN_INFO "%s: will probe irqs later\n", d->name); | |
565 | pciirq = 0; | |
566 | } else if (!pciirq) { | |
567 | if (noisy) | |
568 | printk(KERN_WARNING "%s: bad irq (%d): will probe later\n", | |
569 | d->name, pciirq); | |
570 | pciirq = 0; | |
571 | } else { | |
572 | if (d->init_chipset) { | |
573 | ret = d->init_chipset(dev, d->name); | |
574 | if (ret < 0) | |
575 | goto out; | |
576 | } | |
577 | if (noisy) | |
1da177e4 LT |
578 | printk(KERN_INFO "%s: 100%% native mode on irq %d\n", |
579 | d->name, pciirq); | |
1da177e4 LT |
580 | } |
581 | ||
582 | /* FIXME: silent failure can happen */ | |
583 | ||
8447d9d5 | 584 | ide_pci_setup_ports(dev, d, pciirq, idx); |
1da177e4 LT |
585 | out: |
586 | return ret; | |
587 | } | |
588 | ||
85620436 | 589 | int ide_setup_pci_device(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 590 | { |
8447d9d5 | 591 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 LT |
592 | int ret; |
593 | ||
8447d9d5 | 594 | ret = do_ide_setup_pci_device(dev, d, &idx[0], 1); |
1da177e4 | 595 | |
8447d9d5 | 596 | if (ret >= 0) |
c413b9b9 | 597 | ide_device_add(idx, d); |
1da177e4 | 598 | |
1da177e4 LT |
599 | return ret; |
600 | } | |
601 | ||
602 | EXPORT_SYMBOL_GPL(ide_setup_pci_device); | |
603 | ||
604 | int ide_setup_pci_devices(struct pci_dev *dev1, struct pci_dev *dev2, | |
85620436 | 605 | const struct ide_port_info *d) |
1da177e4 LT |
606 | { |
607 | struct pci_dev *pdev[] = { dev1, dev2 }; | |
1da177e4 | 608 | int ret, i; |
8447d9d5 | 609 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 LT |
610 | |
611 | for (i = 0; i < 2; i++) { | |
8447d9d5 | 612 | ret = do_ide_setup_pci_device(pdev[i], d, &idx[i*2], !i); |
1da177e4 LT |
613 | /* |
614 | * FIXME: Mom, mom, they stole me the helper function to undo | |
615 | * do_ide_setup_pci_device() on the first device! | |
616 | */ | |
617 | if (ret < 0) | |
618 | goto out; | |
619 | } | |
620 | ||
c413b9b9 | 621 | ide_device_add(idx, d); |
1da177e4 LT |
622 | out: |
623 | return ret; | |
624 | } | |
625 | ||
626 | EXPORT_SYMBOL_GPL(ide_setup_pci_devices); |