[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / via82cxxx.c

/*
 *
 * Version 3.50
 *
 * VIA IDE driver for Linux. Supported southbridges:
 *
 *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
 *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
 *   vt8235, vt8237, vt8237a
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
 *
 * Based on the work of:
 *	Michel Aubry
 *	Jeff Garzik
 *	Andre Hedrick
 *
 * Documentation:
 *	Obsolete device documentation publically available from via.com.tw
 *	Current device documentation available under NDA only
 */

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/dmi.h>

#include <asm/io.h>

#ifdef CONFIG_PPC_CHRP
#include <asm/processor.h>
#endif

#include "ide-timing.h"

#define VIA_IDE_ENABLE		0x40
#define VIA_IDE_CONFIG		0x41
#define VIA_FIFO_CONFIG		0x43
#define VIA_MISC_1		0x44
#define VIA_MISC_2		0x45
#define VIA_MISC_3		0x46
#define VIA_DRIVE_TIMING	0x48
#define VIA_8BIT_TIMING		0x4e
#define VIA_ADDRESS_SETUP	0x4c
#define VIA_UDMA_TIMING		0x50

#define VIA_BAD_PREQ		0x01 /* Crashes if PREQ# till DDACK# set */
#define VIA_BAD_CLK66		0x02 /* 66 MHz clock doesn't work correctly */
#define VIA_SET_FIFO		0x04 /* Needs to have FIFO split set */
#define VIA_NO_UNMASK		0x08 /* Doesn't work with IRQ unmasking on */
#define VIA_BAD_ID		0x10 /* Has wrong vendor ID (0x1107) */
#define VIA_BAD_AST		0x20 /* Don't touch Address Setup Timing */

/*
 * VIA SouthBridge chips.
 */

static struct via_isa_bridge {
	char *name;
	u16 id;
	u8 rev_min;
	u8 rev_max;
	u8 udma_mask;
	u8 flags;
} via_isa_bridges[] = {
	{ "vx800",	PCI_DEVICE_ID_VIA_VX800,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "cx700",	PCI_DEVICE_ID_VIA_CX700,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237s",	PCI_DEVICE_ID_VIA_8237S,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8251",	PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237a",	PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233a",	PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233c",	PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, ATA_UDMA5, },
	{ "vt8233",	PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, ATA_UDMA5, },
	{ "vt8231",	PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, ATA_UDMA5, },
	{ "vt82c686b",	PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, ATA_UDMA5, },
	{ "vt82c686a",	PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c686",	PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c596b",	PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c596a",	PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586a",	PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586",	PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f,      0x00, VIA_SET_FIFO },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
	{ NULL }
};

static unsigned int via_clock;
static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };

struct via82cxxx_dev
{
	struct via_isa_bridge *via_config;
	unsigned int via_80w;
};

/**
 *	via_set_speed			-	write timing registers
 *	@dev: PCI device
 *	@dn: device
 *	@timing: IDE timing data to use
 *
 *	via_set_speed writes timing values to the chipset registers
 */

static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
{
	struct pci_dev *dev = hwif->pci_dev;
	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
	u8 t;

	if (~vdev->via_config->flags & VIA_BAD_AST) {
		pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
		t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
		pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	}

	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
		((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
		((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	case ATA_UDMA4: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
	case ATA_UDMA5: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	case ATA_UDMA6: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	default: return;
	}

	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
}

/**
 *	via_set_drive		-	configure transfer mode
 *	@drive: Drive to set up
 *	@speed: desired speed
 *
 *	via_set_drive() computes timing values configures the chipset to
 *	a desired transfer mode.  It also can be called by upper layers.
 */

static void via_set_drive(ide_drive_t *drive, const u8 speed)
{
	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
	struct via82cxxx_dev *vdev = pci_get_drvdata(drive->hwif->pci_dev);
	struct ide_timing t, p;
	unsigned int T, UT;

	T = 1000000000 / via_clock;

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: UT = T;   break;
	case ATA_UDMA4: UT = T/2; break;
	case ATA_UDMA5: UT = T/3; break;
	case ATA_UDMA6: UT = T/4; break;
	default:	UT = T;
	}

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer->present) {
		ide_timing_compute(peer, peer->current_speed, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	via_set_speed(HWIF(drive), drive->dn, &t);
}

/**
 *	via_set_pio_mode	-	set host controller for PIO mode
 *	@drive: drive
 *	@pio: PIO mode number
 *
 *	A callback from the upper layers for PIO-only tuning.
 */

static void via_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	via_set_drive(drive, XFER_PIO_0 + pio);
}

static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
{
	struct via_isa_bridge *via_config;

	for (via_config = via_isa_bridges; via_config->id; via_config++)
		if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
			!!(via_config->flags & VIA_BAD_ID),
			via_config->id, NULL))) {

			if ((*isa)->revision >= via_config->rev_min &&
			    (*isa)->revision <= via_config->rev_max)
				break;
			pci_dev_put(*isa);
		}

	return via_config;
}

/*
 * Check and handle 80-wire cable presence
 */
static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
{
	int i;

	switch (vdev->via_config->udma_mask) {
		case ATA_UDMA4:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> (i & 16)) & 8) &&
				    ((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 2)) {
					/*
					 * 2x PCI clock and
					 * UDMA w/ < 3T/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA5:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 4))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA6:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 6))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;
	}
}

/**
 *	init_chipset_via82cxxx	-	initialization handler
 *	@dev: PCI device
 *	@name: Name of interface
 *
 *	The initialization callback. Here we determine the IDE chip type
 *	and initialize its drive independent registers.
 */

static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
{
	struct pci_dev *isa = NULL;
	struct via82cxxx_dev *vdev;
	struct via_isa_bridge *via_config;
	u8 t, v;
	u32 u;

	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
	if (!vdev) {
		printk(KERN_ERR "VP_IDE: out of memory :(\n");
		return -ENOMEM;
	}
	pci_set_drvdata(dev, vdev);

	/*
	 * Find the ISA bridge to see how good the IDE is.
	 */
	vdev->via_config = via_config = via_config_find(&isa);

	/* We checked this earlier so if it fails here deeep badness
	   is involved */

	BUG_ON(!via_config->id);

	/*
	 * Detect cable and configure Clk66
	 */
	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);

	via_cable_detect(vdev, u);

	if (via_config->udma_mask == ATA_UDMA4) {
		/* Enable Clk66 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
	} else if (via_config->flags & VIA_BAD_CLK66) {
		/* Would cause trouble on 596a and 686 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	}

	/*
	 * Check whether interfaces are enabled.
	 */

	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);

	/*
	 * Set up FIFO sizes and thresholds.
	 */

	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);

	/* Disable PREQ# till DDACK# */
	if (via_config->flags & VIA_BAD_PREQ) {
		/* Would crash on 586b rev 41 */
		t &= 0x7f;
	}

	/* Fix FIFO split between channels */
	if (via_config->flags & VIA_SET_FIFO) {
		t &= (t & 0x9f);
		switch (v & 3) {
			case 2: t |= 0x00; break;	/* 16 on primary */
			case 1: t |= 0x60; break;	/* 16 on secondary */
			case 3: t |= 0x20; break;	/* 8 pri 8 sec */
		}
	}

	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);

	/*
	 * Determine system bus clock.
	 */

	via_clock = system_bus_clock() * 1000;

	switch (via_clock) {
		case 33000: via_clock = 33333; break;
		case 37000: via_clock = 37500; break;
		case 41000: via_clock = 41666; break;
	}

	if (via_clock < 20000 || via_clock > 50000) {
		printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
			"impossible (%d), using 33 MHz instead.\n", via_clock);
		printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
			"to assume 80-wire cable.\n");
		via_clock = 33333;
	}

	/*
	 * Print the boot message.
	 */

	printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s "
		"controller on pci%s\n",
		via_config->name, isa->revision,
		via_config->udma_mask ? "U" : "MW",
		via_dma[via_config->udma_mask ?
			(fls(via_config->udma_mask) - 1) : 0],
		pci_name(dev));

	pci_dev_put(isa);
	return 0;
}

/*
 *	Cable special cases
 */

static const struct dmi_system_id cable_dmi_table[] = {
	{
		.ident = "Acer Ferrari 3400",
		.matches = {
			DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
			DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
		},
	},
	{ }
};

static int via_cable_override(struct pci_dev *pdev)
{
	/* Systems by DMI */
	if (dmi_check_system(cable_dmi_table))
		return 1;

	/* Arima W730-K8/Targa Visionary 811/... */
	if (pdev->subsystem_vendor == 0x161F &&
	    pdev->subsystem_device == 0x2032)
		return 1;

	return 0;
}

static u8 __devinit via82cxxx_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = hwif->pci_dev;
	struct via82cxxx_dev *vdev = pci_get_drvdata(pdev);

	if (via_cable_override(pdev))
		return ATA_CBL_PATA40_SHORT;

	if ((vdev->via_80w >> hwif->channel) & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &via_set_pio_mode;
	hwif->set_dma_mode = &via_set_drive;

	if (!hwif->dma_base)
		return;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
		hwif->cbl = via82cxxx_cable_detect(hwif);
}

static const struct ide_port_info via82cxxx_chipset __devinitdata = {
	.name		= "VP_IDE",
	.init_chipset	= init_chipset_via82cxxx,
	.init_hwif	= init_hwif_via82cxxx,
	.enablebits	= { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
	.host_flags	= IDE_HFLAG_PIO_NO_BLACKLIST |
			  IDE_HFLAG_PIO_NO_DOWNGRADE |
			  IDE_HFLAG_ABUSE_SET_DMA_MODE |
			  IDE_HFLAG_POST_SET_MODE |
			  IDE_HFLAG_IO_32BIT |
			  IDE_HFLAG_BOOTABLE,
	.pio_mask	= ATA_PIO5,
	.swdma_mask	= ATA_SWDMA2,
	.mwdma_mask	= ATA_MWDMA2,
};

static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct pci_dev *isa = NULL;
	struct via_isa_bridge *via_config;
	u8 idx = id->driver_data;
	struct ide_port_info d;

	d = via82cxxx_chipset;

	/*
	 * Find the ISA bridge and check we know what it is.
	 */
	via_config = via_config_find(&isa);
	pci_dev_put(isa);
	if (!via_config->id) {
		printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
		return -ENODEV;
	}

	if (idx == 0)
		d.host_flags |= IDE_HFLAG_NO_AUTODMA;
	else
		d.enablebits[1].reg = d.enablebits[0].reg = 0;

	if ((via_config->flags & VIA_NO_UNMASK) == 0)
		d.host_flags |= IDE_HFLAG_UNMASK_IRQS;

#ifdef CONFIG_PPC_CHRP
	if (machine_is(chrp) && _chrp_type == _CHRP_Pegasos)
		d.host_flags |= IDE_HFLAG_FORCE_LEGACY_IRQS;
#endif

	d.udma_mask = via_config->udma_mask;

	return ide_setup_pci_device(dev, &d);
}

static const struct pci_device_id via_pci_tbl[] = {
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1),  0 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1),  0 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410),      1 },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, via_pci_tbl);

static struct pci_driver driver = {
	.name 		= "VIA_IDE",
	.id_table 	= via_pci_tbl,
	.probe 		= via_init_one,
};

static int __init via_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(via_ide_init);

MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for VIA IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	*
6157332e	3	* Version 3.50
1da177e4 LT	4	*
	5	* VIA IDE driver for Linux. Supported southbridges:
	6	*
	7	* vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
	8	* vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
a7dec1e0	9	* vt8235, vt8237, vt8237a
1da177e4 LT	10	*
1da177e4 LT	11	* Copyright (c) 2000-2002 Vojtech Pavlik
75b1d975	12	* Copyright (c) 2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	13	*
	14	* Based on the work of:
	15	* Michel Aubry
	16	* Jeff Garzik
	17	* Andre Hedrick
	18	*
	19	* Documentation:
	20	* Obsolete device documentation publically available from via.com.tw
	21	* Current device documentation available under NDA only
	22	*/
	23
	24	/*
	25	* This program is free software; you can redistribute it and/or modify it
	26	* under the terms of the GNU General Public License version 2 as published by
	27	* the Free Software Foundation.
	28	*/
	29
1da177e4 LT	30	#include <linux/module.h>
	31	#include <linux/kernel.h>
	32	#include <linux/ioport.h>
	33	#include <linux/blkdev.h>
	34	#include <linux/pci.h>
	35	#include <linux/init.h>
	36	#include <linux/ide.h>
bdab00b7 BZ	37	#include <linux/dmi.h>
bdab00b7 BZ	38
1da177e4 LT	39	#include <asm/io.h>
1da177e4 LT	40
74a9d5f1	41	#ifdef CONFIG_PPC_CHRP
1da177e4 LT	42	#include <asm/processor.h>
	43	#endif
	44
	45	#include "ide-timing.h"
	46
1da177e4 LT	47	#define VIA_IDE_ENABLE 0x40
	48	#define VIA_IDE_CONFIG 0x41
	49	#define VIA_FIFO_CONFIG 0x43
	50	#define VIA_MISC_1 0x44
	51	#define VIA_MISC_2 0x45
	52	#define VIA_MISC_3 0x46
	53	#define VIA_DRIVE_TIMING 0x48
	54	#define VIA_8BIT_TIMING 0x4e
	55	#define VIA_ADDRESS_SETUP 0x4c
	56	#define VIA_UDMA_TIMING 0x50
	57
75b1d975 BZ	58	#define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
	59	#define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
	60	#define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
	61	#define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
	62	#define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
	63	#define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
1da177e4 LT	64
	65	/*
	66	* VIA SouthBridge chips.
	67	*/
	68
	69	static struct via_isa_bridge {
	70	char *name;
	71	u16 id;
	72	u8 rev_min;
	73	u8 rev_max;
75b1d975 BZ	74	u8 udma_mask;
75b1d975 BZ	75	u8 flags;
1da177e4	76	} via_isa_bridges[] = {
b311ec4a	77	{ "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
75b1d975 BZ	78	{ "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	79	{ "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	80	{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	81	{ "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	82	{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	83	{ "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	84	{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	85	{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	86	{ "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
	87	{ "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
	88	{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
	89	{ "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
	90	{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
	91	{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	92	{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
	93	{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	94	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	95	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO \| VIA_BAD_PREQ },
	96	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	97	{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	98	{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
	99	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK },
	100	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK \| VIA_BAD_ID },
1da177e4 LT	101	{ NULL }
	102	};
	103
1da177e4	104	static unsigned int via_clock;
75b1d975	105	static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
1da177e4	106
7462cbff DD	107	struct via82cxxx_dev
	108	{
	109	struct via_isa_bridge *via_config;
	110	unsigned int via_80w;
	111	};
	112
1da177e4 LT	113	/**
	114	* via_set_speed - write timing registers
	115	* @dev: PCI device
	116	* @dn: device
	117	* @timing: IDE timing data to use
	118	*
	119	* via_set_speed writes timing values to the chipset registers
	120	*/
	121
7462cbff	122	static void via_set_speed(ide_hwif_t hwif, u8 dn, struct ide_timing timing)
1da177e4	123	{
7462cbff	124	struct pci_dev *dev = hwif->pci_dev;
cd36beec	125	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
1da177e4 LT	126	u8 t;
1da177e4 LT	127
7462cbff	128	if (~vdev->via_config->flags & VIA_BAD_AST) {
1da177e4 LT	129	pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
	130	t = (t & ~(3 << ((3 - dn) << 1))) \| ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
	131	pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	132	}
	133
	134	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
	135	((FIT(timing->act8b, 1, 16) - 1) << 4) \| (FIT(timing->rec8b, 1, 16) - 1));
	136
	137	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
	138	((FIT(timing->active, 1, 16) - 1) << 4) \| (FIT(timing->recover, 1, 16) - 1));
	139
75b1d975 BZ	140	switch (vdev->via_config->udma_mask) {
	141	case ATA_UDMA2: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	142	case ATA_UDMA4: t = timing->udma ? (0xe8 \| (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
	143	case ATA_UDMA5: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	144	case ATA_UDMA6: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	145	default: return;
1da177e4 LT	146	}
	147
	148	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
	149	}
	150
	151	/**
	152	* via_set_drive - configure transfer mode
	153	* @drive: Drive to set up
	154	* @speed: desired speed
	155	*
88b2b32b BZ	156	* via_set_drive() computes timing values configures the chipset to
88b2b32b BZ	157	* a desired transfer mode. It also can be called by upper layers.
1da177e4 LT	158	*/
1da177e4 LT	159
88b2b32b	160	static void via_set_drive(ide_drive_t *drive, const u8 speed)
1da177e4 LT	161	{
1da177e4 LT	162	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
cd36beec	163	struct via82cxxx_dev *vdev = pci_get_drvdata(drive->hwif->pci_dev);
1da177e4 LT	164	struct ide_timing t, p;
	165	unsigned int T, UT;
	166
1da177e4 LT	167	T = 1000000000 / via_clock;
1da177e4 LT	168
75b1d975 BZ	169	switch (vdev->via_config->udma_mask) {
	170	case ATA_UDMA2: UT = T; break;
	171	case ATA_UDMA4: UT = T/2; break;
	172	case ATA_UDMA5: UT = T/3; break;
	173	case ATA_UDMA6: UT = T/4; break;
	174	default: UT = T;
1da177e4 LT	175	}
	176
	177	ide_timing_compute(drive, speed, &t, T, UT);
	178
	179	if (peer->present) {
	180	ide_timing_compute(peer, peer->current_speed, &p, T, UT);
	181	ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	182	}
	183
7462cbff	184	via_set_speed(HWIF(drive), drive->dn, &t);
1da177e4 LT	185	}
	186
	187	/**
88b2b32b	188	* via_set_pio_mode - set host controller for PIO mode
26bcb879 BZ	189	* @drive: drive
26bcb879 BZ	190	* @pio: PIO mode number
1da177e4 LT	191	*
	192	* A callback from the upper layers for PIO-only tuning.
	193	*/
	194
26bcb879	195	static void via_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	196	{
26bcb879	197	via_set_drive(drive, XFER_PIO_0 + pio);
1da177e4 LT	198	}
1da177e4 LT	199
7462cbff DD	200	static struct via_isa_bridge via_config_find(struct pci_dev *isa)
	201	{
	202	struct via_isa_bridge *via_config;
7462cbff DD	203
7462cbff DD	204	for (via_config = via_isa_bridges; via_config->id; via_config++)
652aa162	205	if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
7462cbff DD	206	!!(via_config->flags & VIA_BAD_ID),
	207	via_config->id, NULL))) {
	208
44c10138 AK	209	if ((*isa)->revision >= via_config->rev_min &&
44c10138 AK	210	(*isa)->revision <= via_config->rev_max)
7462cbff	211	break;
652aa162	212	pci_dev_put(*isa);
7462cbff DD	213	}
	214
	215	return via_config;
1da177e4 LT	216	}
1da177e4 LT	217
cd36beec BZ	218	/*
	219	* Check and handle 80-wire cable presence
	220	*/
	221	static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
	222	{
	223	int i;
	224
75b1d975 BZ	225	switch (vdev->via_config->udma_mask) {
75b1d975 BZ	226	case ATA_UDMA4:
cd36beec BZ	227	for (i = 24; i >= 0; i -= 8)
	228	if (((u >> (i & 16)) & 8) &&
	229	((u >> i) & 0x20) &&
	230	(((u >> i) & 7) < 2)) {
	231	/*
	232	* 2x PCI clock and
	233	* UDMA w/ < 3T/cycle
	234	*/
	235	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	236	}
	237	break;
	238
75b1d975	239	case ATA_UDMA5:
cd36beec BZ	240	for (i = 24; i >= 0; i -= 8)
	241	if (((u >> i) & 0x10) \|\|
	242	(((u >> i) & 0x20) &&
	243	(((u >> i) & 7) < 4))) {
	244	/* BIOS 80-wire bit or
	245	* UDMA w/ < 60ns/cycle
	246	*/
	247	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	248	}
	249	break;
	250
75b1d975	251	case ATA_UDMA6:
cd36beec BZ	252	for (i = 24; i >= 0; i -= 8)
	253	if (((u >> i) & 0x10) \|\|
	254	(((u >> i) & 0x20) &&
	255	(((u >> i) & 7) < 6))) {
	256	/* BIOS 80-wire bit or
	257	* UDMA w/ < 60ns/cycle
	258	*/
	259	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	260	}
	261	break;
	262	}
	263	}
	264
1da177e4 LT	265	/**
	266	* init_chipset_via82cxxx - initialization handler
	267	* @dev: PCI device
	268	* @name: Name of interface
	269	*
	270	* The initialization callback. Here we determine the IDE chip type
	271	* and initialize its drive independent registers.
	272	*/
	273
f3718d3e	274	static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev dev, const char name)
1da177e4 LT	275	{
1da177e4 LT	276	struct pci_dev *isa = NULL;
cd36beec	277	struct via82cxxx_dev *vdev;
7462cbff	278	struct via_isa_bridge *via_config;
1da177e4	279	u8 t, v;
cd36beec BZ	280	u32 u;
	281
	282	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
	283	if (!vdev) {
	284	printk(KERN_ERR "VP_IDE: out of memory :(\n");
	285	return -ENOMEM;
	286	}
	287	pci_set_drvdata(dev, vdev);
1da177e4 LT	288
	289	/*
	290	* Find the ISA bridge to see how good the IDE is.
	291	*/
cd36beec	292	vdev->via_config = via_config = via_config_find(&isa);
23a1b2a7 AC	293
	294	/* We checked this earlier so if it fails here deeep badness
	295	is involved */
	296
	297	BUG_ON(!via_config->id);
1da177e4 LT	298
1da177e4 LT	299	/*
cd36beec	300	* Detect cable and configure Clk66
1da177e4	301	*/
cd36beec BZ	302	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
	303
	304	via_cable_detect(vdev, u);
1da177e4	305
75b1d975	306	if (via_config->udma_mask == ATA_UDMA4) {
7462cbff	307	/* Enable Clk66 */
7462cbff DD	308	pci_write_config_dword(dev, VIA_UDMA_TIMING, u\|0x80008);
7462cbff DD	309	} else if (via_config->flags & VIA_BAD_CLK66) {
1da177e4	310	/* Would cause trouble on 596a and 686 */
1da177e4 LT	311	pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	312	}
	313
	314	/*
	315	* Check whether interfaces are enabled.
	316	*/
	317
	318	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
	319
	320	/*
	321	* Set up FIFO sizes and thresholds.
	322	*/
	323
	324	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
	325
	326	/* Disable PREQ# till DDACK# */
	327	if (via_config->flags & VIA_BAD_PREQ) {
	328	/* Would crash on 586b rev 41 */
	329	t &= 0x7f;
	330	}
	331
	332	/* Fix FIFO split between channels */
	333	if (via_config->flags & VIA_SET_FIFO) {
	334	t &= (t & 0x9f);
	335	switch (v & 3) {
	336	case 2: t \|= 0x00; break; /* 16 on primary */
	337	case 1: t \|= 0x60; break; /* 16 on secondary */
	338	case 3: t \|= 0x20; break; /* 8 pri 8 sec */
	339	}
	340	}
	341
	342	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
	343
	344	/*
	345	* Determine system bus clock.
	346	*/
	347
	348	via_clock = system_bus_clock() * 1000;
	349
	350	switch (via_clock) {
	351	case 33000: via_clock = 33333; break;
	352	case 37000: via_clock = 37500; break;
	353	case 41000: via_clock = 41666; break;
	354	}
	355
	356	if (via_clock < 20000 \|\| via_clock > 50000) {
	357	printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
	358	"impossible (%d), using 33 MHz instead.\n", via_clock);
	359	printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
	360	"to assume 80-wire cable.\n");
	361	via_clock = 33333;
	362	}
	363
	364	/*
	365	* Print the boot message.
	366	*/
	367
75b1d975	368	printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s "
1da177e4	369	"controller on pci%s\n",
44c10138	370	via_config->name, isa->revision,
75b1d975 BZ	371	via_config->udma_mask ? "U" : "MW",
	372	via_dma[via_config->udma_mask ?
	373	(fls(via_config->udma_mask) - 1) : 0],
1da177e4 LT	374	pci_name(dev));
1da177e4 LT	375
652aa162	376	pci_dev_put(isa);
1da177e4 LT	377	return 0;
	378	}
	379
bdab00b7 BZ	380	/*
	381	* Cable special cases
	382	*/
	383
1855256c	384	static const struct dmi_system_id cable_dmi_table[] = {
bdab00b7 BZ	385	{
	386	.ident = "Acer Ferrari 3400",
	387	.matches = {
	388	DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
	389	DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
	390	},
	391	},
	392	{ }
	393	};
	394
58e47bb1	395	static int via_cable_override(struct pci_dev *pdev)
bdab00b7 BZ	396	{
	397	/* Systems by DMI */
	398	if (dmi_check_system(cable_dmi_table))
	399	return 1;
58e47bb1 BZ	400
	401	/* Arima W730-K8/Targa Visionary 811/... */
	402	if (pdev->subsystem_vendor == 0x161F &&
	403	pdev->subsystem_device == 0x2032)
	404	return 1;
	405
bdab00b7 BZ	406	return 0;
	407	}
	408
	409	static u8 __devinit via82cxxx_cable_detect(ide_hwif_t *hwif)
	410	{
58e47bb1 BZ	411	struct pci_dev *pdev = hwif->pci_dev;
58e47bb1 BZ	412	struct via82cxxx_dev *vdev = pci_get_drvdata(pdev);
bdab00b7	413
58e47bb1	414	if (via_cable_override(pdev))
bdab00b7 BZ	415	return ATA_CBL_PATA40_SHORT;
	416
	417	if ((vdev->via_80w >> hwif->channel) & 1)
	418	return ATA_CBL_PATA80;
	419	else
	420	return ATA_CBL_PATA40;
	421	}
	422
f3718d3e	423	static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
1da177e4	424	{
26bcb879	425	hwif->set_pio_mode = &via_set_pio_mode;
88b2b32b	426	hwif->set_dma_mode = &via_set_drive;
1da177e4	427
1da177e4 LT	428	if (!hwif->dma_base)
	429	return;
	430
bdab00b7 BZ	431	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
bdab00b7 BZ	432	hwif->cbl = via82cxxx_cable_detect(hwif);
1da177e4 LT	433	}
1da177e4 LT	434
85620436	435	static const struct ide_port_info via82cxxx_chipset __devinitdata = {
6157332e BZ	436	.name = "VP_IDE",
	437	.init_chipset = init_chipset_via82cxxx,
	438	.init_hwif = init_hwif_via82cxxx,
	439	.enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
	440	.host_flags = IDE_HFLAG_PIO_NO_BLACKLIST \|
	441	IDE_HFLAG_PIO_NO_DOWNGRADE \|
4db90a14	442	IDE_HFLAG_ABUSE_SET_DMA_MODE \|
6157332e BZ	443	IDE_HFLAG_POST_SET_MODE \|
	444	IDE_HFLAG_IO_32BIT \|
	445	IDE_HFLAG_BOOTABLE,
	446	.pio_mask = ATA_PIO5,
	447	.swdma_mask = ATA_SWDMA2,
	448	.mwdma_mask = ATA_MWDMA2,
1da177e4 LT	449	};
	450
	451	static int __devinit via_init_one(struct pci_dev dev, const struct pci_device_id id)
	452	{
23a1b2a7 AC	453	struct pci_dev *isa = NULL;
23a1b2a7 AC	454	struct via_isa_bridge *via_config;
6157332e	455	u8 idx = id->driver_data;
039788e1	456	struct ide_port_info d;
6157332e BZ	457
6157332e BZ	458	d = via82cxxx_chipset;
8acf28c0	459
23a1b2a7 AC	460	/*
	461	* Find the ISA bridge and check we know what it is.
	462	*/
	463	via_config = via_config_find(&isa);
	464	pci_dev_put(isa);
	465	if (!via_config->id) {
	466	printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
	467	return -ENODEV;
	468	}
8acf28c0	469
6157332e BZ	470	if (idx == 0)
6157332e BZ	471	d.host_flags \|= IDE_HFLAG_NO_AUTODMA;
caea7602	472	else
6157332e BZ	473	d.enablebits[1].reg = d.enablebits[0].reg = 0;
	474
	475	if ((via_config->flags & VIA_NO_UNMASK) == 0)
	476	d.host_flags \|= IDE_HFLAG_UNMASK_IRQS;
caea7602	477
8acf28c0 BZ	478	#ifdef CONFIG_PPC_CHRP
8acf28c0 BZ	479	if (machine_is(chrp) && _chrp_type == _CHRP_Pegasos)
6157332e	480	d.host_flags \|= IDE_HFLAG_FORCE_LEGACY_IRQS;
8acf28c0 BZ	481	#endif
8acf28c0 BZ	482
6157332e	483	d.udma_mask = via_config->udma_mask;
8acf28c0	484
6157332e	485	return ide_setup_pci_device(dev, &d);
1da177e4 LT	486	}
1da177e4 LT	487
9cbcc5e3 BZ	488	static const struct pci_device_id via_pci_tbl[] = {
	489	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 },
	490	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 },
	491	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 },
	492	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
1da177e4 LT	493	{ 0, },
	494	};
	495	MODULE_DEVICE_TABLE(pci, via_pci_tbl);
	496
	497	static struct pci_driver driver = {
	498	.name = "VIA_IDE",
	499	.id_table = via_pci_tbl,
	500	.probe = via_init_one,
	501	};
	502
82ab1eec	503	static int __init via_ide_init(void)
1da177e4 LT	504	{
	505	return ide_pci_register_driver(&driver);
	506	}
	507
	508	module_init(via_ide_init);
	509
	510	MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
	511	MODULE_DESCRIPTION("PCI driver module for VIA IDE");
	512	MODULE_LICENSE("GPL");