[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / via82cxxx.c

/*
 *
 * Version 3.40
 *
 * VIA IDE driver for Linux. Supported southbridges:
 *
 *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
 *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
 *   vt8235, vt8237, vt8237a
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
 *
 * Based on the work of:
 *	Michel Aubry
 *	Jeff Garzik
 *	Andre Hedrick
 *
 * Documentation:
 *	Obsolete device documentation publically available from via.com.tw
 *	Current device documentation available under NDA only
 */

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <asm/io.h>

#ifdef CONFIG_PPC_CHRP
#include <asm/processor.h>
#endif

#include "ide-timing.h"

#define VIA_IDE_ENABLE		0x40
#define VIA_IDE_CONFIG		0x41
#define VIA_FIFO_CONFIG		0x43
#define VIA_MISC_1		0x44
#define VIA_MISC_2		0x45
#define VIA_MISC_3		0x46
#define VIA_DRIVE_TIMING	0x48
#define VIA_8BIT_TIMING		0x4e
#define VIA_ADDRESS_SETUP	0x4c
#define VIA_UDMA_TIMING		0x50

#define VIA_BAD_PREQ		0x01 /* Crashes if PREQ# till DDACK# set */
#define VIA_BAD_CLK66		0x02 /* 66 MHz clock doesn't work correctly */
#define VIA_SET_FIFO		0x04 /* Needs to have FIFO split set */
#define VIA_NO_UNMASK		0x08 /* Doesn't work with IRQ unmasking on */
#define VIA_BAD_ID		0x10 /* Has wrong vendor ID (0x1107) */
#define VIA_BAD_AST		0x20 /* Don't touch Address Setup Timing */

/*
 * VIA SouthBridge chips.
 */

static struct via_isa_bridge {
	char *name;
	u16 id;
	u8 rev_min;
	u8 rev_max;
	u8 udma_mask;
	u8 flags;
} via_isa_bridges[] = {
	{ "cx700",	PCI_DEVICE_ID_VIA_CX700,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237s",	PCI_DEVICE_ID_VIA_8237S,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8251",	PCI_DEVICE_ID_VIA_8251,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8237a",	PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233a",	PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	{ "vt8233c",	PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, ATA_UDMA5, },
	{ "vt8233",	PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, ATA_UDMA5, },
	{ "vt8231",	PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, ATA_UDMA5, },
	{ "vt82c686b",	PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, ATA_UDMA5, },
	{ "vt82c686a",	PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c686",	PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c596b",	PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, ATA_UDMA4, },
	{ "vt82c596a",	PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586a",	PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	{ "vt82c586",	PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f,      0x00, VIA_SET_FIFO },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f,      0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
	{ NULL }
};

static unsigned int via_clock;
static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };

struct via82cxxx_dev
{
	struct via_isa_bridge *via_config;
	unsigned int via_80w;
};

/**
 *	via_set_speed			-	write timing registers
 *	@dev: PCI device
 *	@dn: device
 *	@timing: IDE timing data to use
 *
 *	via_set_speed writes timing values to the chipset registers
 */

static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
{
	struct pci_dev *dev = hwif->pci_dev;
	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
	u8 t;

	if (~vdev->via_config->flags & VIA_BAD_AST) {
		pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
		t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
		pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	}

	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
		((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
		((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	case ATA_UDMA4: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
	case ATA_UDMA5: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	case ATA_UDMA6: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	default: return;
	}

	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
}

/**
 *	via_set_drive		-	configure transfer mode
 *	@drive: Drive to set up
 *	@speed: desired speed
 *
 *	via_set_drive() computes timing values configures the drive and
 *	the chipset to a desired transfer mode. It also can be called
 *	by upper layers.
 */

static int via_set_drive(ide_drive_t *drive, u8 speed)
{
	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
	struct via82cxxx_dev *vdev = pci_get_drvdata(drive->hwif->pci_dev);
	struct ide_timing t, p;
	unsigned int T, UT;

	if (speed != XFER_PIO_SLOW)
		ide_config_drive_speed(drive, speed);

	T = 1000000000 / via_clock;

	switch (vdev->via_config->udma_mask) {
	case ATA_UDMA2: UT = T;   break;
	case ATA_UDMA4: UT = T/2; break;
	case ATA_UDMA5: UT = T/3; break;
	case ATA_UDMA6: UT = T/4; break;
	default:	UT = T;
	}

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer->present) {
		ide_timing_compute(peer, peer->current_speed, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	via_set_speed(HWIF(drive), drive->dn, &t);

	if (!drive->init_speed)
		drive->init_speed = speed;
	drive->current_speed = speed;

	return 0;
}

/**
 *	via82cxxx_tune_drive	-	PIO setup
 *	@drive: drive to set up
 *	@pio: mode to use (255 for 'best possible')
 *
 *	A callback from the upper layers for PIO-only tuning.
 */

static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
{
	if (pio == 255) {
		via_set_drive(drive, ide_find_best_pio_mode(drive));
		return;
	}

	via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
}

/**
 *	via82cxxx_ide_dma_check		-	set up for DMA if possible
 *	@drive: IDE drive to set up
 *
 *	Set up the drive for the highest supported speed considering the
 *	driver, controller and cable
 */
 
static int via82cxxx_ide_dma_check (ide_drive_t *drive)
{
	u8 speed = ide_max_dma_mode(drive);

	if (speed == 0)
		speed = ide_find_best_pio_mode(drive);

	via_set_drive(drive, speed);

	if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
		return 0;

	return -1;
}

static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
{
	struct via_isa_bridge *via_config;
	u8 t;

	for (via_config = via_isa_bridges; via_config->id; via_config++)
		if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
			!!(via_config->flags & VIA_BAD_ID),
			via_config->id, NULL))) {

			pci_read_config_byte(*isa, PCI_REVISION_ID, &t);
			if (t >= via_config->rev_min &&
			    t <= via_config->rev_max)
				break;
			pci_dev_put(*isa);
		}

	return via_config;
}

/*
 * Check and handle 80-wire cable presence
 */
static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
{
	int i;

	switch (vdev->via_config->udma_mask) {
		case ATA_UDMA4:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> (i & 16)) & 8) &&
				    ((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 2)) {
					/*
					 * 2x PCI clock and
					 * UDMA w/ < 3T/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA5:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 4))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;

		case ATA_UDMA6:
			for (i = 24; i >= 0; i -= 8)
				if (((u >> i) & 0x10) ||
				    (((u >> i) & 0x20) &&
				     (((u >> i) & 7) < 6))) {
					/* BIOS 80-wire bit or
					 * UDMA w/ < 60ns/cycle
					 */
					vdev->via_80w |= (1 << (1 - (i >> 4)));
				}
			break;
	}
}

/**
 *	init_chipset_via82cxxx	-	initialization handler
 *	@dev: PCI device
 *	@name: Name of interface
 *
 *	The initialization callback. Here we determine the IDE chip type
 *	and initialize its drive independent registers.
 */

static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
{
	struct pci_dev *isa = NULL;
	struct via82cxxx_dev *vdev;
	struct via_isa_bridge *via_config;
	u8 t, v;
	u32 u;

	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
	if (!vdev) {
		printk(KERN_ERR "VP_IDE: out of memory :(\n");
		return -ENOMEM;
	}
	pci_set_drvdata(dev, vdev);

	/*
	 * Find the ISA bridge to see how good the IDE is.
	 */
	vdev->via_config = via_config = via_config_find(&isa);

	/* We checked this earlier so if it fails here deeep badness
	   is involved */

	BUG_ON(!via_config->id);

	/*
	 * Detect cable and configure Clk66
	 */
	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);

	via_cable_detect(vdev, u);

	if (via_config->udma_mask == ATA_UDMA4) {
		/* Enable Clk66 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
	} else if (via_config->flags & VIA_BAD_CLK66) {
		/* Would cause trouble on 596a and 686 */
		pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	}

	/*
	 * Check whether interfaces are enabled.
	 */

	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);

	/*
	 * Set up FIFO sizes and thresholds.
	 */

	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);

	/* Disable PREQ# till DDACK# */
	if (via_config->flags & VIA_BAD_PREQ) {
		/* Would crash on 586b rev 41 */
		t &= 0x7f;
	}

	/* Fix FIFO split between channels */
	if (via_config->flags & VIA_SET_FIFO) {
		t &= (t & 0x9f);
		switch (v & 3) {
			case 2: t |= 0x00; break;	/* 16 on primary */
			case 1: t |= 0x60; break;	/* 16 on secondary */
			case 3: t |= 0x20; break;	/* 8 pri 8 sec */
		}
	}

	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);

	/*
	 * Determine system bus clock.
	 */

	via_clock = system_bus_clock() * 1000;

	switch (via_clock) {
		case 33000: via_clock = 33333; break;
		case 37000: via_clock = 37500; break;
		case 41000: via_clock = 41666; break;
	}

	if (via_clock < 20000 || via_clock > 50000) {
		printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
			"impossible (%d), using 33 MHz instead.\n", via_clock);
		printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
			"to assume 80-wire cable.\n");
		via_clock = 33333;
	}

	/*
	 * Print the boot message.
	 */

	pci_read_config_byte(isa, PCI_REVISION_ID, &t);
	printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s "
		"controller on pci%s\n",
		via_config->name, t,
		via_config->udma_mask ? "U" : "MW",
		via_dma[via_config->udma_mask ?
			(fls(via_config->udma_mask) - 1) : 0],
		pci_name(dev));

	pci_dev_put(isa);
	return 0;
}

static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
{
	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
	int i;

	hwif->autodma = 0;

	hwif->tuneproc = &via82cxxx_tune_drive;
	hwif->speedproc = &via_set_drive;


#ifdef CONFIG_PPC_CHRP
	if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) {
		hwif->irq = hwif->channel ? 15 : 14;
	}
#endif

	for (i = 0; i < 2; i++) {
		hwif->drives[i].io_32bit = 1;
		hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
		hwif->drives[i].autotune = 1;
		hwif->drives[i].dn = hwif->channel * 2 + i;
	}

	if (!hwif->dma_base)
		return;

	hwif->atapi_dma = 1;

	hwif->ultra_mask = vdev->via_config->udma_mask;
	hwif->mwdma_mask = 0x07;
	hwif->swdma_mask = 0x07;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
		if ((vdev->via_80w >> hwif->channel) & 1)
			hwif->cbl = ATA_CBL_PATA80;
		else
			hwif->cbl = ATA_CBL_PATA40;
	}

	hwif->ide_dma_check = &via82cxxx_ide_dma_check;
	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}

static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "VP_IDE",
		.init_chipset	= init_chipset_via82cxxx,
		.init_hwif	= init_hwif_via82cxxx,
		.channels	= 2,
		.autodma	= NOAUTODMA,
		.enablebits	= {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
		.bootable	= ON_BOARD
	},{	/* 1 */
		.name		= "VP_IDE",
		.init_chipset	= init_chipset_via82cxxx,
		.init_hwif	= init_hwif_via82cxxx,
		.channels	= 2,
		.autodma	= AUTODMA,
		.enablebits	= {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
		.bootable	= ON_BOARD,
	}
};

static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct pci_dev *isa = NULL;
	struct via_isa_bridge *via_config;
	/*
	 * Find the ISA bridge and check we know what it is.
	 */
	via_config = via_config_find(&isa);
	pci_dev_put(isa);
	if (!via_config->id) {
		printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
		return -ENODEV;
	}
	return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]);
}

static struct pci_device_id via_pci_tbl[] = {
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410,     PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_SATA_EIDE,     PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, via_pci_tbl);

static struct pci_driver driver = {
	.name 		= "VIA_IDE",
	.id_table 	= via_pci_tbl,
	.probe 		= via_init_one,
};

static int __init via_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(via_ide_init);

MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for VIA IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	*
75b1d975	3	* Version 3.40
1da177e4 LT	4	*
	5	* VIA IDE driver for Linux. Supported southbridges:
	6	*
	7	* vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
	8	* vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
a7dec1e0	9	* vt8235, vt8237, vt8237a
1da177e4 LT	10	*
1da177e4 LT	11	* Copyright (c) 2000-2002 Vojtech Pavlik
75b1d975	12	* Copyright (c) 2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	13	*
	14	* Based on the work of:
	15	* Michel Aubry
	16	* Jeff Garzik
	17	* Andre Hedrick
	18	*
	19	* Documentation:
	20	* Obsolete device documentation publically available from via.com.tw
	21	* Current device documentation available under NDA only
	22	*/
	23
	24	/*
	25	* This program is free software; you can redistribute it and/or modify it
	26	* under the terms of the GNU General Public License version 2 as published by
	27	* the Free Software Foundation.
	28	*/
	29
1da177e4 LT	30	#include <linux/module.h>
	31	#include <linux/kernel.h>
	32	#include <linux/ioport.h>
	33	#include <linux/blkdev.h>
	34	#include <linux/pci.h>
	35	#include <linux/init.h>
	36	#include <linux/ide.h>
	37	#include <asm/io.h>
	38
74a9d5f1	39	#ifdef CONFIG_PPC_CHRP
1da177e4 LT	40	#include <asm/processor.h>
	41	#endif
	42
	43	#include "ide-timing.h"
	44
1da177e4 LT	45	#define VIA_IDE_ENABLE 0x40
	46	#define VIA_IDE_CONFIG 0x41
	47	#define VIA_FIFO_CONFIG 0x43
	48	#define VIA_MISC_1 0x44
	49	#define VIA_MISC_2 0x45
	50	#define VIA_MISC_3 0x46
	51	#define VIA_DRIVE_TIMING 0x48
	52	#define VIA_8BIT_TIMING 0x4e
	53	#define VIA_ADDRESS_SETUP 0x4c
	54	#define VIA_UDMA_TIMING 0x50
	55
75b1d975 BZ	56	#define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
	57	#define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
	58	#define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
	59	#define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
	60	#define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
	61	#define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
1da177e4 LT	62
	63	/*
	64	* VIA SouthBridge chips.
	65	*/
	66
	67	static struct via_isa_bridge {
	68	char *name;
	69	u16 id;
	70	u8 rev_min;
	71	u8 rev_max;
75b1d975 BZ	72	u8 udma_mask;
75b1d975 BZ	73	u8 flags;
1da177e4	74	} via_isa_bridges[] = {
75b1d975 BZ	75	{ "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	76	{ "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	77	{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	78	{ "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	79	{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	80	{ "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	81	{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	82	{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
	83	{ "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
	84	{ "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
	85	{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
	86	{ "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
	87	{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
	88	{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	89	{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
	90	{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
	91	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
	92	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO \| VIA_BAD_PREQ },
	93	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
	94	{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
	95	{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
	96	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK },
	97	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO \| VIA_NO_UNMASK \| VIA_BAD_ID },
1da177e4 LT	98	{ NULL }
	99	};
	100
1da177e4	101	static unsigned int via_clock;
75b1d975	102	static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
1da177e4	103
7462cbff DD	104	struct via82cxxx_dev
	105	{
	106	struct via_isa_bridge *via_config;
	107	unsigned int via_80w;
	108	};
	109
1da177e4 LT	110	/**
	111	* via_set_speed - write timing registers
	112	* @dev: PCI device
	113	* @dn: device
	114	* @timing: IDE timing data to use
	115	*
	116	* via_set_speed writes timing values to the chipset registers
	117	*/
	118
7462cbff	119	static void via_set_speed(ide_hwif_t hwif, u8 dn, struct ide_timing timing)
1da177e4	120	{
7462cbff	121	struct pci_dev *dev = hwif->pci_dev;
cd36beec	122	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
1da177e4 LT	123	u8 t;
1da177e4 LT	124
7462cbff	125	if (~vdev->via_config->flags & VIA_BAD_AST) {
1da177e4 LT	126	pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
	127	t = (t & ~(3 << ((3 - dn) << 1))) \| ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
	128	pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
	129	}
	130
	131	pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
	132	((FIT(timing->act8b, 1, 16) - 1) << 4) \| (FIT(timing->rec8b, 1, 16) - 1));
	133
	134	pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
	135	((FIT(timing->active, 1, 16) - 1) << 4) \| (FIT(timing->recover, 1, 16) - 1));
	136
75b1d975 BZ	137	switch (vdev->via_config->udma_mask) {
	138	case ATA_UDMA2: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	139	case ATA_UDMA4: t = timing->udma ? (0xe8 \| (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
	140	case ATA_UDMA5: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	141	case ATA_UDMA6: t = timing->udma ? (0xe0 \| (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
	142	default: return;
1da177e4 LT	143	}
	144
	145	pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
	146	}
	147
	148	/**
	149	* via_set_drive - configure transfer mode
	150	* @drive: Drive to set up
	151	* @speed: desired speed
	152	*
	153	* via_set_drive() computes timing values configures the drive and
	154	* the chipset to a desired transfer mode. It also can be called
	155	* by upper layers.
	156	*/
	157
	158	static int via_set_drive(ide_drive_t *drive, u8 speed)
	159	{
	160	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
cd36beec	161	struct via82cxxx_dev *vdev = pci_get_drvdata(drive->hwif->pci_dev);
1da177e4 LT	162	struct ide_timing t, p;
	163	unsigned int T, UT;
	164
	165	if (speed != XFER_PIO_SLOW)
	166	ide_config_drive_speed(drive, speed);
	167
	168	T = 1000000000 / via_clock;
	169
75b1d975 BZ	170	switch (vdev->via_config->udma_mask) {
	171	case ATA_UDMA2: UT = T; break;
	172	case ATA_UDMA4: UT = T/2; break;
	173	case ATA_UDMA5: UT = T/3; break;
	174	case ATA_UDMA6: UT = T/4; break;
	175	default: UT = T;
1da177e4 LT	176	}
	177
	178	ide_timing_compute(drive, speed, &t, T, UT);
	179
	180	if (peer->present) {
	181	ide_timing_compute(peer, peer->current_speed, &p, T, UT);
	182	ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	183	}
	184
7462cbff	185	via_set_speed(HWIF(drive), drive->dn, &t);
1da177e4 LT	186
	187	if (!drive->init_speed)
	188	drive->init_speed = speed;
	189	drive->current_speed = speed;
	190
	191	return 0;
	192	}
	193
	194	/**
	195	* via82cxxx_tune_drive - PIO setup
	196	* @drive: drive to set up
	197	* @pio: mode to use (255 for 'best possible')
	198	*
	199	* A callback from the upper layers for PIO-only tuning.
	200	*/
	201
	202	static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
	203	{
	204	if (pio == 255) {
75b1d975	205	via_set_drive(drive, ide_find_best_pio_mode(drive));
1da177e4 LT	206	return;
	207	}
	208
	209	via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
	210	}
	211
	212	/**
	213	* via82cxxx_ide_dma_check - set up for DMA if possible
	214	* @drive: IDE drive to set up
	215	*
	216	* Set up the drive for the highest supported speed considering the
	217	* driver, controller and cable
	218	*/
	219
	220	static int via82cxxx_ide_dma_check (ide_drive_t *drive)
	221	{
75b1d975	222	u8 speed = ide_max_dma_mode(drive);
1da177e4	223
75b1d975 BZ	224	if (speed == 0)
75b1d975 BZ	225	speed = ide_find_best_pio_mode(drive);
1da177e4 LT	226
	227	via_set_drive(drive, speed);
	228
	229	if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
3608b5d7 BZ	230	return 0;
	231
	232	return -1;
7462cbff DD	233	}
	234
	235	static struct via_isa_bridge via_config_find(struct pci_dev *isa)
	236	{
	237	struct via_isa_bridge *via_config;
	238	u8 t;
	239
	240	for (via_config = via_isa_bridges; via_config->id; via_config++)
652aa162	241	if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
7462cbff DD	242	!!(via_config->flags & VIA_BAD_ID),
	243	via_config->id, NULL))) {
	244
	245	pci_read_config_byte(*isa, PCI_REVISION_ID, &t);
	246	if (t >= via_config->rev_min &&
	247	t <= via_config->rev_max)
	248	break;
652aa162	249	pci_dev_put(*isa);
7462cbff DD	250	}
	251
	252	return via_config;
1da177e4 LT	253	}
1da177e4 LT	254
cd36beec BZ	255	/*
	256	* Check and handle 80-wire cable presence
	257	*/
	258	static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
	259	{
	260	int i;
	261
75b1d975 BZ	262	switch (vdev->via_config->udma_mask) {
75b1d975 BZ	263	case ATA_UDMA4:
cd36beec BZ	264	for (i = 24; i >= 0; i -= 8)
	265	if (((u >> (i & 16)) & 8) &&
	266	((u >> i) & 0x20) &&
	267	(((u >> i) & 7) < 2)) {
	268	/*
	269	* 2x PCI clock and
	270	* UDMA w/ < 3T/cycle
	271	*/
	272	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	273	}
	274	break;
	275
75b1d975	276	case ATA_UDMA5:
cd36beec BZ	277	for (i = 24; i >= 0; i -= 8)
	278	if (((u >> i) & 0x10) \|\|
	279	(((u >> i) & 0x20) &&
	280	(((u >> i) & 7) < 4))) {
	281	/* BIOS 80-wire bit or
	282	* UDMA w/ < 60ns/cycle
	283	*/
	284	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	285	}
	286	break;
	287
75b1d975	288	case ATA_UDMA6:
cd36beec BZ	289	for (i = 24; i >= 0; i -= 8)
	290	if (((u >> i) & 0x10) \|\|
	291	(((u >> i) & 0x20) &&
	292	(((u >> i) & 7) < 6))) {
	293	/* BIOS 80-wire bit or
	294	* UDMA w/ < 60ns/cycle
	295	*/
	296	vdev->via_80w \|= (1 << (1 - (i >> 4)));
	297	}
	298	break;
	299	}
	300	}
	301
1da177e4 LT	302	/**
	303	* init_chipset_via82cxxx - initialization handler
	304	* @dev: PCI device
	305	* @name: Name of interface
	306	*
	307	* The initialization callback. Here we determine the IDE chip type
	308	* and initialize its drive independent registers.
	309	*/
	310
f3718d3e	311	static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev dev, const char name)
1da177e4 LT	312	{
1da177e4 LT	313	struct pci_dev *isa = NULL;
cd36beec	314	struct via82cxxx_dev *vdev;
7462cbff	315	struct via_isa_bridge *via_config;
1da177e4	316	u8 t, v;
cd36beec BZ	317	u32 u;
	318
	319	vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
	320	if (!vdev) {
	321	printk(KERN_ERR "VP_IDE: out of memory :(\n");
	322	return -ENOMEM;
	323	}
	324	pci_set_drvdata(dev, vdev);
1da177e4 LT	325
	326	/*
	327	* Find the ISA bridge to see how good the IDE is.
	328	*/
cd36beec	329	vdev->via_config = via_config = via_config_find(&isa);
23a1b2a7 AC	330
	331	/* We checked this earlier so if it fails here deeep badness
	332	is involved */
	333
	334	BUG_ON(!via_config->id);
1da177e4 LT	335
1da177e4 LT	336	/*
cd36beec	337	* Detect cable and configure Clk66
1da177e4	338	*/
cd36beec BZ	339	pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
	340
	341	via_cable_detect(vdev, u);
1da177e4	342
75b1d975	343	if (via_config->udma_mask == ATA_UDMA4) {
7462cbff	344	/* Enable Clk66 */
7462cbff DD	345	pci_write_config_dword(dev, VIA_UDMA_TIMING, u\|0x80008);
7462cbff DD	346	} else if (via_config->flags & VIA_BAD_CLK66) {
1da177e4	347	/* Would cause trouble on 596a and 686 */
1da177e4 LT	348	pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
	349	}
	350
	351	/*
	352	* Check whether interfaces are enabled.
	353	*/
	354
	355	pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
	356
	357	/*
	358	* Set up FIFO sizes and thresholds.
	359	*/
	360
	361	pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
	362
	363	/* Disable PREQ# till DDACK# */
	364	if (via_config->flags & VIA_BAD_PREQ) {
	365	/* Would crash on 586b rev 41 */
	366	t &= 0x7f;
	367	}
	368
	369	/* Fix FIFO split between channels */
	370	if (via_config->flags & VIA_SET_FIFO) {
	371	t &= (t & 0x9f);
	372	switch (v & 3) {
	373	case 2: t \|= 0x00; break; /* 16 on primary */
	374	case 1: t \|= 0x60; break; /* 16 on secondary */
	375	case 3: t \|= 0x20; break; /* 8 pri 8 sec */
	376	}
	377	}
	378
	379	pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
	380
	381	/*
	382	* Determine system bus clock.
	383	*/
	384
	385	via_clock = system_bus_clock() * 1000;
	386
	387	switch (via_clock) {
	388	case 33000: via_clock = 33333; break;
	389	case 37000: via_clock = 37500; break;
	390	case 41000: via_clock = 41666; break;
	391	}
	392
	393	if (via_clock < 20000 \|\| via_clock > 50000) {
	394	printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
	395	"impossible (%d), using 33 MHz instead.\n", via_clock);
	396	printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
	397	"to assume 80-wire cable.\n");
	398	via_clock = 33333;
	399	}
	400
	401	/*
	402	* Print the boot message.
	403	*/
	404
	405	pci_read_config_byte(isa, PCI_REVISION_ID, &t);
75b1d975	406	printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s "
1da177e4 LT	407	"controller on pci%s\n",
1da177e4 LT	408	via_config->name, t,
75b1d975 BZ	409	via_config->udma_mask ? "U" : "MW",
	410	via_dma[via_config->udma_mask ?
	411	(fls(via_config->udma_mask) - 1) : 0],
1da177e4 LT	412	pci_name(dev));
1da177e4 LT	413
652aa162	414	pci_dev_put(isa);
1da177e4 LT	415	return 0;
	416	}
	417
f3718d3e	418	static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
1da177e4	419	{
cd36beec	420	struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
1da177e4 LT	421	int i;
	422
	423	hwif->autodma = 0;
	424
	425	hwif->tuneproc = &via82cxxx_tune_drive;
	426	hwif->speedproc = &via_set_drive;
	427
	428
74a9d5f1	429	#ifdef CONFIG_PPC_CHRP
e8222502	430	if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) {
1da177e4 LT	431	hwif->irq = hwif->channel ? 15 : 14;
	432	}
	433	#endif
	434
	435	for (i = 0; i < 2; i++) {
	436	hwif->drives[i].io_32bit = 1;
7462cbff	437	hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
1da177e4 LT	438	hwif->drives[i].autotune = 1;
	439	hwif->drives[i].dn = hwif->channel * 2 + i;
	440	}
	441
	442	if (!hwif->dma_base)
	443	return;
	444
	445	hwif->atapi_dma = 1;
75b1d975 BZ	446
75b1d975 BZ	447	hwif->ultra_mask = vdev->via_config->udma_mask;
1da177e4 LT	448	hwif->mwdma_mask = 0x07;
	449	hwif->swdma_mask = 0x07;
	450
49521f97 BZ	451	if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
	452	if ((vdev->via_80w >> hwif->channel) & 1)
	453	hwif->cbl = ATA_CBL_PATA80;
	454	else
	455	hwif->cbl = ATA_CBL_PATA40;
	456	}
	457
1da177e4 LT	458	hwif->ide_dma_check = &via82cxxx_ide_dma_check;
	459	if (!noautodma)
	460	hwif->autodma = 1;
	461	hwif->drives[0].autodma = hwif->autodma;
	462	hwif->drives[1].autodma = hwif->autodma;
	463	}
	464
4f1d774a MK	465	static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = {
	466	{ /* 0 */
	467	.name = "VP_IDE",
	468	.init_chipset = init_chipset_via82cxxx,
	469	.init_hwif = init_hwif_via82cxxx,
	470	.channels = 2,
	471	.autodma = NOAUTODMA,
	472	.enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
	473	.bootable = ON_BOARD
	474	},{ /* 1 */
	475	.name = "VP_IDE",
	476	.init_chipset = init_chipset_via82cxxx,
	477	.init_hwif = init_hwif_via82cxxx,
	478	.channels = 2,
	479	.autodma = AUTODMA,
	480	.enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
	481	.bootable = ON_BOARD,
	482	}
1da177e4 LT	483	};
	484
	485	static int __devinit via_init_one(struct pci_dev dev, const struct pci_device_id id)
	486	{
23a1b2a7 AC	487	struct pci_dev *isa = NULL;
	488	struct via_isa_bridge *via_config;
	489	/*
	490	* Find the ISA bridge and check we know what it is.
	491	*/
	492	via_config = via_config_find(&isa);
	493	pci_dev_put(isa);
	494	if (!via_config->id) {
	495	printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
	496	return -ENODEV;
	497	}
4f1d774a	498	return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]);
1da177e4 LT	499	}
	500
	501	static struct pci_device_id via_pci_tbl[] = {
	502	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	503	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
4f1d774a	504	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
e0b874df	505	{ PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_SATA_EIDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1da177e4 LT	506	{ 0, },
	507	};
	508	MODULE_DEVICE_TABLE(pci, via_pci_tbl);
	509
	510	static struct pci_driver driver = {
	511	.name = "VIA_IDE",
	512	.id_table = via_pci_tbl,
	513	.probe = via_init_one,
	514	};
	515
82ab1eec	516	static int __init via_ide_init(void)
1da177e4 LT	517	{
	518	return ide_pci_register_driver(&driver);
	519	}
	520
	521	module_init(via_ide_init);
	522
	523	MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
	524	MODULE_DESCRIPTION("PCI driver module for VIA IDE");
	525	MODULE_LICENSE("GPL");