Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * VIA IDE driver for Linux. Supported southbridges: |
3 | * | |
4 | * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, | |
5 | * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, | |
a7dec1e0 | 6 | * vt8235, vt8237, vt8237a |
1da177e4 LT |
7 | * |
8 | * Copyright (c) 2000-2002 Vojtech Pavlik | |
75b1d975 | 9 | * Copyright (c) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
10 | * |
11 | * Based on the work of: | |
12 | * Michel Aubry | |
13 | * Jeff Garzik | |
14 | * Andre Hedrick | |
15 | * | |
16 | * Documentation: | |
17 | * Obsolete device documentation publically available from via.com.tw | |
18 | * Current device documentation available under NDA only | |
19 | */ | |
20 | ||
21 | /* | |
22 | * This program is free software; you can redistribute it and/or modify it | |
23 | * under the terms of the GNU General Public License version 2 as published by | |
24 | * the Free Software Foundation. | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | #include <linux/module.h> |
28 | #include <linux/kernel.h> | |
1da177e4 LT |
29 | #include <linux/pci.h> |
30 | #include <linux/init.h> | |
31 | #include <linux/ide.h> | |
bdab00b7 BZ |
32 | #include <linux/dmi.h> |
33 | ||
74a9d5f1 | 34 | #ifdef CONFIG_PPC_CHRP |
1da177e4 LT |
35 | #include <asm/processor.h> |
36 | #endif | |
37 | ||
1da177e4 LT |
38 | #define VIA_IDE_ENABLE 0x40 |
39 | #define VIA_IDE_CONFIG 0x41 | |
40 | #define VIA_FIFO_CONFIG 0x43 | |
41 | #define VIA_MISC_1 0x44 | |
42 | #define VIA_MISC_2 0x45 | |
43 | #define VIA_MISC_3 0x46 | |
44 | #define VIA_DRIVE_TIMING 0x48 | |
45 | #define VIA_8BIT_TIMING 0x4e | |
46 | #define VIA_ADDRESS_SETUP 0x4c | |
47 | #define VIA_UDMA_TIMING 0x50 | |
48 | ||
75b1d975 BZ |
49 | #define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */ |
50 | #define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */ | |
51 | #define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */ | |
52 | #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */ | |
53 | #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */ | |
54 | #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */ | |
1da177e4 LT |
55 | |
56 | /* | |
57 | * VIA SouthBridge chips. | |
58 | */ | |
59 | ||
60 | static struct via_isa_bridge { | |
61 | char *name; | |
62 | u16 id; | |
63 | u8 rev_min; | |
64 | u8 rev_max; | |
75b1d975 BZ |
65 | u8 udma_mask; |
66 | u8 flags; | |
1da177e4 | 67 | } via_isa_bridges[] = { |
b311ec4a | 68 | { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
75b1d975 BZ |
69 | { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, |
70 | { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
71 | { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
72 | { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
73 | { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
74 | { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
75 | { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
76 | { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST }, | |
77 | { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, }, | |
78 | { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, }, | |
79 | { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, }, | |
80 | { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, }, | |
81 | { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, }, | |
82 | { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
83 | { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, }, | |
84 | { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 }, | |
85 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO }, | |
86 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ }, | |
87 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO }, | |
88 | { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO }, | |
89 | { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO }, | |
90 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK }, | |
91 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, | |
1da177e4 LT |
92 | { NULL } |
93 | }; | |
94 | ||
1da177e4 | 95 | static unsigned int via_clock; |
75b1d975 | 96 | static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" }; |
1da177e4 | 97 | |
7462cbff DD |
98 | struct via82cxxx_dev |
99 | { | |
100 | struct via_isa_bridge *via_config; | |
101 | unsigned int via_80w; | |
102 | }; | |
103 | ||
1da177e4 LT |
104 | /** |
105 | * via_set_speed - write timing registers | |
106 | * @dev: PCI device | |
107 | * @dn: device | |
108 | * @timing: IDE timing data to use | |
109 | * | |
110 | * via_set_speed writes timing values to the chipset registers | |
111 | */ | |
112 | ||
7462cbff | 113 | static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) |
1da177e4 | 114 | { |
36501650 BZ |
115 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
116 | struct via82cxxx_dev *vdev = pci_get_drvdata(dev); | |
1da177e4 LT |
117 | u8 t; |
118 | ||
7462cbff | 119 | if (~vdev->via_config->flags & VIA_BAD_AST) { |
1da177e4 | 120 | pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t); |
d6cddd3c | 121 | t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); |
1da177e4 LT |
122 | pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t); |
123 | } | |
124 | ||
125 | pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)), | |
d6cddd3c | 126 | ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); |
1da177e4 LT |
127 | |
128 | pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn), | |
d6cddd3c | 129 | ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); |
1da177e4 | 130 | |
75b1d975 | 131 | switch (vdev->via_config->udma_mask) { |
d6cddd3c HH |
132 | case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; |
133 | case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break; | |
134 | case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; | |
135 | case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; | |
75b1d975 | 136 | default: return; |
1da177e4 LT |
137 | } |
138 | ||
139 | pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t); | |
140 | } | |
141 | ||
142 | /** | |
143 | * via_set_drive - configure transfer mode | |
144 | * @drive: Drive to set up | |
145 | * @speed: desired speed | |
146 | * | |
88b2b32b BZ |
147 | * via_set_drive() computes timing values configures the chipset to |
148 | * a desired transfer mode. It also can be called by upper layers. | |
1da177e4 LT |
149 | */ |
150 | ||
88b2b32b | 151 | static void via_set_drive(ide_drive_t *drive, const u8 speed) |
1da177e4 | 152 | { |
36501650 BZ |
153 | ide_hwif_t *hwif = drive->hwif; |
154 | ide_drive_t *peer = hwif->drives + (~drive->dn & 1); | |
155 | struct pci_dev *dev = to_pci_dev(hwif->dev); | |
156 | struct via82cxxx_dev *vdev = pci_get_drvdata(dev); | |
1da177e4 LT |
157 | struct ide_timing t, p; |
158 | unsigned int T, UT; | |
159 | ||
1da177e4 LT |
160 | T = 1000000000 / via_clock; |
161 | ||
75b1d975 BZ |
162 | switch (vdev->via_config->udma_mask) { |
163 | case ATA_UDMA2: UT = T; break; | |
164 | case ATA_UDMA4: UT = T/2; break; | |
165 | case ATA_UDMA5: UT = T/3; break; | |
166 | case ATA_UDMA6: UT = T/4; break; | |
167 | default: UT = T; | |
1da177e4 LT |
168 | } |
169 | ||
170 | ide_timing_compute(drive, speed, &t, T, UT); | |
171 | ||
172 | if (peer->present) { | |
173 | ide_timing_compute(peer, peer->current_speed, &p, T, UT); | |
174 | ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); | |
175 | } | |
176 | ||
7462cbff | 177 | via_set_speed(HWIF(drive), drive->dn, &t); |
1da177e4 LT |
178 | } |
179 | ||
180 | /** | |
88b2b32b | 181 | * via_set_pio_mode - set host controller for PIO mode |
26bcb879 BZ |
182 | * @drive: drive |
183 | * @pio: PIO mode number | |
1da177e4 LT |
184 | * |
185 | * A callback from the upper layers for PIO-only tuning. | |
186 | */ | |
187 | ||
26bcb879 | 188 | static void via_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 189 | { |
26bcb879 | 190 | via_set_drive(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
191 | } |
192 | ||
7462cbff DD |
193 | static struct via_isa_bridge *via_config_find(struct pci_dev **isa) |
194 | { | |
195 | struct via_isa_bridge *via_config; | |
7462cbff DD |
196 | |
197 | for (via_config = via_isa_bridges; via_config->id; via_config++) | |
652aa162 | 198 | if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA + |
7462cbff DD |
199 | !!(via_config->flags & VIA_BAD_ID), |
200 | via_config->id, NULL))) { | |
201 | ||
44c10138 AK |
202 | if ((*isa)->revision >= via_config->rev_min && |
203 | (*isa)->revision <= via_config->rev_max) | |
7462cbff | 204 | break; |
652aa162 | 205 | pci_dev_put(*isa); |
7462cbff DD |
206 | } |
207 | ||
208 | return via_config; | |
1da177e4 LT |
209 | } |
210 | ||
cd36beec BZ |
211 | /* |
212 | * Check and handle 80-wire cable presence | |
213 | */ | |
214 | static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u) | |
215 | { | |
216 | int i; | |
217 | ||
75b1d975 BZ |
218 | switch (vdev->via_config->udma_mask) { |
219 | case ATA_UDMA4: | |
cd36beec BZ |
220 | for (i = 24; i >= 0; i -= 8) |
221 | if (((u >> (i & 16)) & 8) && | |
222 | ((u >> i) & 0x20) && | |
223 | (((u >> i) & 7) < 2)) { | |
224 | /* | |
225 | * 2x PCI clock and | |
226 | * UDMA w/ < 3T/cycle | |
227 | */ | |
228 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
229 | } | |
230 | break; | |
231 | ||
75b1d975 | 232 | case ATA_UDMA5: |
cd36beec BZ |
233 | for (i = 24; i >= 0; i -= 8) |
234 | if (((u >> i) & 0x10) || | |
235 | (((u >> i) & 0x20) && | |
236 | (((u >> i) & 7) < 4))) { | |
237 | /* BIOS 80-wire bit or | |
238 | * UDMA w/ < 60ns/cycle | |
239 | */ | |
240 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
241 | } | |
242 | break; | |
243 | ||
75b1d975 | 244 | case ATA_UDMA6: |
cd36beec BZ |
245 | for (i = 24; i >= 0; i -= 8) |
246 | if (((u >> i) & 0x10) || | |
247 | (((u >> i) & 0x20) && | |
248 | (((u >> i) & 7) < 6))) { | |
249 | /* BIOS 80-wire bit or | |
250 | * UDMA w/ < 60ns/cycle | |
251 | */ | |
252 | vdev->via_80w |= (1 << (1 - (i >> 4))); | |
253 | } | |
254 | break; | |
255 | } | |
256 | } | |
257 | ||
1da177e4 LT |
258 | /** |
259 | * init_chipset_via82cxxx - initialization handler | |
260 | * @dev: PCI device | |
261 | * @name: Name of interface | |
262 | * | |
263 | * The initialization callback. Here we determine the IDE chip type | |
264 | * and initialize its drive independent registers. | |
265 | */ | |
266 | ||
f3718d3e | 267 | static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name) |
1da177e4 LT |
268 | { |
269 | struct pci_dev *isa = NULL; | |
cd36beec | 270 | struct via82cxxx_dev *vdev; |
7462cbff | 271 | struct via_isa_bridge *via_config; |
1da177e4 | 272 | u8 t, v; |
cd36beec BZ |
273 | u32 u; |
274 | ||
275 | vdev = kzalloc(sizeof(*vdev), GFP_KERNEL); | |
276 | if (!vdev) { | |
277 | printk(KERN_ERR "VP_IDE: out of memory :(\n"); | |
278 | return -ENOMEM; | |
279 | } | |
280 | pci_set_drvdata(dev, vdev); | |
1da177e4 LT |
281 | |
282 | /* | |
283 | * Find the ISA bridge to see how good the IDE is. | |
284 | */ | |
cd36beec | 285 | vdev->via_config = via_config = via_config_find(&isa); |
23a1b2a7 AC |
286 | |
287 | /* We checked this earlier so if it fails here deeep badness | |
288 | is involved */ | |
289 | ||
290 | BUG_ON(!via_config->id); | |
1da177e4 LT |
291 | |
292 | /* | |
cd36beec | 293 | * Detect cable and configure Clk66 |
1da177e4 | 294 | */ |
cd36beec BZ |
295 | pci_read_config_dword(dev, VIA_UDMA_TIMING, &u); |
296 | ||
297 | via_cable_detect(vdev, u); | |
1da177e4 | 298 | |
75b1d975 | 299 | if (via_config->udma_mask == ATA_UDMA4) { |
7462cbff | 300 | /* Enable Clk66 */ |
7462cbff DD |
301 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008); |
302 | } else if (via_config->flags & VIA_BAD_CLK66) { | |
1da177e4 | 303 | /* Would cause trouble on 596a and 686 */ |
1da177e4 LT |
304 | pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008); |
305 | } | |
306 | ||
307 | /* | |
308 | * Check whether interfaces are enabled. | |
309 | */ | |
310 | ||
311 | pci_read_config_byte(dev, VIA_IDE_ENABLE, &v); | |
312 | ||
313 | /* | |
314 | * Set up FIFO sizes and thresholds. | |
315 | */ | |
316 | ||
317 | pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t); | |
318 | ||
319 | /* Disable PREQ# till DDACK# */ | |
320 | if (via_config->flags & VIA_BAD_PREQ) { | |
321 | /* Would crash on 586b rev 41 */ | |
322 | t &= 0x7f; | |
323 | } | |
324 | ||
325 | /* Fix FIFO split between channels */ | |
326 | if (via_config->flags & VIA_SET_FIFO) { | |
327 | t &= (t & 0x9f); | |
328 | switch (v & 3) { | |
329 | case 2: t |= 0x00; break; /* 16 on primary */ | |
330 | case 1: t |= 0x60; break; /* 16 on secondary */ | |
331 | case 3: t |= 0x20; break; /* 8 pri 8 sec */ | |
332 | } | |
333 | } | |
334 | ||
335 | pci_write_config_byte(dev, VIA_FIFO_CONFIG, t); | |
336 | ||
337 | /* | |
338 | * Determine system bus clock. | |
339 | */ | |
340 | ||
30e5ee4d | 341 | via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000; |
1da177e4 LT |
342 | |
343 | switch (via_clock) { | |
344 | case 33000: via_clock = 33333; break; | |
345 | case 37000: via_clock = 37500; break; | |
346 | case 41000: via_clock = 41666; break; | |
347 | } | |
348 | ||
349 | if (via_clock < 20000 || via_clock > 50000) { | |
350 | printk(KERN_WARNING "VP_IDE: User given PCI clock speed " | |
351 | "impossible (%d), using 33 MHz instead.\n", via_clock); | |
352 | printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want " | |
353 | "to assume 80-wire cable.\n"); | |
354 | via_clock = 33333; | |
355 | } | |
356 | ||
357 | /* | |
358 | * Print the boot message. | |
359 | */ | |
360 | ||
75b1d975 | 361 | printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s " |
1da177e4 | 362 | "controller on pci%s\n", |
44c10138 | 363 | via_config->name, isa->revision, |
75b1d975 BZ |
364 | via_config->udma_mask ? "U" : "MW", |
365 | via_dma[via_config->udma_mask ? | |
366 | (fls(via_config->udma_mask) - 1) : 0], | |
1da177e4 LT |
367 | pci_name(dev)); |
368 | ||
652aa162 | 369 | pci_dev_put(isa); |
1da177e4 LT |
370 | return 0; |
371 | } | |
372 | ||
bdab00b7 BZ |
373 | /* |
374 | * Cable special cases | |
375 | */ | |
376 | ||
1855256c | 377 | static const struct dmi_system_id cable_dmi_table[] = { |
bdab00b7 BZ |
378 | { |
379 | .ident = "Acer Ferrari 3400", | |
380 | .matches = { | |
381 | DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."), | |
382 | DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"), | |
383 | }, | |
384 | }, | |
385 | { } | |
386 | }; | |
387 | ||
58e47bb1 | 388 | static int via_cable_override(struct pci_dev *pdev) |
bdab00b7 BZ |
389 | { |
390 | /* Systems by DMI */ | |
391 | if (dmi_check_system(cable_dmi_table)) | |
392 | return 1; | |
58e47bb1 BZ |
393 | |
394 | /* Arima W730-K8/Targa Visionary 811/... */ | |
395 | if (pdev->subsystem_vendor == 0x161F && | |
396 | pdev->subsystem_device == 0x2032) | |
397 | return 1; | |
398 | ||
bdab00b7 BZ |
399 | return 0; |
400 | } | |
401 | ||
402 | static u8 __devinit via82cxxx_cable_detect(ide_hwif_t *hwif) | |
403 | { | |
36501650 | 404 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
58e47bb1 | 405 | struct via82cxxx_dev *vdev = pci_get_drvdata(pdev); |
bdab00b7 | 406 | |
58e47bb1 | 407 | if (via_cable_override(pdev)) |
bdab00b7 BZ |
408 | return ATA_CBL_PATA40_SHORT; |
409 | ||
410 | if ((vdev->via_80w >> hwif->channel) & 1) | |
411 | return ATA_CBL_PATA80; | |
412 | else | |
413 | return ATA_CBL_PATA40; | |
414 | } | |
415 | ||
ac95beed BZ |
416 | static const struct ide_port_ops via_port_ops = { |
417 | .set_pio_mode = via_set_pio_mode, | |
418 | .set_dma_mode = via_set_drive, | |
419 | .cable_detect = via82cxxx_cable_detect, | |
420 | }; | |
1da177e4 | 421 | |
85620436 | 422 | static const struct ide_port_info via82cxxx_chipset __devinitdata = { |
6157332e BZ |
423 | .name = "VP_IDE", |
424 | .init_chipset = init_chipset_via82cxxx, | |
6157332e | 425 | .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } }, |
ac95beed | 426 | .port_ops = &via_port_ops, |
6157332e | 427 | .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST | |
6157332e | 428 | IDE_HFLAG_POST_SET_MODE | |
5e71d9c5 | 429 | IDE_HFLAG_IO_32BIT, |
6157332e BZ |
430 | .pio_mask = ATA_PIO5, |
431 | .swdma_mask = ATA_SWDMA2, | |
432 | .mwdma_mask = ATA_MWDMA2, | |
1da177e4 LT |
433 | }; |
434 | ||
435 | static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
436 | { | |
23a1b2a7 AC |
437 | struct pci_dev *isa = NULL; |
438 | struct via_isa_bridge *via_config; | |
6157332e | 439 | u8 idx = id->driver_data; |
039788e1 | 440 | struct ide_port_info d; |
6157332e BZ |
441 | |
442 | d = via82cxxx_chipset; | |
8acf28c0 | 443 | |
23a1b2a7 AC |
444 | /* |
445 | * Find the ISA bridge and check we know what it is. | |
446 | */ | |
447 | via_config = via_config_find(&isa); | |
448 | pci_dev_put(isa); | |
449 | if (!via_config->id) { | |
450 | printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n"); | |
451 | return -ENODEV; | |
452 | } | |
8acf28c0 | 453 | |
6157332e BZ |
454 | if (idx == 0) |
455 | d.host_flags |= IDE_HFLAG_NO_AUTODMA; | |
caea7602 | 456 | else |
6157332e BZ |
457 | d.enablebits[1].reg = d.enablebits[0].reg = 0; |
458 | ||
459 | if ((via_config->flags & VIA_NO_UNMASK) == 0) | |
460 | d.host_flags |= IDE_HFLAG_UNMASK_IRQS; | |
caea7602 | 461 | |
8acf28c0 BZ |
462 | #ifdef CONFIG_PPC_CHRP |
463 | if (machine_is(chrp) && _chrp_type == _CHRP_Pegasos) | |
6157332e | 464 | d.host_flags |= IDE_HFLAG_FORCE_LEGACY_IRQS; |
8acf28c0 BZ |
465 | #endif |
466 | ||
6157332e | 467 | d.udma_mask = via_config->udma_mask; |
8acf28c0 | 468 | |
6cdf6eb3 | 469 | return ide_pci_init_one(dev, &d, NULL); |
1da177e4 LT |
470 | } |
471 | ||
9cbcc5e3 BZ |
472 | static const struct pci_device_id via_pci_tbl[] = { |
473 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 }, | |
474 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 }, | |
84f7e451 | 475 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 }, |
9cbcc5e3 BZ |
476 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 }, |
477 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 }, | |
1da177e4 LT |
478 | { 0, }, |
479 | }; | |
480 | MODULE_DEVICE_TABLE(pci, via_pci_tbl); | |
481 | ||
482 | static struct pci_driver driver = { | |
483 | .name = "VIA_IDE", | |
484 | .id_table = via_pci_tbl, | |
485 | .probe = via_init_one, | |
486 | }; | |
487 | ||
82ab1eec | 488 | static int __init via_ide_init(void) |
1da177e4 LT |
489 | { |
490 | return ide_pci_register_driver(&driver); | |
491 | } | |
492 | ||
493 | module_init(via_ide_init); | |
494 | ||
495 | MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick"); | |
496 | MODULE_DESCRIPTION("PCI driver module for VIA IDE"); | |
497 | MODULE_LICENSE("GPL"); |