Commit | Line | Data |
---|---|---|
33dced2e | 1 | /* |
31e8a465 | 2 | * drivers/ide/pci/tc86c001.c Version 1.01 Sep 5, 2007 |
33dced2e SS |
3 | * |
4 | * Copyright (C) 2002 Toshiba Corporation | |
5 | * Copyright (C) 2005-2006 MontaVista Software, Inc. <source@mvista.com> | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/types.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/ide.h> | |
15 | ||
88b2b32b | 16 | static void tc86c001_set_mode(ide_drive_t *drive, const u8 speed) |
33dced2e SS |
17 | { |
18 | ide_hwif_t *hwif = HWIF(drive); | |
19 | unsigned long scr_port = hwif->config_data + (drive->dn ? 0x02 : 0x00); | |
31e8a465 | 20 | u16 mode, scr = inw(scr_port); |
33dced2e | 21 | |
33dced2e SS |
22 | switch (speed) { |
23 | case XFER_UDMA_4: mode = 0x00c0; break; | |
24 | case XFER_UDMA_3: mode = 0x00b0; break; | |
25 | case XFER_UDMA_2: mode = 0x00a0; break; | |
26 | case XFER_UDMA_1: mode = 0x0090; break; | |
27 | case XFER_UDMA_0: mode = 0x0080; break; | |
28 | case XFER_MW_DMA_2: mode = 0x0070; break; | |
29 | case XFER_MW_DMA_1: mode = 0x0060; break; | |
30 | case XFER_MW_DMA_0: mode = 0x0050; break; | |
31 | case XFER_PIO_4: mode = 0x0400; break; | |
32 | case XFER_PIO_3: mode = 0x0300; break; | |
33 | case XFER_PIO_2: mode = 0x0200; break; | |
34 | case XFER_PIO_1: mode = 0x0100; break; | |
35 | case XFER_PIO_0: | |
36 | default: mode = 0x0000; break; | |
37 | } | |
38 | ||
39 | scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f; | |
40 | scr |= mode; | |
0ecdca26 | 41 | outw(scr, scr_port); |
33dced2e SS |
42 | } |
43 | ||
26bcb879 | 44 | static void tc86c001_set_pio_mode(ide_drive_t *drive, const u8 pio) |
33dced2e | 45 | { |
88b2b32b | 46 | tc86c001_set_mode(drive, XFER_PIO_0 + pio); |
33dced2e SS |
47 | } |
48 | ||
49 | /* | |
50 | * HACKITY HACK | |
51 | * | |
52 | * This is a workaround for the limitation 5 of the TC86C001 IDE controller: | |
53 | * if a DMA transfer terminates prematurely, the controller leaves the device's | |
54 | * interrupt request (INTRQ) pending and does not generate a PCI interrupt (or | |
55 | * set the interrupt bit in the DMA status register), thus no PCI interrupt | |
56 | * will occur until a DMA transfer has been successfully completed. | |
57 | * | |
58 | * We work around this by initiating dummy, zero-length DMA transfer on | |
59 | * a DMA timeout expiration. I found no better way to do this with the current | |
60 | * IDE core than to temporarily replace a higher level driver's timer expiry | |
61 | * handler with our own backing up to that handler in case our recovery fails. | |
62 | */ | |
63 | static int tc86c001_timer_expiry(ide_drive_t *drive) | |
64 | { | |
65 | ide_hwif_t *hwif = HWIF(drive); | |
66 | ide_expiry_t *expiry = ide_get_hwifdata(hwif); | |
67 | ide_hwgroup_t *hwgroup = HWGROUP(drive); | |
31e8a465 | 68 | u8 dma_stat = inb(hwif->dma_status); |
33dced2e SS |
69 | |
70 | /* Restore a higher level driver's expiry handler first. */ | |
71 | hwgroup->expiry = expiry; | |
72 | ||
73 | if ((dma_stat & 5) == 1) { /* DMA active and no interrupt */ | |
74 | unsigned long sc_base = hwif->config_data; | |
75 | unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04); | |
31e8a465 | 76 | u8 dma_cmd = inb(hwif->dma_command); |
33dced2e SS |
77 | |
78 | printk(KERN_WARNING "%s: DMA interrupt possibly stuck, " | |
79 | "attempting recovery...\n", drive->name); | |
80 | ||
81 | /* Stop DMA */ | |
0ecdca26 | 82 | outb(dma_cmd & ~0x01, hwif->dma_command); |
33dced2e SS |
83 | |
84 | /* Setup the dummy DMA transfer */ | |
0ecdca26 BZ |
85 | outw(0, sc_base + 0x0a); /* Sector Count */ |
86 | outw(0, twcr_port); /* Transfer Word Count 1 or 2 */ | |
33dced2e SS |
87 | |
88 | /* Start the dummy DMA transfer */ | |
0ecdca26 BZ |
89 | outb(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */ |
90 | outb(0x01, hwif->dma_command); /* set START_STOPBM */ | |
33dced2e SS |
91 | |
92 | /* | |
93 | * If an interrupt was pending, it should come thru shortly. | |
94 | * If not, a higher level driver's expiry handler should | |
95 | * eventually cause some kind of recovery from the DMA stall. | |
96 | */ | |
97 | return WAIT_MIN_SLEEP; | |
98 | } | |
99 | ||
100 | /* Chain to the restored expiry handler if DMA wasn't active. */ | |
101 | if (likely(expiry != NULL)) | |
102 | return expiry(drive); | |
103 | ||
104 | /* If there was no handler, "emulate" that for ide_timer_expiry()... */ | |
105 | return -1; | |
106 | } | |
107 | ||
108 | static void tc86c001_dma_start(ide_drive_t *drive) | |
109 | { | |
110 | ide_hwif_t *hwif = HWIF(drive); | |
111 | ide_hwgroup_t *hwgroup = HWGROUP(drive); | |
112 | unsigned long sc_base = hwif->config_data; | |
113 | unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04); | |
114 | unsigned long nsectors = hwgroup->rq->nr_sectors; | |
115 | ||
116 | /* | |
117 | * We have to manually load the sector count and size into | |
118 | * the appropriate system control registers for DMA to work | |
119 | * with LBA48 and ATAPI devices... | |
120 | */ | |
0ecdca26 BZ |
121 | outw(nsectors, sc_base + 0x0a); /* Sector Count */ |
122 | outw(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */ | |
33dced2e SS |
123 | |
124 | /* Install our timeout expiry hook, saving the current handler... */ | |
125 | ide_set_hwifdata(hwif, hwgroup->expiry); | |
126 | hwgroup->expiry = &tc86c001_timer_expiry; | |
127 | ||
128 | ide_dma_start(drive); | |
129 | } | |
130 | ||
131 | static int tc86c001_busproc(ide_drive_t *drive, int state) | |
132 | { | |
133 | ide_hwif_t *hwif = HWIF(drive); | |
134 | unsigned long sc_base = hwif->config_data; | |
135 | u16 scr1; | |
136 | ||
137 | /* System Control 1 Register bit 11 (ATA Hard Reset) read */ | |
31e8a465 | 138 | scr1 = inw(sc_base + 0x00); |
33dced2e SS |
139 | |
140 | switch (state) { | |
141 | case BUSSTATE_ON: | |
142 | if (!(scr1 & 0x0800)) | |
143 | return 0; | |
144 | scr1 &= ~0x0800; | |
145 | ||
146 | hwif->drives[0].failures = hwif->drives[1].failures = 0; | |
147 | break; | |
148 | case BUSSTATE_OFF: | |
149 | if (scr1 & 0x0800) | |
150 | return 0; | |
151 | scr1 |= 0x0800; | |
152 | ||
153 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | |
154 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
155 | break; | |
156 | default: | |
157 | return -EINVAL; | |
158 | } | |
159 | ||
160 | /* System Control 1 Register bit 11 (ATA Hard Reset) write */ | |
0ecdca26 | 161 | outw(scr1, sc_base + 0x00); |
33dced2e SS |
162 | return 0; |
163 | } | |
164 | ||
e8ab7f53 | 165 | static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif) |
33dced2e SS |
166 | { |
167 | unsigned long sc_base = pci_resource_start(hwif->pci_dev, 5); | |
31e8a465 | 168 | u16 scr1 = inw(sc_base + 0x00); |
33dced2e SS |
169 | |
170 | /* System Control 1 Register bit 15 (Soft Reset) set */ | |
0ecdca26 | 171 | outw(scr1 | 0x8000, sc_base + 0x00); |
33dced2e SS |
172 | |
173 | /* System Control 1 Register bit 14 (FIFO Reset) set */ | |
0ecdca26 | 174 | outw(scr1 | 0x4000, sc_base + 0x00); |
33dced2e SS |
175 | |
176 | /* System Control 1 Register: reset clear */ | |
0ecdca26 | 177 | outw(scr1 & ~0xc000, sc_base + 0x00); |
33dced2e SS |
178 | |
179 | /* Store the system control register base for convenience... */ | |
180 | hwif->config_data = sc_base; | |
181 | ||
26bcb879 | 182 | hwif->set_pio_mode = &tc86c001_set_pio_mode; |
88b2b32b BZ |
183 | hwif->set_dma_mode = &tc86c001_set_mode; |
184 | ||
33dced2e SS |
185 | hwif->busproc = &tc86c001_busproc; |
186 | ||
33dced2e SS |
187 | if (!hwif->dma_base) |
188 | return; | |
189 | ||
190 | /* | |
191 | * Sector Count Control Register bits 0 and 1 set: | |
192 | * software sets Sector Count Register for master and slave device | |
193 | */ | |
0ecdca26 | 194 | outw(0x0003, sc_base + 0x0c); |
33dced2e SS |
195 | |
196 | /* Sector Count Register limit */ | |
197 | hwif->rqsize = 0xffff; | |
198 | ||
33dced2e SS |
199 | hwif->dma_start = &tc86c001_dma_start; |
200 | ||
49521f97 | 201 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) { |
33dced2e SS |
202 | /* |
203 | * System Control 1 Register bit 13 (PDIAGN): | |
204 | * 0=80-pin cable, 1=40-pin cable | |
205 | */ | |
31e8a465 | 206 | scr1 = inw(sc_base + 0x00); |
49521f97 | 207 | hwif->cbl = (scr1 & 0x2000) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; |
33dced2e | 208 | } |
33dced2e SS |
209 | } |
210 | ||
ba59c4b8 AM |
211 | static unsigned int __devinit init_chipset_tc86c001(struct pci_dev *dev, |
212 | const char *name) | |
33dced2e SS |
213 | { |
214 | int err = pci_request_region(dev, 5, name); | |
215 | ||
216 | if (err) | |
217 | printk(KERN_ERR "%s: system control regs already in use", name); | |
218 | return err; | |
219 | } | |
220 | ||
85620436 | 221 | static const struct ide_port_info tc86c001_chipset __devinitdata = { |
33dced2e SS |
222 | .name = "TC86C001", |
223 | .init_chipset = init_chipset_tc86c001, | |
224 | .init_hwif = init_hwif_tc86c001, | |
7cab14a7 | 225 | .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD, |
4099d143 | 226 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
227 | .mwdma_mask = ATA_MWDMA2, |
228 | .udma_mask = ATA_UDMA4, | |
33dced2e SS |
229 | }; |
230 | ||
231 | static int __devinit tc86c001_init_one(struct pci_dev *dev, | |
232 | const struct pci_device_id *id) | |
233 | { | |
234 | return ide_setup_pci_device(dev, &tc86c001_chipset); | |
235 | } | |
236 | ||
9cbcc5e3 BZ |
237 | static const struct pci_device_id tc86c001_pci_tbl[] = { |
238 | { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE), 0 }, | |
33dced2e SS |
239 | { 0, } |
240 | }; | |
241 | MODULE_DEVICE_TABLE(pci, tc86c001_pci_tbl); | |
242 | ||
243 | static struct pci_driver driver = { | |
244 | .name = "TC86C001", | |
245 | .id_table = tc86c001_pci_tbl, | |
246 | .probe = tc86c001_init_one | |
247 | }; | |
248 | ||
a534b68d | 249 | static int __init tc86c001_ide_init(void) |
33dced2e SS |
250 | { |
251 | return ide_pci_register_driver(&driver); | |
252 | } | |
253 | module_init(tc86c001_ide_init); | |
254 | ||
255 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); | |
256 | MODULE_DESCRIPTION("PCI driver module for TC86C001 IDE"); | |
257 | MODULE_LICENSE("GPL"); |