Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org> |
07af4276 | 3 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 | 4 | * |
44854add | 5 | * This is a look-alike variation of the ICH0 PIIX4 Ultra-66, |
1da177e4 LT |
6 | * but this keeps the ISA-Bridge and slots alive. |
7 | * | |
8 | */ | |
9 | ||
1da177e4 LT |
10 | #include <linux/types.h> |
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/ioport.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/hdreg.h> | |
16 | #include <linux/ide.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/init.h> | |
19 | ||
20 | #include <asm/io.h> | |
21 | ||
a482958b BZ |
22 | static DEFINE_SPINLOCK(slc90e66_lock); |
23 | ||
88b2b32b | 24 | static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 LT |
25 | { |
26 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 27 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
24e6458d | 28 | int is_slave = drive->dn & 1; |
1da177e4 LT |
29 | int master_port = hwif->channel ? 0x42 : 0x40; |
30 | int slave_port = 0x44; | |
31 | unsigned long flags; | |
32 | u16 master_data; | |
33 | u8 slave_data; | |
24e6458d SS |
34 | int control = 0; |
35 | /* ISP RTC */ | |
f201f504 | 36 | static const u8 timings[][2]= { |
24e6458d SS |
37 | { 0, 0 }, |
38 | { 0, 0 }, | |
39 | { 1, 0 }, | |
40 | { 2, 1 }, | |
41 | { 2, 3 }, }; | |
1da177e4 | 42 | |
a482958b | 43 | spin_lock_irqsave(&slc90e66_lock, flags); |
1da177e4 | 44 | pci_read_config_word(dev, master_port, &master_data); |
24e6458d SS |
45 | |
46 | if (pio > 1) | |
47 | control |= 1; /* Programmable timing on */ | |
48 | if (drive->media == ide_disk) | |
49 | control |= 4; /* Prefetch, post write */ | |
50 | if (pio > 2) | |
51 | control |= 2; /* IORDY */ | |
1da177e4 | 52 | if (is_slave) { |
24e6458d SS |
53 | master_data |= 0x4000; |
54 | master_data &= ~0x0070; | |
55 | if (pio > 1) { | |
07af4276 SS |
56 | /* Set PPE, IE and TIME */ |
57 | master_data |= control << 4; | |
24e6458d | 58 | } |
1da177e4 | 59 | pci_read_config_byte(dev, slave_port, &slave_data); |
07af4276 SS |
60 | slave_data &= hwif->channel ? 0x0f : 0xf0; |
61 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << | |
62 | (hwif->channel ? 4 : 0); | |
1da177e4 | 63 | } else { |
24e6458d SS |
64 | master_data &= ~0x3307; |
65 | if (pio > 1) { | |
1da177e4 | 66 | /* enable PPE, IE and TIME */ |
07af4276 | 67 | master_data |= control; |
24e6458d | 68 | } |
07af4276 | 69 | master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8); |
1da177e4 LT |
70 | } |
71 | pci_write_config_word(dev, master_port, master_data); | |
72 | if (is_slave) | |
73 | pci_write_config_byte(dev, slave_port, slave_data); | |
a482958b | 74 | spin_unlock_irqrestore(&slc90e66_lock, flags); |
1da177e4 LT |
75 | } |
76 | ||
88b2b32b | 77 | static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
78 | { |
79 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 80 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 81 | u8 maslave = hwif->channel ? 0x42 : 0x40; |
1da177e4 LT |
82 | int sitre = 0, a_speed = 7 << (drive->dn * 4); |
83 | int u_speed = 0, u_flag = 1 << drive->dn; | |
84 | u16 reg4042, reg44, reg48, reg4a; | |
85 | ||
86 | pci_read_config_word(dev, maslave, ®4042); | |
87 | sitre = (reg4042 & 0x4000) ? 1 : 0; | |
88 | pci_read_config_word(dev, 0x44, ®44); | |
89 | pci_read_config_word(dev, 0x48, ®48); | |
90 | pci_read_config_word(dev, 0x4a, ®4a); | |
91 | ||
1da177e4 | 92 | if (speed >= XFER_UDMA_0) { |
4db90a14 BZ |
93 | u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4); |
94 | ||
1da177e4 LT |
95 | if (!(reg48 & u_flag)) |
96 | pci_write_config_word(dev, 0x48, reg48|u_flag); | |
97 | /* FIXME: (reg4a & a_speed) ? */ | |
98 | if ((reg4a & u_speed) != u_speed) { | |
99 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
100 | pci_read_config_word(dev, 0x4a, ®4a); | |
101 | pci_write_config_word(dev, 0x4a, reg4a|u_speed); | |
102 | } | |
103 | } else { | |
8c91abf8 | 104 | const u8 mwdma_to_pio[] = { 0, 3, 4 }; |
1c54a93d | 105 | u8 pio; |
8c91abf8 | 106 | |
1da177e4 LT |
107 | if (reg48 & u_flag) |
108 | pci_write_config_word(dev, 0x48, reg48 & ~u_flag); | |
109 | if (reg4a & a_speed) | |
110 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
8c91abf8 BZ |
111 | |
112 | if (speed >= XFER_MW_DMA_0) | |
113 | pio = mwdma_to_pio[speed - XFER_MW_DMA_0]; | |
114 | else | |
115 | pio = 2; /* only SWDMA2 is allowed */ | |
1da177e4 | 116 | |
1c54a93d BZ |
117 | slc90e66_set_pio_mode(drive, pio); |
118 | } | |
1da177e4 LT |
119 | } |
120 | ||
97319630 | 121 | static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif) |
1da177e4 | 122 | { |
36501650 | 123 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
124 | u8 reg47 = 0; |
125 | u8 mask = hwif->channel ? 0x01 : 0x02; /* bit0:Primary */ | |
126 | ||
26bcb879 | 127 | hwif->set_pio_mode = &slc90e66_set_pio_mode; |
88b2b32b | 128 | hwif->set_dma_mode = &slc90e66_set_dma_mode; |
1da177e4 | 129 | |
36501650 | 130 | pci_read_config_byte(dev, 0x47, ®47); |
1da177e4 | 131 | |
a7b888b2 | 132 | if (hwif->dma_base == 0) |
1da177e4 | 133 | return; |
1da177e4 | 134 | |
49521f97 | 135 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
1da177e4 | 136 | /* bit[0(1)]: 0:80, 1:40 */ |
49521f97 | 137 | hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; |
1da177e4 LT |
138 | } |
139 | ||
85620436 | 140 | static const struct ide_port_info slc90e66_chipset __devinitdata = { |
1da177e4 LT |
141 | .name = "SLC90E66", |
142 | .init_hwif = init_hwif_slc90e66, | |
1da177e4 | 143 | .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, |
3985ee3b | 144 | .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE, |
4099d143 | 145 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
146 | .swdma_mask = ATA_SWDMA2_ONLY, |
147 | .mwdma_mask = ATA_MWDMA12_ONLY, | |
148 | .udma_mask = ATA_UDMA4, | |
1da177e4 LT |
149 | }; |
150 | ||
151 | static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
152 | { | |
153 | return ide_setup_pci_device(dev, &slc90e66_chipset); | |
154 | } | |
155 | ||
9cbcc5e3 BZ |
156 | static const struct pci_device_id slc90e66_pci_tbl[] = { |
157 | { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 }, | |
1da177e4 LT |
158 | { 0, }, |
159 | }; | |
160 | MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl); | |
161 | ||
162 | static struct pci_driver driver = { | |
163 | .name = "SLC90e66_IDE", | |
164 | .id_table = slc90e66_pci_tbl, | |
165 | .probe = slc90e66_init_one, | |
166 | }; | |
167 | ||
82ab1eec | 168 | static int __init slc90e66_ide_init(void) |
1da177e4 LT |
169 | { |
170 | return ide_pci_register_driver(&driver); | |
171 | } | |
172 | ||
173 | module_init(slc90e66_ide_init); | |
174 | ||
175 | MODULE_AUTHOR("Andre Hedrick"); | |
176 | MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE"); | |
177 | MODULE_LICENSE("GPL"); |