[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ide / pci / sl82c105.c

/*
 * linux/drivers/ide/pci/sl82c105.c
 *
 * SL82C105/Winbond 553 IDE driver
 *
 * Maintainer unknown.
 *
 * Drive tuning added from Rebel.com's kernel sources
 *  -- Russell King (15/11/98) linux@arm.linux.org.uk
 * 
 * Merge in Russell's HW workarounds, fix various problems
 * with the timing registers setup.
 *  -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
 *
 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/dma.h>

#undef DEBUG

#ifdef DEBUG
#define DBG(arg) printk arg
#else
#define DBG(fmt,...)
#endif
/*
 * SL82C105 PCI config register 0x40 bits.
 */
#define CTRL_IDE_IRQB   (1 << 30)
#define CTRL_IDE_IRQA   (1 << 28)
#define CTRL_LEGIRQ     (1 << 11)
#define CTRL_P1F16      (1 << 5)
#define CTRL_P1EN       (1 << 4)
#define CTRL_P0F16      (1 << 1)
#define CTRL_P0EN       (1 << 0)

/*
 * Convert a PIO mode and cycle time to the required on/off times
 * for the interface.  This has protection against runaway timings.
 */
static unsigned int get_pio_timings(ide_pio_data_t *p)
{
	unsigned int cmd_on, cmd_off;

	cmd_on  = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
	cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30;

	if (cmd_on == 0)
		cmd_on = 1;

	if (cmd_off == 0)
		cmd_off = 1;

	return (cmd_on - 1) << 8 | (cmd_off - 1) | (p->use_iordy ? 0x40 : 0x00);
}

/*
 * Configure the chipset for PIO mode.
 */
static u8 sl82c105_tune_pio(ide_drive_t *drive, u8 pio)
{
	struct pci_dev *dev	= HWIF(drive)->pci_dev;
	int reg			= 0x44 + drive->dn * 4;
	ide_pio_data_t p;
	u16 drv_ctrl;

	DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive->name, pio));

	pio = ide_get_best_pio_mode(drive, pio, 5, &p);

	drv_ctrl = get_pio_timings(&p);

	/*
	 * Store the PIO timings so that we can restore them
	 * in case DMA will be turned off...
	 */
	drive->drive_data &= 0xffff0000;
	drive->drive_data |= drv_ctrl;

	if (!drive->using_dma) {
		/*
		 * If we are actually using MW DMA, then we can not
		 * reprogram the interface drive control register.
		 */
		pci_write_config_word(dev, reg,  drv_ctrl);
		pci_read_config_word (dev, reg, &drv_ctrl);
	}

	printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
	       ide_xfer_verbose(pio + XFER_PIO_0), p.cycle_time, drv_ctrl);

	return pio;
}

/*
 * Configure the drive and chipset for a new transfer speed.
 */
static int sl82c105_tune_chipset(ide_drive_t *drive, u8 speed)
{
	static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
	u16 drv_ctrl;

 	DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
	     drive->name, ide_xfer_verbose(speed)));

	speed = ide_rate_filter(drive, speed);

	switch (speed) {
	case XFER_MW_DMA_2:
	case XFER_MW_DMA_1:
	case XFER_MW_DMA_0:
		drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];

		/*
		 * Store the DMA timings so that we can actually program
		 * them when DMA will be turned on...
		 */
		drive->drive_data &= 0x0000ffff;
		drive->drive_data |= (unsigned long)drv_ctrl << 16;

		/*
		 * If we are already using DMA, we just reprogram
		 * the drive control register.
		 */
		if (drive->using_dma) {
			struct pci_dev *dev	= HWIF(drive)->pci_dev;
			int reg 		= 0x44 + drive->dn * 4;

			pci_write_config_word(dev, reg, drv_ctrl);
		}
		break;
	case XFER_PIO_5:
	case XFER_PIO_4:
	case XFER_PIO_3:
	case XFER_PIO_2:
	case XFER_PIO_1:
	case XFER_PIO_0:
		(void) sl82c105_tune_pio(drive, speed - XFER_PIO_0);
		break;
	default:
		return -1;
	}

	return ide_config_drive_speed(drive, speed);
}

/*
 * Check to see if the drive and chipset are capable of DMA mode.
 */
static int sl82c105_ide_dma_check(ide_drive_t *drive)
{
	DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive->name));

	if (ide_tune_dma(drive))
		return 0;

	return -1;
}

/*
 * The SL82C105 holds off all IDE interrupts while in DMA mode until
 * all DMA activity is completed.  Sometimes this causes problems (eg,
 * when the drive wants to report an error condition).
 *
 * 0x7e is a "chip testing" register.  Bit 2 resets the DMA controller
 * state machine.  We need to kick this to work around various bugs.
 */
static inline void sl82c105_reset_host(struct pci_dev *dev)
{
	u16 val;

	pci_read_config_word(dev, 0x7e, &val);
	pci_write_config_word(dev, 0x7e, val | (1 << 2));
	pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
}

/*
 * If we get an IRQ timeout, it might be that the DMA state machine
 * got confused.  Fix from Todd Inglett.  Details from Winbond.
 *
 * This function is called when the IDE timer expires, the drive
 * indicates that it is READY, and we were waiting for DMA to complete.
 */
static void sl82c105_dma_lost_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u32 val, mask		= hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
	u8 dma_cmd;

	printk("sl82c105: lost IRQ, resetting host\n");

	/*
	 * Check the raw interrupt from the drive.
	 */
	pci_read_config_dword(dev, 0x40, &val);
	if (val & mask)
		printk("sl82c105: drive was requesting IRQ, but host lost it\n");

	/*
	 * Was DMA enabled?  If so, disable it - we're resetting the
	 * host.  The IDE layer will be handling the drive for us.
	 */
	dma_cmd = inb(hwif->dma_command);
	if (dma_cmd & 1) {
		outb(dma_cmd & ~1, hwif->dma_command);
		printk("sl82c105: DMA was enabled\n");
	}

	sl82c105_reset_host(dev);
}

/*
 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
 * Winbond recommend that the DMA state machine is reset prior to
 * setting the bus master DMA enable bit.
 *
 * The generic IDE core will have disabled the BMEN bit before this
 * function is called.
 */
static void sl82c105_dma_start(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;

	sl82c105_reset_host(dev);
	ide_dma_start(drive);
}

static void sl82c105_dma_timeout(ide_drive_t *drive)
{
	DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name));

	sl82c105_reset_host(HWIF(drive)->pci_dev);
	ide_dma_timeout(drive);
}

static int sl82c105_ide_dma_on(ide_drive_t *drive)
{
	struct pci_dev *dev	= HWIF(drive)->pci_dev;
	int rc, reg 		= 0x44 + drive->dn * 4;

	DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));

	rc = __ide_dma_on(drive);
	if (rc == 0) {
		pci_write_config_word(dev, reg, drive->drive_data >> 16);

		printk(KERN_INFO "%s: DMA enabled\n", drive->name);
	}
	return rc;
}

static void sl82c105_dma_off_quietly(ide_drive_t *drive)
{
	struct pci_dev *dev	= HWIF(drive)->pci_dev;
	int reg 		= 0x44 + drive->dn * 4;

	DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));

	pci_write_config_word(dev, reg, drive->drive_data);

	ide_dma_off_quietly(drive);
}

/*
 * Ok, that is nasty, but we must make sure the DMA timings
 * won't be used for a PIO access. The solution here is
 * to make sure the 16 bits mode is diabled on the channel
 * when DMA is enabled, thus causing the chip to use PIO0
 * timings for those operations.
 */
static void sl82c105_selectproc(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u32 val, old, mask;

	//DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));

	mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
	old = val = (u32)pci_get_drvdata(dev);
	if (drive->using_dma)
		val &= ~mask;
	else
		val |= mask;
	if (old != val) {
		pci_write_config_dword(dev, 0x40, val);	
		pci_set_drvdata(dev, (void *)val);
	}
}

/*
 * ATA reset will clear the 16 bits mode in the control
 * register, we need to update our cache
 */
static void sl82c105_resetproc(ide_drive_t *drive)
{
	struct pci_dev *dev = HWIF(drive)->pci_dev;
	u32 val;

	DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));

	pci_read_config_dword(dev, 0x40, &val);
	pci_set_drvdata(dev, (void *)val);
}
	
/*
 * We only deal with PIO mode here - DMA mode 'using_dma' is not
 * initialised at the point that this function is called.
 */
static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio)
{
	DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive->name, pio));

	pio = sl82c105_tune_pio(drive, pio);
	(void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
}

/*
 * Return the revision of the Winbond bridge
 * which this function is part of.
 */
static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
{
	struct pci_dev *bridge;

	/*
	 * The bridge should be part of the same device, but function 0.
	 */
	bridge = pci_get_bus_and_slot(dev->bus->number,
			       PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
	if (!bridge)
		return -1;

	/*
	 * Make sure it is a Winbond 553 and is an ISA bridge.
	 */
	if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
	    bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
	    bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
	    	pci_dev_put(bridge);
		return -1;
	}
	/*
	 * We need to find function 0's revision, not function 1
	 */
	pci_dev_put(bridge);

	return bridge->revision;
}

/*
 * Enable the PCI device
 * 
 * --BenH: It's arch fixup code that should enable channels that
 * have not been enabled by firmware. I decided we can still enable
 * channel 0 here at least, but channel 1 has to be enabled by
 * firmware or arch code. We still set both to 16 bits mode.
 */
static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
{
	u32 val;

	DBG(("init_chipset_sl82c105()\n"));

	pci_read_config_dword(dev, 0x40, &val);
	val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
	pci_write_config_dword(dev, 0x40, val);
	pci_set_drvdata(dev, (void *)val);

	return dev->irq;
}

/*
 * Initialise IDE channel
 */
static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
{
	unsigned int rev;

	DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));

	hwif->tuneproc		= &sl82c105_tune_drive;
	hwif->speedproc 	= &sl82c105_tune_chipset;
	hwif->selectproc	= &sl82c105_selectproc;
	hwif->resetproc 	= &sl82c105_resetproc;

	/*
	 * We support 32-bit I/O on this interface, and
	 * it doesn't have problems with interrupts.
	 */
	hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1;
	hwif->drives[0].unmask   = hwif->drives[1].unmask   = 1;

	/*
	 * We always autotune PIO,  this is done before DMA is checked,
	 * so there's no risk of accidentally disabling DMA
	 */
	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;

	if (!hwif->dma_base)
		return;

	rev = sl82c105_bridge_revision(hwif->pci_dev);
	if (rev <= 5) {
		/*
		 * Never ever EVER under any circumstances enable
		 * DMA when the bridge is this old.
		 */
		printk("    %s: Winbond W83C553 bridge revision %d, "
		       "BM-DMA disabled\n", hwif->name, rev);
		return;
	}

	hwif->atapi_dma  = 1;
	hwif->mwdma_mask = 0x07;

	hwif->ide_dma_check		= &sl82c105_ide_dma_check;
	hwif->ide_dma_on		= &sl82c105_ide_dma_on;
	hwif->dma_off_quietly		= &sl82c105_dma_off_quietly;
	hwif->dma_lost_irq		= &sl82c105_dma_lost_irq;
	hwif->dma_start			= &sl82c105_dma_start;
	hwif->dma_timeout		= &sl82c105_dma_timeout;

	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;

	if (hwif->mate)
		hwif->serialized = hwif->mate->serialized = 1;
}

static ide_pci_device_t sl82c105_chipset __devinitdata = {
	.name		= "W82C105",
	.init_chipset	= init_chipset_sl82c105,
	.init_hwif	= init_hwif_sl82c105,
	.channels	= 2,
	.autodma	= NOAUTODMA,
	.enablebits	= {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
	.bootable	= ON_BOARD,
};

static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &sl82c105_chipset);
}

static struct pci_device_id sl82c105_pci_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);

static struct pci_driver driver = {
	.name		= "W82C105_IDE",
	.id_table	= sl82c105_pci_tbl,
	.probe		= sl82c105_init_one,
};

static int __init sl82c105_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(sl82c105_ide_init);

MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/ide/pci/sl82c105.c
	3	*
	4	* SL82C105/Winbond 553 IDE driver
	5	*
	6	* Maintainer unknown.
	7	*
	8	* Drive tuning added from Rebel.com's kernel sources
	9	* -- Russell King (15/11/98) linux@arm.linux.org.uk
	10	*
	11	* Merge in Russell's HW workarounds, fix various problems
	12	* with the timing registers setup.
	13	* -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
e93df705 SS	14	*
e93df705 SS	15	* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	16	*/
1da177e4 LT	17
1da177e4 LT	18	#include <linux/types.h>
	19	#include <linux/module.h>
	20	#include <linux/kernel.h>
	21	#include <linux/timer.h>
	22	#include <linux/mm.h>
	23	#include <linux/ioport.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/blkdev.h>
	26	#include <linux/hdreg.h>
	27	#include <linux/pci.h>
	28	#include <linux/ide.h>
	29
	30	#include <asm/io.h>
	31	#include <asm/dma.h>
	32
	33	#undef DEBUG
	34
	35	#ifdef DEBUG
	36	#define DBG(arg) printk arg
	37	#else
	38	#define DBG(fmt,...)
	39	#endif
	40	/*
	41	* SL82C105 PCI config register 0x40 bits.
	42	*/
	43	#define CTRL_IDE_IRQB (1 << 30)
	44	#define CTRL_IDE_IRQA (1 << 28)
	45	#define CTRL_LEGIRQ (1 << 11)
	46	#define CTRL_P1F16 (1 << 5)
	47	#define CTRL_P1EN (1 << 4)
	48	#define CTRL_P0F16 (1 << 1)
	49	#define CTRL_P0EN (1 << 0)
	50
	51	/*
e93df705 SS	52	* Convert a PIO mode and cycle time to the required on/off times
e93df705 SS	53	* for the interface. This has protection against runaway timings.
1da177e4	54	*/
e93df705	55	static unsigned int get_pio_timings(ide_pio_data_t *p)
1da177e4	56	{
e93df705	57	unsigned int cmd_on, cmd_off;
1da177e4	58
e93df705	59	cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
1da177e4 LT	60	cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30;
1da177e4 LT	61
1da177e4 LT	62	if (cmd_on == 0)
	63	cmd_on = 1;
	64
1da177e4 LT	65	if (cmd_off == 0)
	66	cmd_off = 1;
	67
	68	return (cmd_on - 1) << 8 \| (cmd_off - 1) \| (p->use_iordy ? 0x40 : 0x00);
	69	}
	70
	71	/*
e93df705	72	* Configure the chipset for PIO mode.
1da177e4	73	*/
e93df705	74	static u8 sl82c105_tune_pio(ide_drive_t *drive, u8 pio)
1da177e4	75	{
e93df705 SS	76	struct pci_dev *dev = HWIF(drive)->pci_dev;
e93df705 SS	77	int reg = 0x44 + drive->dn * 4;
1da177e4	78	ide_pio_data_t p;
e93df705	79	u16 drv_ctrl;
1da177e4	80
e93df705	81	DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive->name, pio));
1da177e4 LT	82
	83	pio = ide_get_best_pio_mode(drive, pio, 5, &p);
	84
46cedc9b SS	85	drv_ctrl = get_pio_timings(&p);
	86
	87	/*
	88	* Store the PIO timings so that we can restore them
	89	* in case DMA will be turned off...
	90	*/
	91	drive->drive_data &= 0xffff0000;
	92	drive->drive_data \|= drv_ctrl;
1da177e4	93
e93df705	94	if (!drive->using_dma) {
1da177e4 LT	95	/*
	96	* If we are actually using MW DMA, then we can not
	97	* reprogram the interface drive control register.
	98	*/
e93df705 SS	99	pci_write_config_word(dev, reg, drv_ctrl);
e93df705 SS	100	pci_read_config_word (dev, reg, &drv_ctrl);
1da177e4	101	}
e93df705 SS	102
	103	printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
	104	ide_xfer_verbose(pio + XFER_PIO_0), p.cycle_time, drv_ctrl);
	105
	106	return pio;
1da177e4 LT	107	}
1da177e4 LT	108
46cedc9b SS	109	/*
	110	* Configure the drive and chipset for a new transfer speed.
	111	*/
	112	static int sl82c105_tune_chipset(ide_drive_t *drive, u8 speed)
	113	{
	114	static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
	115	u16 drv_ctrl;
	116
	117	DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
	118	drive->name, ide_xfer_verbose(speed)));
	119
	120	speed = ide_rate_filter(drive, speed);
	121
	122	switch (speed) {
	123	case XFER_MW_DMA_2:
	124	case XFER_MW_DMA_1:
	125	case XFER_MW_DMA_0:
	126	drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
	127
	128	/*
	129	* Store the DMA timings so that we can actually program
	130	* them when DMA will be turned on...
	131	*/
	132	drive->drive_data &= 0x0000ffff;
	133	drive->drive_data \|= (unsigned long)drv_ctrl << 16;
	134
	135	/*
	136	* If we are already using DMA, we just reprogram
	137	* the drive control register.
	138	*/
	139	if (drive->using_dma) {
	140	struct pci_dev *dev = HWIF(drive)->pci_dev;
	141	int reg = 0x44 + drive->dn * 4;
	142
	143	pci_write_config_word(dev, reg, drv_ctrl);
	144	}
	145	break;
	146	case XFER_PIO_5:
	147	case XFER_PIO_4:
	148	case XFER_PIO_3:
	149	case XFER_PIO_2:
	150	case XFER_PIO_1:
	151	case XFER_PIO_0:
	152	(void) sl82c105_tune_pio(drive, speed - XFER_PIO_0);
	153	break;
	154	default:
	155	return -1;
	156	}
	157
	158	return ide_config_drive_speed(drive, speed);
	159	}
	160
1da177e4	161	/*
688a87d1	162	* Check to see if the drive and chipset are capable of DMA mode.
1da177e4	163	*/
688a87d1	164	static int sl82c105_ide_dma_check(ide_drive_t *drive)
1da177e4	165	{
688a87d1	166	DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive->name));
1da177e4	167
4728d546	168	if (ide_tune_dma(drive))
688a87d1	169	return 0;
1da177e4	170
3608b5d7	171	return -1;
1da177e4 LT	172	}
	173
	174	/*
	175	* The SL82C105 holds off all IDE interrupts while in DMA mode until
	176	* all DMA activity is completed. Sometimes this causes problems (eg,
	177	* when the drive wants to report an error condition).
	178	*
	179	* 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
	180	* state machine. We need to kick this to work around various bugs.
	181	*/
	182	static inline void sl82c105_reset_host(struct pci_dev *dev)
	183	{
	184	u16 val;
	185
	186	pci_read_config_word(dev, 0x7e, &val);
	187	pci_write_config_word(dev, 0x7e, val \| (1 << 2));
	188	pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
	189	}
	190
	191	/*
	192	* If we get an IRQ timeout, it might be that the DMA state machine
	193	* got confused. Fix from Todd Inglett. Details from Winbond.
	194	*
	195	* This function is called when the IDE timer expires, the drive
	196	* indicates that it is READY, and we were waiting for DMA to complete.
	197	*/
841d2a9b	198	static void sl82c105_dma_lost_irq(ide_drive_t *drive)
1da177e4	199	{
688a87d1 SS	200	ide_hwif_t *hwif = HWIF(drive);
	201	struct pci_dev *dev = hwif->pci_dev;
	202	u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
	203	u8 dma_cmd;
1da177e4	204
688a87d1	205	printk("sl82c105: lost IRQ, resetting host\n");
1da177e4 LT	206
	207	/*
	208	* Check the raw interrupt from the drive.
	209	*/
	210	pci_read_config_dword(dev, 0x40, &val);
	211	if (val & mask)
	212	printk("sl82c105: drive was requesting IRQ, but host lost it\n");
	213
	214	/*
	215	* Was DMA enabled? If so, disable it - we're resetting the
	216	* host. The IDE layer will be handling the drive for us.
	217	*/
688a87d1 SS	218	dma_cmd = inb(hwif->dma_command);
	219	if (dma_cmd & 1) {
	220	outb(dma_cmd & ~1, hwif->dma_command);
1da177e4 LT	221	printk("sl82c105: DMA was enabled\n");
	222	}
	223
	224	sl82c105_reset_host(dev);
1da177e4 LT	225	}
	226
	227	/*
	228	* ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
	229	* Winbond recommend that the DMA state machine is reset prior to
	230	* setting the bus master DMA enable bit.
	231	*
	232	* The generic IDE core will have disabled the BMEN bit before this
	233	* function is called.
	234	*/
688a87d1	235	static void sl82c105_dma_start(ide_drive_t *drive)
1da177e4	236	{
688a87d1 SS	237	ide_hwif_t *hwif = HWIF(drive);
688a87d1 SS	238	struct pci_dev *dev = hwif->pci_dev;
1da177e4 LT	239
	240	sl82c105_reset_host(dev);
	241	ide_dma_start(drive);
	242	}
	243
c283f5db	244	static void sl82c105_dma_timeout(ide_drive_t *drive)
1da177e4	245	{
c283f5db	246	DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name));
1da177e4	247
c283f5db SS	248	sl82c105_reset_host(HWIF(drive)->pci_dev);
c283f5db SS	249	ide_dma_timeout(drive);
1da177e4 LT	250	}
1da177e4 LT	251
688a87d1	252	static int sl82c105_ide_dma_on(ide_drive_t *drive)
1da177e4	253	{
688a87d1 SS	254	struct pci_dev *dev = HWIF(drive)->pci_dev;
	255	int rc, reg = 0x44 + drive->dn * 4;
	256
1da177e4 LT	257	DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
1da177e4 LT	258
688a87d1 SS	259	rc = __ide_dma_on(drive);
688a87d1 SS	260	if (rc == 0) {
46cedc9b	261	pci_write_config_word(dev, reg, drive->drive_data >> 16);
688a87d1 SS	262
	263	printk(KERN_INFO "%s: DMA enabled\n", drive->name);
	264	}
	265	return rc;
1da177e4 LT	266	}
1da177e4 LT	267
7469aaf6	268	static void sl82c105_dma_off_quietly(ide_drive_t *drive)
1da177e4	269	{
e93df705 SS	270	struct pci_dev *dev = HWIF(drive)->pci_dev;
e93df705 SS	271	int reg = 0x44 + drive->dn * 4;
1da177e4	272
7469aaf6 BZ	273	DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));
7469aaf6 BZ	274
e93df705 SS	275	pci_write_config_word(dev, reg, drive->drive_data);
e93df705 SS	276
7469aaf6	277	ide_dma_off_quietly(drive);
1da177e4 LT	278	}
	279
	280	/*
	281	* Ok, that is nasty, but we must make sure the DMA timings
	282	* won't be used for a PIO access. The solution here is
	283	* to make sure the 16 bits mode is diabled on the channel
	284	* when DMA is enabled, thus causing the chip to use PIO0
	285	* timings for those operations.
	286	*/
	287	static void sl82c105_selectproc(ide_drive_t *drive)
	288	{
688a87d1 SS	289	ide_hwif_t *hwif = HWIF(drive);
688a87d1 SS	290	struct pci_dev *dev = hwif->pci_dev;
1da177e4 LT	291	u32 val, old, mask;
	292
	293	//DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
	294
	295	mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
dd607d23	296	old = val = (u32)pci_get_drvdata(dev);
1da177e4 LT	297	if (drive->using_dma)
	298	val &= ~mask;
	299	else
	300	val \|= mask;
	301	if (old != val) {
	302	pci_write_config_dword(dev, 0x40, val);
dd607d23	303	pci_set_drvdata(dev, (void *)val);
1da177e4 LT	304	}
	305	}
	306
	307	/*
	308	* ATA reset will clear the 16 bits mode in the control
	309	* register, we need to update our cache
	310	*/
	311	static void sl82c105_resetproc(ide_drive_t *drive)
	312	{
dd607d23	313	struct pci_dev *dev = HWIF(drive)->pci_dev;
1da177e4 LT	314	u32 val;
	315
	316	DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
	317
	318	pci_read_config_dword(dev, 0x40, &val);
dd607d23	319	pci_set_drvdata(dev, (void *)val);
1da177e4 LT	320	}
	321
	322	/*
	323	* We only deal with PIO mode here - DMA mode 'using_dma' is not
	324	* initialised at the point that this function is called.
	325	*/
e93df705	326	static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio)
1da177e4	327	{
e93df705	328	DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive->name, pio));
1da177e4	329
e93df705 SS	330	pio = sl82c105_tune_pio(drive, pio);
e93df705 SS	331	(void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
1da177e4 LT	332	}
	333
	334	/*
	335	* Return the revision of the Winbond bridge
	336	* which this function is part of.
	337	*/
	338	static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
	339	{
	340	struct pci_dev *bridge;
1da177e4 LT	341
	342	/*
	343	* The bridge should be part of the same device, but function 0.
	344	*/
640b31bf	345	bridge = pci_get_bus_and_slot(dev->bus->number,
1da177e4 LT	346	PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
	347	if (!bridge)
	348	return -1;
	349
	350	/*
	351	* Make sure it is a Winbond 553 and is an ISA bridge.
	352	*/
	353	if (bridge->vendor != PCI_VENDOR_ID_WINBOND \|\|
	354	bridge->device != PCI_DEVICE_ID_WINBOND_83C553 \|\|
640b31bf AC	355	bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
640b31bf AC	356	pci_dev_put(bridge);
1da177e4	357	return -1;
640b31bf	358	}
1da177e4 LT	359	/*
	360	* We need to find function 0's revision, not function 1
	361	*/
640b31bf	362	pci_dev_put(bridge);
1da177e4	363
44c10138	364	return bridge->revision;
1da177e4 LT	365	}
	366
	367	/*
	368	* Enable the PCI device
	369	*
	370	* --BenH: It's arch fixup code that should enable channels that
	371	* have not been enabled by firmware. I decided we can still enable
	372	* channel 0 here at least, but channel 1 has to be enabled by
	373	* firmware or arch code. We still set both to 16 bits mode.
	374	*/
34a62246	375	static unsigned int __devinit init_chipset_sl82c105(struct pci_dev dev, const char msg)
1da177e4 LT	376	{
	377	u32 val;
	378
	379	DBG(("init_chipset_sl82c105()\n"));
	380
	381	pci_read_config_dword(dev, 0x40, &val);
	382	val \|= CTRL_P0EN \| CTRL_P0F16 \| CTRL_P1F16;
	383	pci_write_config_dword(dev, 0x40, val);
dd607d23	384	pci_set_drvdata(dev, (void *)val);
1da177e4 LT	385
	386	return dev->irq;
	387	}
	388
1da177e4	389	/*
688a87d1	390	* Initialise IDE channel
1da177e4	391	*/
34a62246	392	static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
1da177e4	393	{
9648f552	394	unsigned int rev;
dd607d23	395
1da177e4 LT	396	DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
1da177e4 LT	397
e93df705	398	hwif->tuneproc = &sl82c105_tune_drive;
46cedc9b	399	hwif->speedproc = &sl82c105_tune_chipset;
e93df705 SS	400	hwif->selectproc = &sl82c105_selectproc;
	401	hwif->resetproc = &sl82c105_resetproc;
	402
	403	/*
	404	* We support 32-bit I/O on this interface, and
	405	* it doesn't have problems with interrupts.
	406	*/
	407	hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1;
	408	hwif->drives[0].unmask = hwif->drives[1].unmask = 1;
dd607d23 SS	409
dd607d23 SS	410	/*
dd607d23 SS	411	* We always autotune PIO, this is done before DMA is checked,
	412	* so there's no risk of accidentally disabling DMA
	413	*/
e93df705	414	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1da177e4	415
1da177e4 LT	416	if (!hwif->dma_base)
	417	return;
	418
9648f552 RK	419	rev = sl82c105_bridge_revision(hwif->pci_dev);
	420	if (rev <= 5) {
	421	/*
	422	* Never ever EVER under any circumstances enable
	423	* DMA when the bridge is this old.
	424	*/
688a87d1 SS	425	printk(" %s: Winbond W83C553 bridge revision %d, "
	426	"BM-DMA disabled\n", hwif->name, rev);
	427	return;
9648f552	428	}
688a87d1 SS	429
688a87d1 SS	430	hwif->atapi_dma = 1;
46cedc9b	431	hwif->mwdma_mask = 0x07;
688a87d1 SS	432
	433	hwif->ide_dma_check = &sl82c105_ide_dma_check;
	434	hwif->ide_dma_on = &sl82c105_ide_dma_on;
	435	hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
841d2a9b	436	hwif->dma_lost_irq = &sl82c105_dma_lost_irq;
688a87d1	437	hwif->dma_start = &sl82c105_dma_start;
c283f5db	438	hwif->dma_timeout = &sl82c105_dma_timeout;
688a87d1 SS	439
	440	if (!noautodma)
	441	hwif->autodma = 1;
	442	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
	443
	444	if (hwif->mate)
	445	hwif->serialized = hwif->mate->serialized = 1;
1da177e4 LT	446	}
	447
	448	static ide_pci_device_t sl82c105_chipset __devinitdata = {
	449	.name = "W82C105",
	450	.init_chipset = init_chipset_sl82c105,
	451	.init_hwif = init_hwif_sl82c105,
1da177e4 LT	452	.channels = 2,
	453	.autodma = NOAUTODMA,
	454	.enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
	455	.bootable = ON_BOARD,
	456	};
	457
	458	static int __devinit sl82c105_init_one(struct pci_dev dev, const struct pci_device_id id)
	459	{
	460	return ide_setup_pci_device(dev, &sl82c105_chipset);
	461	}
	462
	463	static struct pci_device_id sl82c105_pci_tbl[] = {
f201f504	464	{ PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0},
1da177e4 LT	465	{ 0, },
	466	};
	467	MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
	468
	469	static struct pci_driver driver = {
	470	.name = "W82C105_IDE",
	471	.id_table = sl82c105_pci_tbl,
	472	.probe = sl82c105_init_one,
	473	};
	474
82ab1eec	475	static int __init sl82c105_ide_init(void)
1da177e4 LT	476	{
	477	return ide_pci_register_driver(&driver);
	478	}
	479
	480	module_init(sl82c105_ide_init);
	481
	482	MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
	483	MODULE_LICENSE("GPL");