[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ide / pci / sl82c105.c

/*
 * linux/drivers/ide/pci/sl82c105.c
 *
 * SL82C105/Winbond 553 IDE driver
 *
 * Maintainer unknown.
 *
 * Drive tuning added from Rebel.com's kernel sources
 *  -- Russell King (15/11/98) linux@arm.linux.org.uk
 * 
 * Merge in Russell's HW workarounds, fix various problems
 * with the timing registers setup.
 *  -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/dma.h>

#undef DEBUG

#ifdef DEBUG
#define DBG(arg) printk arg
#else
#define DBG(fmt,...)
#endif
/*
 * SL82C105 PCI config register 0x40 bits.
 */
#define CTRL_IDE_IRQB   (1 << 30)
#define CTRL_IDE_IRQA   (1 << 28)
#define CTRL_LEGIRQ     (1 << 11)
#define CTRL_P1F16      (1 << 5)
#define CTRL_P1EN       (1 << 4)
#define CTRL_P0F16      (1 << 1)
#define CTRL_P0EN       (1 << 0)

/*
 * Convert a PIO mode and cycle time to the required on/off
 * times for the interface.  This has protection against run-away
 * timings.
 */
static unsigned int get_timing_sl82c105(ide_pio_data_t *p)
{
	unsigned int cmd_on;
	unsigned int cmd_off;

	cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
	cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30;

	if (cmd_on > 32)
		cmd_on = 32;
	if (cmd_on == 0)
		cmd_on = 1;

	if (cmd_off > 32)
		cmd_off = 32;
	if (cmd_off == 0)
		cmd_off = 1;

	return (cmd_on - 1) << 8 | (cmd_off - 1) | (p->use_iordy ? 0x40 : 0x00);
}

/*
 * Configure the drive and chipset for PIO
 */
static void config_for_pio(ide_drive_t *drive, int pio, int report, int chipset_only)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *dev = hwif->pci_dev;
	ide_pio_data_t p;
	u16 drv_ctrl = 0x909;
	unsigned int xfer_mode, reg;

	DBG(("config_for_pio(drive:%s, pio:%d, report:%d, chipset_only:%d)\n",
		drive->name, pio, report, chipset_only));
		
	reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);

	pio = ide_get_best_pio_mode(drive, pio, 5, &p);

	xfer_mode = XFER_PIO_0 + pio;

	if (chipset_only || ide_config_drive_speed(drive, xfer_mode) == 0) {
		drv_ctrl = get_timing_sl82c105(&p);
		drive->pio_speed = xfer_mode;
	} else
		drive->pio_speed = XFER_PIO_0;

	if (drive->using_dma == 0) {
		/*
		 * If we are actually using MW DMA, then we can not
		 * reprogram the interface drive control register.
		 */
		pci_write_config_word(dev, reg, drv_ctrl);
		pci_read_config_word(dev, reg, &drv_ctrl);

		if (report) {
			printk("%s: selected %s (%dns) (%04X)\n", drive->name,
			       ide_xfer_verbose(xfer_mode), p.cycle_time, drv_ctrl);
		}
	}
}

/*
 * Configure the drive and the chipset for DMA
 */
static int config_for_dma (ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *dev = hwif->pci_dev;
	unsigned int reg;

	DBG(("config_for_dma(drive:%s)\n", drive->name));

	reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);

	if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0)
		return 1;

	pci_write_config_word(dev, reg, 0x0240);

	return 0;
}

/*
 * Check to see if the drive and
 * chipset is capable of DMA mode
 */

static int sl82c105_check_drive (ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);

	DBG(("sl82c105_check_drive(drive:%s)\n", drive->name));

	do {
		struct hd_driveid *id = drive->id;

		if (!drive->autodma)
			break;

		if (!id || !(id->capability & 1))
			break;

		/* Consult the list of known "bad" drives */
		if (__ide_dma_bad_drive(drive))
			break;

		if (id->field_valid & 2) {
			if ((id->dma_mword & hwif->mwdma_mask) ||
			    (id->dma_1word & hwif->swdma_mask))
				return 0;
		}

		if (__ide_dma_good_drive(drive) && id->eide_dma_time < 150)
			return 0;
	} while (0);

	return -1;
}

/*
 * The SL82C105 holds off all IDE interrupts while in DMA mode until
 * all DMA activity is completed.  Sometimes this causes problems (eg,
 * when the drive wants to report an error condition).
 *
 * 0x7e is a "chip testing" register.  Bit 2 resets the DMA controller
 * state machine.  We need to kick this to work around various bugs.
 */
static inline void sl82c105_reset_host(struct pci_dev *dev)
{
	u16 val;

	pci_read_config_word(dev, 0x7e, &val);
	pci_write_config_word(dev, 0x7e, val | (1 << 2));
	pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
}

/*
 * If we get an IRQ timeout, it might be that the DMA state machine
 * got confused.  Fix from Todd Inglett.  Details from Winbond.
 *
 * This function is called when the IDE timer expires, the drive
 * indicates that it is READY, and we were waiting for DMA to complete.
 */
static int sl82c105_ide_dma_lost_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *dev = hwif->pci_dev;
	u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
	unsigned long dma_base = hwif->dma_base;

	printk("sl82c105: lost IRQ: resetting host\n");

	/*
	 * Check the raw interrupt from the drive.
	 */
	pci_read_config_dword(dev, 0x40, &val);
	if (val & mask)
		printk("sl82c105: drive was requesting IRQ, but host lost it\n");

	/*
	 * Was DMA enabled?  If so, disable it - we're resetting the
	 * host.  The IDE layer will be handling the drive for us.
	 */
	val = inb(dma_base);
	if (val & 1) {
		outb(val & ~1, dma_base);
		printk("sl82c105: DMA was enabled\n");
	}

	sl82c105_reset_host(dev);

	/* ide_dmaproc would return 1, so we do as well */
	return 1;
}

/*
 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
 * Winbond recommend that the DMA state machine is reset prior to
 * setting the bus master DMA enable bit.
 *
 * The generic IDE core will have disabled the BMEN bit before this
 * function is called.
 */
static void sl82c105_ide_dma_start(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *dev = hwif->pci_dev;

	sl82c105_reset_host(dev);
	ide_dma_start(drive);
}

static int sl82c105_ide_dma_timeout(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *dev = hwif->pci_dev;

	DBG(("sl82c105_ide_dma_timeout(drive:%s)\n", drive->name));

	sl82c105_reset_host(dev);
	return __ide_dma_timeout(drive);
}

static int sl82c105_ide_dma_on (ide_drive_t *drive)
{
	DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));

	if (config_for_dma(drive))
		return 1;
	printk(KERN_INFO "%s: DMA enabled\n", drive->name);
	return __ide_dma_on(drive);
}

static int sl82c105_ide_dma_off_quietly (ide_drive_t *drive)
{
	u8 speed = XFER_PIO_0;
	int rc;
	
	DBG(("sl82c105_ide_dma_off_quietly(drive:%s)\n", drive->name));

	rc = __ide_dma_off_quietly(drive);
	if (drive->pio_speed)
		speed = drive->pio_speed - XFER_PIO_0;
	config_for_pio(drive, speed, 0, 1);

	return rc;
}

/*
 * Ok, that is nasty, but we must make sure the DMA timings
 * won't be used for a PIO access. The solution here is
 * to make sure the 16 bits mode is diabled on the channel
 * when DMA is enabled, thus causing the chip to use PIO0
 * timings for those operations.
 */
static void sl82c105_selectproc(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *dev = hwif->pci_dev;
	u32 val, old, mask;

	//DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));

	mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
	old = val = (u32)pci_get_drvdata(dev);
	if (drive->using_dma)
		val &= ~mask;
	else
		val |= mask;
	if (old != val) {
		pci_write_config_dword(dev, 0x40, val);	
		pci_set_drvdata(dev, (void *)val);
	}
}

/*
 * ATA reset will clear the 16 bits mode in the control
 * register, we need to update our cache
 */
static void sl82c105_resetproc(ide_drive_t *drive)
{
	struct pci_dev *dev = HWIF(drive)->pci_dev;
	u32 val;

	DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));

	pci_read_config_dword(dev, 0x40, &val);
	pci_set_drvdata(dev, (void *)val);
}
	
/*
 * We only deal with PIO mode here - DMA mode 'using_dma' is not
 * initialised at the point that this function is called.
 */
static void tune_sl82c105(ide_drive_t *drive, u8 pio)
{
	DBG(("tune_sl82c105(drive:%s)\n", drive->name));

	config_for_pio(drive, pio, 1, 0);

	/*
	 * We support 32-bit I/O on this interface, and it
	 * doesn't have problems with interrupts.
	 */
	drive->io_32bit = 1;
	drive->unmask = 1;
}

/*
 * Return the revision of the Winbond bridge
 * which this function is part of.
 */
static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
{
	struct pci_dev *bridge;
	u8 rev;

	/*
	 * The bridge should be part of the same device, but function 0.
	 */
	bridge = pci_find_slot(dev->bus->number,
			       PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
	if (!bridge)
		return -1;

	/*
	 * Make sure it is a Winbond 553 and is an ISA bridge.
	 */
	if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
	    bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
	    bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA)
		return -1;

	/*
	 * We need to find function 0's revision, not function 1
	 */
	pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);

	return rev;
}

/*
 * Enable the PCI device
 * 
 * --BenH: It's arch fixup code that should enable channels that
 * have not been enabled by firmware. I decided we can still enable
 * channel 0 here at least, but channel 1 has to be enabled by
 * firmware or arch code. We still set both to 16 bits mode.
 */
static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
{
	u32 val;

	DBG(("init_chipset_sl82c105()\n"));

	pci_read_config_dword(dev, 0x40, &val);
	val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
	pci_write_config_dword(dev, 0x40, val);
	pci_set_drvdata(dev, (void *)val);

	return dev->irq;
}

/*
 * Initialise the chip
 */
static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
{
	unsigned int rev;

	DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));

	hwif->tuneproc = tune_sl82c105;
	hwif->selectproc = sl82c105_selectproc;
	hwif->resetproc = sl82c105_resetproc;

	/*
	 * Default to PIO 0 for fallback unless tuned otherwise.
	 * We always autotune PIO,  this is done before DMA is checked,
	 * so there's no risk of accidentally disabling DMA
	 */
	hwif->drives[0].pio_speed = XFER_PIO_0;
	hwif->drives[0].autotune = 1;
	hwif->drives[1].pio_speed = XFER_PIO_0;
	hwif->drives[1].autotune = 1;

	hwif->atapi_dma = 0;
	hwif->mwdma_mask = 0;
	hwif->swdma_mask = 0;
	hwif->autodma = 0;

	if (!hwif->dma_base)
		return;

	rev = sl82c105_bridge_revision(hwif->pci_dev);
	if (rev <= 5) {
		/*
		 * Never ever EVER under any circumstances enable
		 * DMA when the bridge is this old.
		 */
		printk("    %s: Winbond 553 bridge revision %d, BM-DMA disabled\n",
		       hwif->name, rev);
	} else {
		hwif->atapi_dma = 1;
		hwif->mwdma_mask = 0x04;

		hwif->ide_dma_check = &sl82c105_check_drive;
		hwif->ide_dma_on = &sl82c105_ide_dma_on;
		hwif->ide_dma_off_quietly = &sl82c105_ide_dma_off_quietly;
		hwif->ide_dma_lostirq = &sl82c105_ide_dma_lost_irq;
		hwif->dma_start = &sl82c105_ide_dma_start;
		hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout;

		if (!noautodma)
			hwif->autodma = 1;
		hwif->drives[0].autodma = hwif->autodma;
		hwif->drives[1].autodma = hwif->autodma;

		if (hwif->mate)
			hwif->serialized = hwif->mate->serialized = 1;
	}
}

static ide_pci_device_t sl82c105_chipset __devinitdata = {
	.name		= "W82C105",
	.init_chipset	= init_chipset_sl82c105,
	.init_hwif	= init_hwif_sl82c105,
	.channels	= 2,
	.autodma	= NOAUTODMA,
	.enablebits	= {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
	.bootable	= ON_BOARD,
};

static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &sl82c105_chipset);
}

static struct pci_device_id sl82c105_pci_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);

static struct pci_driver driver = {
	.name		= "W82C105_IDE",
	.id_table	= sl82c105_pci_tbl,
	.probe		= sl82c105_init_one,
};

static int __init sl82c105_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(sl82c105_ide_init);

MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/ide/pci/sl82c105.c
	3	*
	4	* SL82C105/Winbond 553 IDE driver
	5	*
	6	* Maintainer unknown.
	7	*
	8	* Drive tuning added from Rebel.com's kernel sources
	9	* -- Russell King (15/11/98) linux@arm.linux.org.uk
	10	*
	11	* Merge in Russell's HW workarounds, fix various problems
	12	* with the timing registers setup.
	13	* -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
	14	*/
	15
1da177e4 LT	16	#include <linux/types.h>
	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/timer.h>
	20	#include <linux/mm.h>
	21	#include <linux/ioport.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/blkdev.h>
	24	#include <linux/hdreg.h>
	25	#include <linux/pci.h>
	26	#include <linux/ide.h>
	27
	28	#include <asm/io.h>
	29	#include <asm/dma.h>
	30
	31	#undef DEBUG
	32
	33	#ifdef DEBUG
	34	#define DBG(arg) printk arg
	35	#else
	36	#define DBG(fmt,...)
	37	#endif
	38	/*
	39	* SL82C105 PCI config register 0x40 bits.
	40	*/
	41	#define CTRL_IDE_IRQB (1 << 30)
	42	#define CTRL_IDE_IRQA (1 << 28)
	43	#define CTRL_LEGIRQ (1 << 11)
	44	#define CTRL_P1F16 (1 << 5)
	45	#define CTRL_P1EN (1 << 4)
	46	#define CTRL_P0F16 (1 << 1)
	47	#define CTRL_P0EN (1 << 0)
	48
	49	/*
	50	* Convert a PIO mode and cycle time to the required on/off
	51	* times for the interface. This has protection against run-away
	52	* timings.
	53	*/
	54	static unsigned int get_timing_sl82c105(ide_pio_data_t *p)
	55	{
	56	unsigned int cmd_on;
	57	unsigned int cmd_off;
	58
	59	cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
	60	cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30;
	61
	62	if (cmd_on > 32)
	63	cmd_on = 32;
	64	if (cmd_on == 0)
	65	cmd_on = 1;
	66
	67	if (cmd_off > 32)
	68	cmd_off = 32;
	69	if (cmd_off == 0)
	70	cmd_off = 1;
	71
	72	return (cmd_on - 1) << 8 \| (cmd_off - 1) \| (p->use_iordy ? 0x40 : 0x00);
	73	}
	74
	75	/*
	76	* Configure the drive and chipset for PIO
	77	*/
	78	static void config_for_pio(ide_drive_t *drive, int pio, int report, int chipset_only)
	79	{
80	ide_hwif_t *hwif = HWIF(drive);
81	struct pci_dev *dev = hwif->pci_dev;
82	ide_pio_data_t p;
83	u16 drv_ctrl = 0x909;
84	unsigned int xfer_mode, reg;
85
86	DBG(("config_for_pio(drive:%s, pio:%d, report:%d, chipset_only:%d)\n",
87	drive->name, pio, report, chipset_only));
88
89	reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
90
91	pio = ide_get_best_pio_mode(drive, pio, 5, &p);
92
93	xfer_mode = XFER_PIO_0 + pio;
94
95	if (chipset_only \|\| ide_config_drive_speed(drive, xfer_mode) == 0) {
96	drv_ctrl = get_timing_sl82c105(&p);
97	drive->pio_speed = xfer_mode;
98	} else
99	drive->pio_speed = XFER_PIO_0;
100
101	if (drive->using_dma == 0) {
102	/*
103	* If we are actually using MW DMA, then we can not
104	* reprogram the interface drive control register.
105	*/
106	pci_write_config_word(dev, reg, drv_ctrl);
107	pci_read_config_word(dev, reg, &drv_ctrl);
108
109	if (report) {
110	printk("%s: selected %s (%dns) (%04X)\n", drive->name,
111	ide_xfer_verbose(xfer_mode), p.cycle_time, drv_ctrl);
112	}
113	}
114	}
115
116	/*
117	* Configure the drive and the chipset for DMA
118	*/
119	static int config_for_dma (ide_drive_t *drive)
120	{
121	ide_hwif_t *hwif = HWIF(drive);
122	struct pci_dev *dev = hwif->pci_dev;
123	unsigned int reg;
124
125	DBG(("config_for_dma(drive:%s)\n", drive->name));
126
127	reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
128
129	if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0)
130	return 1;
131
132	pci_write_config_word(dev, reg, 0x0240);
133
134	return 0;
135	}
136
137	/*
138	* Check to see if the drive and
139	* chipset is capable of DMA mode
140	*/
141
142	static int sl82c105_check_drive (ide_drive_t *drive)
143	{
144	ide_hwif_t *hwif = HWIF(drive);
145
146	DBG(("sl82c105_check_drive(drive:%s)\n", drive->name));
147
148	do {
149	struct hd_driveid *id = drive->id;
150
151	if (!drive->autodma)
152	break;
153
154	if (!id \|\| !(id->capability & 1))
155	break;
156
157	/* Consult the list of known "bad" drives */
158	if (__ide_dma_bad_drive(drive))
159	break;
160
161	if (id->field_valid & 2) {
162	if ((id->dma_mword & hwif->mwdma_mask) \|\|
163	(id->dma_1word & hwif->swdma_mask))
3608b5d7	164	return 0;
1da177e4 LT	165	}
1da177e4 LT	166
ea266ba1	167	if (__ide_dma_good_drive(drive) && id->eide_dma_time < 150)
3608b5d7	168	return 0;
1da177e4 LT	169	} while (0);
1da177e4 LT	170
3608b5d7	171	return -1;
1da177e4 LT	172	}
	173
	174	/*
	175	* The SL82C105 holds off all IDE interrupts while in DMA mode until
	176	* all DMA activity is completed. Sometimes this causes problems (eg,
	177	* when the drive wants to report an error condition).
	178	*
	179	* 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
	180	* state machine. We need to kick this to work around various bugs.
	181	*/
	182	static inline void sl82c105_reset_host(struct pci_dev *dev)
	183	{
	184	u16 val;
	185
	186	pci_read_config_word(dev, 0x7e, &val);
	187	pci_write_config_word(dev, 0x7e, val \| (1 << 2));
	188	pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
	189	}
	190
	191	/*
	192	* If we get an IRQ timeout, it might be that the DMA state machine
	193	* got confused. Fix from Todd Inglett. Details from Winbond.
	194	*
	195	* This function is called when the IDE timer expires, the drive
	196	* indicates that it is READY, and we were waiting for DMA to complete.
	197	*/
	198	static int sl82c105_ide_dma_lost_irq(ide_drive_t *drive)
	199	{
	200	ide_hwif_t *hwif = HWIF(drive);
	201	struct pci_dev *dev = hwif->pci_dev;
	202	u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
	203	unsigned long dma_base = hwif->dma_base;
	204
	205	printk("sl82c105: lost IRQ: resetting host\n");
	206
	207	/*
	208	* Check the raw interrupt from the drive.
	209	*/
	210	pci_read_config_dword(dev, 0x40, &val);
	211	if (val & mask)
	212	printk("sl82c105: drive was requesting IRQ, but host lost it\n");
	213
	214	/*
	215	* Was DMA enabled? If so, disable it - we're resetting the
	216	* host. The IDE layer will be handling the drive for us.
	217	*/
0ecdca26	218	val = inb(dma_base);
1da177e4 LT	219	if (val & 1) {
	220	outb(val & ~1, dma_base);
	221	printk("sl82c105: DMA was enabled\n");
	222	}
	223
	224	sl82c105_reset_host(dev);
	225
	226	/* ide_dmaproc would return 1, so we do as well */
	227	return 1;
	228	}
	229
	230	/*
	231	* ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
	232	* Winbond recommend that the DMA state machine is reset prior to
	233	* setting the bus master DMA enable bit.
	234	*
	235	* The generic IDE core will have disabled the BMEN bit before this
	236	* function is called.
	237	*/
	238	static void sl82c105_ide_dma_start(ide_drive_t *drive)
	239	{
	240	ide_hwif_t *hwif = HWIF(drive);
	241	struct pci_dev *dev = hwif->pci_dev;
	242
	243	sl82c105_reset_host(dev);
	244	ide_dma_start(drive);
	245	}
	246
	247	static int sl82c105_ide_dma_timeout(ide_drive_t *drive)
	248	{
	249	ide_hwif_t *hwif = HWIF(drive);
	250	struct pci_dev *dev = hwif->pci_dev;
	251
	252	DBG(("sl82c105_ide_dma_timeout(drive:%s)\n", drive->name));
	253
	254	sl82c105_reset_host(dev);
	255	return __ide_dma_timeout(drive);
	256	}
	257
	258	static int sl82c105_ide_dma_on (ide_drive_t *drive)
	259	{
	260	DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
	261
ea266ba1 SS	262	if (config_for_dma(drive))
ea266ba1 SS	263	return 1;
1da177e4 LT	264	printk(KERN_INFO "%s: DMA enabled\n", drive->name);
	265	return __ide_dma_on(drive);
	266	}
	267
	268	static int sl82c105_ide_dma_off_quietly (ide_drive_t *drive)
	269	{
	270	u8 speed = XFER_PIO_0;
	271	int rc;
	272
	273	DBG(("sl82c105_ide_dma_off_quietly(drive:%s)\n", drive->name));
	274
	275	rc = __ide_dma_off_quietly(drive);
	276	if (drive->pio_speed)
	277	speed = drive->pio_speed - XFER_PIO_0;
	278	config_for_pio(drive, speed, 0, 1);
1da177e4 LT	279
	280	return rc;
	281	}
	282
	283	/*
	284	* Ok, that is nasty, but we must make sure the DMA timings
	285	* won't be used for a PIO access. The solution here is
	286	* to make sure the 16 bits mode is diabled on the channel
	287	* when DMA is enabled, thus causing the chip to use PIO0
	288	* timings for those operations.
	289	*/
	290	static void sl82c105_selectproc(ide_drive_t *drive)
	291	{
	292	ide_hwif_t *hwif = HWIF(drive);
	293	struct pci_dev *dev = hwif->pci_dev;
	294	u32 val, old, mask;
	295
	296	//DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
	297
	298	mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
dd607d23	299	old = val = (u32)pci_get_drvdata(dev);
1da177e4 LT	300	if (drive->using_dma)
	301	val &= ~mask;
	302	else
	303	val \|= mask;
	304	if (old != val) {
	305	pci_write_config_dword(dev, 0x40, val);
dd607d23	306	pci_set_drvdata(dev, (void *)val);
1da177e4 LT	307	}
	308	}
	309
	310	/*
	311	* ATA reset will clear the 16 bits mode in the control
	312	* register, we need to update our cache
	313	*/
	314	static void sl82c105_resetproc(ide_drive_t *drive)
	315	{
dd607d23	316	struct pci_dev *dev = HWIF(drive)->pci_dev;
1da177e4 LT	317	u32 val;
	318
	319	DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
	320
	321	pci_read_config_dword(dev, 0x40, &val);
dd607d23	322	pci_set_drvdata(dev, (void *)val);
1da177e4 LT	323	}
	324
	325	/*
	326	* We only deal with PIO mode here - DMA mode 'using_dma' is not
	327	* initialised at the point that this function is called.
	328	*/
	329	static void tune_sl82c105(ide_drive_t *drive, u8 pio)
	330	{
	331	DBG(("tune_sl82c105(drive:%s)\n", drive->name));
	332
	333	config_for_pio(drive, pio, 1, 0);
	334
	335	/*
	336	* We support 32-bit I/O on this interface, and it
	337	* doesn't have problems with interrupts.
	338	*/
	339	drive->io_32bit = 1;
	340	drive->unmask = 1;
	341	}
	342
	343	/*
	344	* Return the revision of the Winbond bridge
	345	* which this function is part of.
	346	*/
	347	static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
	348	{
	349	struct pci_dev *bridge;
	350	u8 rev;
	351
	352	/*
	353	* The bridge should be part of the same device, but function 0.
	354	*/
	355	bridge = pci_find_slot(dev->bus->number,
	356	PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
	357	if (!bridge)
	358	return -1;
	359
	360	/*
	361	* Make sure it is a Winbond 553 and is an ISA bridge.
	362	*/
	363	if (bridge->vendor != PCI_VENDOR_ID_WINBOND \|\|
	364	bridge->device != PCI_DEVICE_ID_WINBOND_83C553 \|\|
	365	bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA)
	366	return -1;
	367
	368	/*
	369	* We need to find function 0's revision, not function 1
	370	*/
	371	pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
	372
	373	return rev;
	374	}
	375
	376	/*
	377	* Enable the PCI device
	378	*
	379	* --BenH: It's arch fixup code that should enable channels that
	380	* have not been enabled by firmware. I decided we can still enable
	381	* channel 0 here at least, but channel 1 has to be enabled by
	382	* firmware or arch code. We still set both to 16 bits mode.
	383	*/
34a62246	384	static unsigned int __devinit init_chipset_sl82c105(struct pci_dev dev, const char msg)
1da177e4 LT	385	{
	386	u32 val;
	387
	388	DBG(("init_chipset_sl82c105()\n"));
	389
	390	pci_read_config_dword(dev, 0x40, &val);
	391	val \|= CTRL_P0EN \| CTRL_P0F16 \| CTRL_P1F16;
	392	pci_write_config_dword(dev, 0x40, val);
dd607d23	393	pci_set_drvdata(dev, (void *)val);
1da177e4 LT	394
	395	return dev->irq;
	396	}
	397
1da177e4 LT	398	/*
	399	* Initialise the chip
	400	*/
34a62246	401	static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
1da177e4	402	{
9648f552	403	unsigned int rev;
dd607d23	404
1da177e4 LT	405	DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
	406
	407	hwif->tuneproc = tune_sl82c105;
	408	hwif->selectproc = sl82c105_selectproc;
	409	hwif->resetproc = sl82c105_resetproc;
dd607d23 SS	410
	411	/*
	412	* Default to PIO 0 for fallback unless tuned otherwise.
	413	* We always autotune PIO, this is done before DMA is checked,
	414	* so there's no risk of accidentally disabling DMA
	415	*/
1da177e4 LT	416	hwif->drives[0].pio_speed = XFER_PIO_0;
1da177e4 LT	417	hwif->drives[0].autotune = 1;
dd607d23	418	hwif->drives[1].pio_speed = XFER_PIO_0;
1da177e4 LT	419	hwif->drives[1].autotune = 1;
1da177e4 LT	420
9648f552 RK	421	hwif->atapi_dma = 0;
	422	hwif->mwdma_mask = 0;
	423	hwif->swdma_mask = 0;
	424	hwif->autodma = 0;
	425
1da177e4 LT	426	if (!hwif->dma_base)
	427	return;
	428
9648f552 RK	429	rev = sl82c105_bridge_revision(hwif->pci_dev);
	430	if (rev <= 5) {
	431	/*
	432	* Never ever EVER under any circumstances enable
	433	* DMA when the bridge is this old.
	434	*/
	435	printk(" %s: Winbond 553 bridge revision %d, BM-DMA disabled\n",
	436	hwif->name, rev);
	437	} else {
9648f552	438	hwif->atapi_dma = 1;
ea266ba1	439	hwif->mwdma_mask = 0x04;
9648f552 RK	440
	441	hwif->ide_dma_check = &sl82c105_check_drive;
	442	hwif->ide_dma_on = &sl82c105_ide_dma_on;
	443	hwif->ide_dma_off_quietly = &sl82c105_ide_dma_off_quietly;
	444	hwif->ide_dma_lostirq = &sl82c105_ide_dma_lost_irq;
	445	hwif->dma_start = &sl82c105_ide_dma_start;
	446	hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout;
	447
	448	if (!noautodma)
	449	hwif->autodma = 1;
	450	hwif->drives[0].autodma = hwif->autodma;
	451	hwif->drives[1].autodma = hwif->autodma;
a1510210 RK	452
	453	if (hwif->mate)
	454	hwif->serialized = hwif->mate->serialized = 1;
9648f552	455	}
1da177e4 LT	456	}
	457
	458	static ide_pci_device_t sl82c105_chipset __devinitdata = {
	459	.name = "W82C105",
	460	.init_chipset = init_chipset_sl82c105,
	461	.init_hwif = init_hwif_sl82c105,
1da177e4 LT	462	.channels = 2,
	463	.autodma = NOAUTODMA,
	464	.enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
	465	.bootable = ON_BOARD,
	466	};
	467
	468	static int __devinit sl82c105_init_one(struct pci_dev dev, const struct pci_device_id id)
	469	{
	470	return ide_setup_pci_device(dev, &sl82c105_chipset);
	471	}
	472
	473	static struct pci_device_id sl82c105_pci_tbl[] = {
f201f504	474	{ PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0},
1da177e4 LT	475	{ 0, },
	476	};
	477	MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
	478
	479	static struct pci_driver driver = {
	480	.name = "W82C105_IDE",
	481	.id_table = sl82c105_pci_tbl,
	482	.probe = sl82c105_init_one,
	483	};
	484
82ab1eec	485	static int __init sl82c105_ide_init(void)
1da177e4 LT	486	{
	487	return ide_pci_register_driver(&driver);
	488	}
	489
	490	module_init(sl82c105_ide_init);
	491
	492	MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
	493	MODULE_LICENSE("GPL");