Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * SL82C105/Winbond 553 IDE driver |
3 | * | |
4 | * Maintainer unknown. | |
5 | * | |
6 | * Drive tuning added from Rebel.com's kernel sources | |
7 | * -- Russell King (15/11/98) linux@arm.linux.org.uk | |
8 | * | |
9 | * Merge in Russell's HW workarounds, fix various problems | |
10 | * with the timing registers setup. | |
11 | * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org | |
e93df705 SS |
12 | * |
13 | * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com> | |
6ae8b1ef | 14 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
15 | */ |
16 | ||
1da177e4 LT |
17 | #include <linux/types.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/timer.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/blkdev.h> | |
25 | #include <linux/hdreg.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/ide.h> | |
28 | ||
29 | #include <asm/io.h> | |
30 | #include <asm/dma.h> | |
31 | ||
32 | #undef DEBUG | |
33 | ||
34 | #ifdef DEBUG | |
35 | #define DBG(arg) printk arg | |
36 | #else | |
37 | #define DBG(fmt,...) | |
38 | #endif | |
39 | /* | |
40 | * SL82C105 PCI config register 0x40 bits. | |
41 | */ | |
42 | #define CTRL_IDE_IRQB (1 << 30) | |
43 | #define CTRL_IDE_IRQA (1 << 28) | |
44 | #define CTRL_LEGIRQ (1 << 11) | |
45 | #define CTRL_P1F16 (1 << 5) | |
46 | #define CTRL_P1EN (1 << 4) | |
47 | #define CTRL_P0F16 (1 << 1) | |
48 | #define CTRL_P0EN (1 << 0) | |
49 | ||
50 | /* | |
e93df705 SS |
51 | * Convert a PIO mode and cycle time to the required on/off times |
52 | * for the interface. This has protection against runaway timings. | |
1da177e4 | 53 | */ |
7dd00083 | 54 | static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio) |
1da177e4 | 55 | { |
e93df705 | 56 | unsigned int cmd_on, cmd_off; |
2229833c | 57 | u8 iordy = 0; |
1da177e4 | 58 | |
7dd00083 BZ |
59 | cmd_on = (ide_pio_timings[pio].active_time + 29) / 30; |
60 | cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30; | |
1da177e4 | 61 | |
1da177e4 LT |
62 | if (cmd_on == 0) |
63 | cmd_on = 1; | |
64 | ||
1da177e4 LT |
65 | if (cmd_off == 0) |
66 | cmd_off = 1; | |
67 | ||
7dd00083 | 68 | if (pio > 2 || ide_dev_has_iordy(drive->id)) |
2229833c BZ |
69 | iordy = 0x40; |
70 | ||
71 | return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy; | |
1da177e4 LT |
72 | } |
73 | ||
74 | /* | |
e93df705 | 75 | * Configure the chipset for PIO mode. |
1da177e4 | 76 | */ |
88b2b32b | 77 | static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 78 | { |
36501650 | 79 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
e93df705 | 80 | int reg = 0x44 + drive->dn * 4; |
e93df705 | 81 | u16 drv_ctrl; |
1da177e4 | 82 | |
7dd00083 | 83 | drv_ctrl = get_pio_timings(drive, pio); |
46cedc9b SS |
84 | |
85 | /* | |
86 | * Store the PIO timings so that we can restore them | |
87 | * in case DMA will be turned off... | |
88 | */ | |
89 | drive->drive_data &= 0xffff0000; | |
90 | drive->drive_data |= drv_ctrl; | |
1da177e4 | 91 | |
6ae8b1ef BZ |
92 | pci_write_config_word(dev, reg, drv_ctrl); |
93 | pci_read_config_word (dev, reg, &drv_ctrl); | |
e93df705 SS |
94 | |
95 | printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name, | |
7dd00083 BZ |
96 | ide_xfer_verbose(pio + XFER_PIO_0), |
97 | ide_pio_cycle_time(drive, pio), drv_ctrl); | |
1da177e4 LT |
98 | } |
99 | ||
46cedc9b | 100 | /* |
88b2b32b | 101 | * Configure the chipset for DMA mode. |
46cedc9b | 102 | */ |
88b2b32b | 103 | static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed) |
46cedc9b SS |
104 | { |
105 | static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200}; | |
106 | u16 drv_ctrl; | |
107 | ||
108 | DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n", | |
109 | drive->name, ide_xfer_verbose(speed))); | |
110 | ||
4db90a14 | 111 | drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0]; |
46cedc9b | 112 | |
4db90a14 BZ |
113 | /* |
114 | * Store the DMA timings so that we can actually program | |
115 | * them when DMA will be turned on... | |
116 | */ | |
117 | drive->drive_data &= 0x0000ffff; | |
118 | drive->drive_data |= (unsigned long)drv_ctrl << 16; | |
46cedc9b SS |
119 | } |
120 | ||
1da177e4 LT |
121 | /* |
122 | * The SL82C105 holds off all IDE interrupts while in DMA mode until | |
123 | * all DMA activity is completed. Sometimes this causes problems (eg, | |
124 | * when the drive wants to report an error condition). | |
125 | * | |
126 | * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller | |
127 | * state machine. We need to kick this to work around various bugs. | |
128 | */ | |
129 | static inline void sl82c105_reset_host(struct pci_dev *dev) | |
130 | { | |
131 | u16 val; | |
132 | ||
133 | pci_read_config_word(dev, 0x7e, &val); | |
134 | pci_write_config_word(dev, 0x7e, val | (1 << 2)); | |
135 | pci_write_config_word(dev, 0x7e, val & ~(1 << 2)); | |
136 | } | |
137 | ||
138 | /* | |
139 | * If we get an IRQ timeout, it might be that the DMA state machine | |
140 | * got confused. Fix from Todd Inglett. Details from Winbond. | |
141 | * | |
142 | * This function is called when the IDE timer expires, the drive | |
143 | * indicates that it is READY, and we were waiting for DMA to complete. | |
144 | */ | |
841d2a9b | 145 | static void sl82c105_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 146 | { |
688a87d1 | 147 | ide_hwif_t *hwif = HWIF(drive); |
36501650 | 148 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
688a87d1 SS |
149 | u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; |
150 | u8 dma_cmd; | |
1da177e4 | 151 | |
688a87d1 | 152 | printk("sl82c105: lost IRQ, resetting host\n"); |
1da177e4 LT |
153 | |
154 | /* | |
155 | * Check the raw interrupt from the drive. | |
156 | */ | |
157 | pci_read_config_dword(dev, 0x40, &val); | |
158 | if (val & mask) | |
159 | printk("sl82c105: drive was requesting IRQ, but host lost it\n"); | |
160 | ||
161 | /* | |
162 | * Was DMA enabled? If so, disable it - we're resetting the | |
163 | * host. The IDE layer will be handling the drive for us. | |
164 | */ | |
688a87d1 SS |
165 | dma_cmd = inb(hwif->dma_command); |
166 | if (dma_cmd & 1) { | |
167 | outb(dma_cmd & ~1, hwif->dma_command); | |
1da177e4 LT |
168 | printk("sl82c105: DMA was enabled\n"); |
169 | } | |
170 | ||
171 | sl82c105_reset_host(dev); | |
1da177e4 LT |
172 | } |
173 | ||
174 | /* | |
175 | * ATAPI devices can cause the SL82C105 DMA state machine to go gaga. | |
176 | * Winbond recommend that the DMA state machine is reset prior to | |
177 | * setting the bus master DMA enable bit. | |
178 | * | |
179 | * The generic IDE core will have disabled the BMEN bit before this | |
180 | * function is called. | |
181 | */ | |
688a87d1 | 182 | static void sl82c105_dma_start(ide_drive_t *drive) |
1da177e4 | 183 | { |
688a87d1 | 184 | ide_hwif_t *hwif = HWIF(drive); |
36501650 | 185 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
6ae8b1ef BZ |
186 | int reg = 0x44 + drive->dn * 4; |
187 | ||
188 | DBG(("%s(drive:%s)\n", __FUNCTION__, drive->name)); | |
189 | ||
190 | pci_write_config_word(dev, reg, drive->drive_data >> 16); | |
1da177e4 LT |
191 | |
192 | sl82c105_reset_host(dev); | |
193 | ide_dma_start(drive); | |
194 | } | |
195 | ||
c283f5db | 196 | static void sl82c105_dma_timeout(ide_drive_t *drive) |
1da177e4 | 197 | { |
36501650 BZ |
198 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
199 | ||
c283f5db | 200 | DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name)); |
1da177e4 | 201 | |
36501650 | 202 | sl82c105_reset_host(dev); |
c283f5db | 203 | ide_dma_timeout(drive); |
1da177e4 LT |
204 | } |
205 | ||
6ae8b1ef | 206 | static int sl82c105_dma_end(ide_drive_t *drive) |
1da177e4 | 207 | { |
36501650 | 208 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
e93df705 | 209 | int reg = 0x44 + drive->dn * 4; |
6ae8b1ef BZ |
210 | int ret; |
211 | ||
212 | DBG(("%s(drive:%s)\n", __FUNCTION__, drive->name)); | |
1da177e4 | 213 | |
6ae8b1ef | 214 | ret = __ide_dma_end(drive); |
7469aaf6 | 215 | |
e93df705 SS |
216 | pci_write_config_word(dev, reg, drive->drive_data); |
217 | ||
6ae8b1ef | 218 | return ret; |
1da177e4 LT |
219 | } |
220 | ||
1da177e4 LT |
221 | /* |
222 | * ATA reset will clear the 16 bits mode in the control | |
08590556 | 223 | * register, we need to reprogram it |
1da177e4 LT |
224 | */ |
225 | static void sl82c105_resetproc(ide_drive_t *drive) | |
226 | { | |
36501650 | 227 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
1da177e4 LT |
228 | u32 val; |
229 | ||
230 | DBG(("sl82c105_resetproc(drive:%s)\n", drive->name)); | |
231 | ||
232 | pci_read_config_dword(dev, 0x40, &val); | |
08590556 BZ |
233 | val |= (CTRL_P1F16 | CTRL_P0F16); |
234 | pci_write_config_dword(dev, 0x40, val); | |
1da177e4 | 235 | } |
1da177e4 LT |
236 | |
237 | /* | |
238 | * Return the revision of the Winbond bridge | |
239 | * which this function is part of. | |
240 | */ | |
241 | static unsigned int sl82c105_bridge_revision(struct pci_dev *dev) | |
242 | { | |
243 | struct pci_dev *bridge; | |
1da177e4 LT |
244 | |
245 | /* | |
246 | * The bridge should be part of the same device, but function 0. | |
247 | */ | |
640b31bf | 248 | bridge = pci_get_bus_and_slot(dev->bus->number, |
1da177e4 LT |
249 | PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); |
250 | if (!bridge) | |
251 | return -1; | |
252 | ||
253 | /* | |
254 | * Make sure it is a Winbond 553 and is an ISA bridge. | |
255 | */ | |
256 | if (bridge->vendor != PCI_VENDOR_ID_WINBOND || | |
257 | bridge->device != PCI_DEVICE_ID_WINBOND_83C553 || | |
640b31bf AC |
258 | bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) { |
259 | pci_dev_put(bridge); | |
1da177e4 | 260 | return -1; |
640b31bf | 261 | } |
1da177e4 LT |
262 | /* |
263 | * We need to find function 0's revision, not function 1 | |
264 | */ | |
640b31bf | 265 | pci_dev_put(bridge); |
1da177e4 | 266 | |
44c10138 | 267 | return bridge->revision; |
1da177e4 LT |
268 | } |
269 | ||
270 | /* | |
271 | * Enable the PCI device | |
272 | * | |
273 | * --BenH: It's arch fixup code that should enable channels that | |
274 | * have not been enabled by firmware. I decided we can still enable | |
275 | * channel 0 here at least, but channel 1 has to be enabled by | |
276 | * firmware or arch code. We still set both to 16 bits mode. | |
277 | */ | |
34a62246 | 278 | static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg) |
1da177e4 LT |
279 | { |
280 | u32 val; | |
281 | ||
282 | DBG(("init_chipset_sl82c105()\n")); | |
283 | ||
284 | pci_read_config_dword(dev, 0x40, &val); | |
285 | val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16; | |
286 | pci_write_config_dword(dev, 0x40, val); | |
287 | ||
288 | return dev->irq; | |
289 | } | |
290 | ||
1da177e4 | 291 | /* |
688a87d1 | 292 | * Initialise IDE channel |
1da177e4 | 293 | */ |
34a62246 | 294 | static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif) |
1da177e4 | 295 | { |
36501650 | 296 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
9648f552 | 297 | unsigned int rev; |
dd607d23 | 298 | |
1da177e4 LT |
299 | DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index)); |
300 | ||
26bcb879 | 301 | hwif->set_pio_mode = &sl82c105_set_pio_mode; |
88b2b32b | 302 | hwif->set_dma_mode = &sl82c105_set_dma_mode; |
e93df705 SS |
303 | hwif->resetproc = &sl82c105_resetproc; |
304 | ||
1da177e4 LT |
305 | if (!hwif->dma_base) |
306 | return; | |
307 | ||
36501650 | 308 | rev = sl82c105_bridge_revision(dev); |
9648f552 RK |
309 | if (rev <= 5) { |
310 | /* | |
311 | * Never ever EVER under any circumstances enable | |
312 | * DMA when the bridge is this old. | |
313 | */ | |
688a87d1 SS |
314 | printk(" %s: Winbond W83C553 bridge revision %d, " |
315 | "BM-DMA disabled\n", hwif->name, rev); | |
316 | return; | |
9648f552 | 317 | } |
688a87d1 | 318 | |
5f8b6c34 | 319 | hwif->mwdma_mask = ATA_MWDMA2; |
688a87d1 | 320 | |
841d2a9b | 321 | hwif->dma_lost_irq = &sl82c105_dma_lost_irq; |
688a87d1 | 322 | hwif->dma_start = &sl82c105_dma_start; |
6ae8b1ef | 323 | hwif->ide_dma_end = &sl82c105_dma_end; |
c283f5db | 324 | hwif->dma_timeout = &sl82c105_dma_timeout; |
688a87d1 | 325 | |
688a87d1 SS |
326 | if (hwif->mate) |
327 | hwif->serialized = hwif->mate->serialized = 1; | |
1da177e4 LT |
328 | } |
329 | ||
85620436 | 330 | static const struct ide_port_info sl82c105_chipset __devinitdata = { |
1da177e4 LT |
331 | .name = "W82C105", |
332 | .init_chipset = init_chipset_sl82c105, | |
333 | .init_hwif = init_hwif_sl82c105, | |
1da177e4 | 334 | .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, |
caea7602 BZ |
335 | .host_flags = IDE_HFLAG_IO_32BIT | |
336 | IDE_HFLAG_UNMASK_IRQS | | |
337 | IDE_HFLAG_NO_AUTODMA | | |
338 | IDE_HFLAG_BOOTABLE, | |
4099d143 | 339 | .pio_mask = ATA_PIO5, |
1da177e4 LT |
340 | }; |
341 | ||
342 | static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
343 | { | |
344 | return ide_setup_pci_device(dev, &sl82c105_chipset); | |
345 | } | |
346 | ||
9cbcc5e3 BZ |
347 | static const struct pci_device_id sl82c105_pci_tbl[] = { |
348 | { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 }, | |
1da177e4 LT |
349 | { 0, }, |
350 | }; | |
351 | MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl); | |
352 | ||
353 | static struct pci_driver driver = { | |
354 | .name = "W82C105_IDE", | |
355 | .id_table = sl82c105_pci_tbl, | |
356 | .probe = sl82c105_init_one, | |
357 | }; | |
358 | ||
82ab1eec | 359 | static int __init sl82c105_ide_init(void) |
1da177e4 LT |
360 | { |
361 | return ide_pci_register_driver(&driver); | |
362 | } | |
363 | ||
364 | module_init(sl82c105_ide_init); | |
365 | ||
366 | MODULE_DESCRIPTION("PCI driver module for W82C105 IDE"); | |
367 | MODULE_LICENSE("GPL"); |