projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] serverworks: Switch to pci refcounted interfaces
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / sis5513.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/ide/pci/sis5513.c Version 0.16ac+vp Jun 18, 2003
3 *
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
6 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
7 * May be copied or modified under the terms of the GNU General Public License
8 *
9 *
10 * Thanks :
11 *
12 * SiS Taiwan : for direct support and hardware.
13 * Daniela Engert : for initial ATA100 advices and numerous others.
14 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
15 * for checking code correctness, providing patches.
16 *
17 *
18 * Original tests and design on the SiS620 chipset.
19 * ATA100 tests and design on the SiS735 chipset.
20 * ATA16/33 support from specs
21 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
22 * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
23 *
24 * Documentation:
25 * SiS chipset documentation available under NDA to companies only
26 * (not to individuals).
27 */
28
29/*
30 * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
31 * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
32 * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
33 *
34 * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
35 * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
36 * can figure out that we have a more modern and more capable 5513 by looking
37 * for the respective NorthBridge IDs.
38 *
39 * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
40 * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
41 * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
42 * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
43 * bits, changing its device id to the true one - 5517 for 961 and 5518 for
44 * 962/963.
45 */
46
1da177e4
LT		 47#include <linux/types.h>
48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/delay.h>
51#include <linux/timer.h>
52#include <linux/mm.h>
53#include <linux/ioport.h>
54#include <linux/blkdev.h>
55#include <linux/hdreg.h>
56
57#include <linux/interrupt.h>
58#include <linux/pci.h>
59#include <linux/init.h>
60#include <linux/ide.h>
61
62#include <asm/irq.h>
63
64#include "ide-timing.h"
65
66#define DISPLAY_SIS_TIMINGS
67
68/* registers layout and init values are chipset family dependant */
69
70#define ATA_16 0x01
71#define ATA_33 0x02
72#define ATA_66 0x03
73#define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
74#define ATA_100 0x05
75#define ATA_133a 0x06 // SiS961b with 133 support
76#define ATA_133 0x07 // SiS962/963
77
78static u8 chipset_family;
79
80/*
81 * Devices supported
82 */
83static const struct {
84 const char *name;
85 u16 host_id;
86 u8 chipset_family;
87 u8 flags;
88} SiSHostChipInfo[] = {
47d4b906
DW		 89 { "SiS968", PCI_DEVICE_ID_SI_968, ATA_133 },
90 { "SiS966", PCI_DEVICE_ID_SI_966, ATA_133 },
14351f8e 91 { "SiS965", PCI_DEVICE_ID_SI_965, ATA_133 },
1da177e4
LT		 92 { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
93 { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
94 { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
95 { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
96 { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
97
98 { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
99 { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
100
101 { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
102 { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
103 { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
104 { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
105 { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
106
107 { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
108 { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
109 { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
110 { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
111 { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
112 { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
113
114 { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
115 { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
d266ab88 116 { "SiS5517", PCI_DEVICE_ID_SI_5517, ATA_16 },
1da177e4
LT		 117 { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
118};
119
120/* Cycle time bits and values vary across chip dma capabilities
121 These three arrays hold the register layout and the values to set.
122 Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
123
124/* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
125static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
126static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
127static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
128 {0,0,0,0,0,0,0}, /* no udma */
129 {0,0,0,0,0,0,0}, /* no udma */
130 {3,2,1,0,0,0,0}, /* ATA_33 */
131 {7,5,3,2,1,0,0}, /* ATA_66 */
132 {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
133 {11,7,5,4,2,1,0}, /* ATA_100 */
134 {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
135 {15,10,7,5,3,2,1}, /* ATA_133 */
136};
137/* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
138 See SiS962 data sheet for more detail */
139static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
140 {0,0,0,0,0,0,0}, /* no udma */
141 {0,0,0,0,0,0,0}, /* no udma */
142 {2,1,1,0,0,0,0},
143 {4,3,2,1,0,0,0},
144 {4,3,2,1,0,0,0},
145 {6,4,3,1,1,1,0},
146 {9,6,4,2,2,2,2},
147 {9,6,4,2,2,2,2},
148};
149/* Initialize time, Active time, Recovery time vary across
150 IDE clock settings. These 3 arrays hold the register value
151 for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
152static u8 ini_time_value[][8] = {
153 {0,0,0,0,0,0,0,0},
154 {0,0,0,0,0,0,0,0},
155 {2,1,0,0,0,1,0,0},
156 {4,3,1,1,1,3,1,1},
157 {4,3,1,1,1,3,1,1},
158 {6,4,2,2,2,4,2,2},
159 {9,6,3,3,3,6,3,3},
160 {9,6,3,3,3,6,3,3},
161};
162static u8 act_time_value[][8] = {
163 {0,0,0,0,0,0,0,0},
164 {0,0,0,0,0,0,0,0},
165 {9,9,9,2,2,7,2,2},
166 {19,19,19,5,4,14,5,4},
167 {19,19,19,5,4,14,5,4},
168 {28,28,28,7,6,21,7,6},
169 {38,38,38,10,9,28,10,9},
170 {38,38,38,10,9,28,10,9},
171};
172static u8 rco_time_value[][8] = {
173 {0,0,0,0,0,0,0,0},
174 {0,0,0,0,0,0,0,0},
175 {9,2,0,2,0,7,1,1},
176 {19,5,1,5,2,16,3,2},
177 {19,5,1,5,2,16,3,2},
178 {30,9,3,9,4,25,6,4},
179 {40,12,4,12,5,34,12,5},
180 {40,12,4,12,5,34,12,5},
181};
182
183/*
184 * Printing configuration
185 */
186/* Used for chipset type printing at boot time */
187static char* chipset_capability[] = {
188 "ATA", "ATA 16",
189 "ATA 33", "ATA 66",
190 "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
191 "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
192};
193
194#if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
195#include <linux/stat.h>
196#include <linux/proc_fs.h>
197
198static u8 sis_proc = 0;
199
200static struct pci_dev *bmide_dev;
201
202static char* cable_type[] = {
203 "80 pins",
204 "40 pins"
205};
206
207static char* recovery_time[] ={
208 "12 PCICLK", "1 PCICLK",
209 "2 PCICLK", "3 PCICLK",
210 "4 PCICLK", "5 PCICLCK",
211 "6 PCICLK", "7 PCICLCK",
212 "8 PCICLK", "9 PCICLCK",
213 "10 PCICLK", "11 PCICLK",
214 "13 PCICLK", "14 PCICLK",
215 "15 PCICLK", "15 PCICLK"
216};
217
218static char* active_time[] = {
219 "8 PCICLK", "1 PCICLCK",
220 "2 PCICLK", "3 PCICLK",
221 "4 PCICLK", "5 PCICLK",
222 "6 PCICLK", "12 PCICLK"
223};
224
225static char* cycle_time[] = {
226 "Reserved", "2 CLK",
227 "3 CLK", "4 CLK",
228 "5 CLK", "6 CLK",
229 "7 CLK", "8 CLK",
230 "9 CLK", "10 CLK",
231 "11 CLK", "12 CLK",
232 "13 CLK", "14 CLK",
233 "15 CLK", "16 CLK"
234};
235
236/* Generic add master or slave info function */
237static char* get_drives_info (char *buffer, u8 pos)
238{
239 u8 reg00, reg01, reg10, reg11; /* timing registers */
240 u32 regdw0, regdw1;
241 char* p = buffer;
242
243/* Postwrite/Prefetch */
244 if (chipset_family < ATA_133) {
245 pci_read_config_byte(bmide_dev, 0x4b, &reg00);
246 p += sprintf(p, "Drive %d: Postwrite %s \t \t Postwrite %s\n",
247 pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled",
248 (reg00 & (0x40 << pos)) ? "Enabled" : "Disabled");
249 p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
250 (reg00 & (0x01 << pos)) ? "Enabled" : "Disabled",
251 (reg00 & (0x04 << pos)) ? "Enabled" : "Disabled");
252 pci_read_config_byte(bmide_dev, 0x40+2*pos, &reg00);
253 pci_read_config_byte(bmide_dev, 0x41+2*pos, &reg01);
254 pci_read_config_byte(bmide_dev, 0x44+2*pos, &reg10);
255 pci_read_config_byte(bmide_dev, 0x45+2*pos, &reg11);
256 } else {
257 u32 reg54h;
258 u8 drive_pci = 0x40;
259 pci_read_config_dword(bmide_dev, 0x54, &reg54h);
260 if (reg54h & 0x40000000) {
261 // Configuration space remapped to 0x70
262 drive_pci = 0x70;
263 }
264 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos, &regdw0);
265 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos+8, &regdw1);
266
267 p += sprintf(p, "Drive %d:\n", pos);
268 }
269
270
271/* UDMA */
272 if (chipset_family >= ATA_133) {
273 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
274 (regdw0 & 0x04) ? "Enabled" : "Disabled",
275 (regdw1 & 0x04) ? "Enabled" : "Disabled");
276 p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
277 cycle_time[(regdw0 & 0xF0) >> 4],
278 cycle_time[(regdw1 & 0xF0) >> 4]);
279 } else if (chipset_family >= ATA_33) {
280 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
281 (reg01 & 0x80) ? "Enabled" : "Disabled",
282 (reg11 & 0x80) ? "Enabled" : "Disabled");
283
284 p += sprintf(p, " UDMA Cycle Time ");
285 switch(chipset_family) {
286 case ATA_33: p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break;
287 case ATA_66:
288 case ATA_100a: p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break;
289 case ATA_100:
290 case ATA_133a: p += sprintf(p, cycle_time[reg01 & 0x0F]); break;
291 default: p += sprintf(p, "?"); break;
292 }
293 p += sprintf(p, " \t UDMA Cycle Time ");
294 switch(chipset_family) {
295 case ATA_33: p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break;
296 case ATA_66:
297 case ATA_100a: p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break;
298 case ATA_100:
299 case ATA_133a: p += sprintf(p, cycle_time[reg11 & 0x0F]); break;
300 default: p += sprintf(p, "?"); break;
301 }
302 p += sprintf(p, "\n");
303 }
304
305
306 if (chipset_family < ATA_133) { /* else case TODO */
307
308/* Data Active */
309 p += sprintf(p, " Data Active Time ");
310 switch(chipset_family) {
311 case ATA_16: /* confirmed */
312 case ATA_33:
313 case ATA_66:
314 case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break;
315 case ATA_100:
316 case ATA_133a: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break;
317 default: p += sprintf(p, "?"); break;
318 }
319 p += sprintf(p, " \t Data Active Time ");
320 switch(chipset_family) {
321 case ATA_16:
322 case ATA_33:
323 case ATA_66:
324 case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break;
325 case ATA_100:
326 case ATA_133a: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break;
327 default: p += sprintf(p, "?"); break;
328 }
329 p += sprintf(p, "\n");
330
331/* Data Recovery */
332 /* warning: may need (reg&0x07) for pre ATA66 chips */
333 p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
334 recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]);
335 }
336
337 return p;
338}
339
340static char* get_masters_info(char* buffer)
341{
342 return get_drives_info(buffer, 0);
343}
344
345static char* get_slaves_info(char* buffer)
346{
347 return get_drives_info(buffer, 1);
348}
349
350/* Main get_info, called on /proc/ide/sis reads */
351static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
352{
353 char *p = buffer;
354 int len;
355 u8 reg;
356 u16 reg2, reg3;
357
358 p += sprintf(p, "\nSiS 5513 ");
359 switch(chipset_family) {
360 case ATA_16: p += sprintf(p, "DMA 16"); break;
361 case ATA_33: p += sprintf(p, "Ultra 33"); break;
362 case ATA_66: p += sprintf(p, "Ultra 66"); break;
363 case ATA_100a:
364 case ATA_100: p += sprintf(p, "Ultra 100"); break;
365 case ATA_133a:
366 case ATA_133: p += sprintf(p, "Ultra 133"); break;
367 default: p+= sprintf(p, "Unknown???"); break;
368 }
369 p += sprintf(p, " chipset\n");
370 p += sprintf(p, "--------------- Primary Channel "
371 "---------------- Secondary Channel "
372 "-------------\n");
373
374/* Status */
375 pci_read_config_byte(bmide_dev, 0x4a, &reg);
376 if (chipset_family == ATA_133) {
377 pci_read_config_word(bmide_dev, 0x50, &reg2);
378 pci_read_config_word(bmide_dev, 0x52, &reg3);
379 }
380 p += sprintf(p, "Channel Status: ");
381 if (chipset_family < ATA_66) {
382 p += sprintf(p, "%s \t \t \t \t %s\n",
383 (reg & 0x04) ? "On" : "Off",
384 (reg & 0x02) ? "On" : "Off");
385 } else if (chipset_family < ATA_133) {
386 p += sprintf(p, "%s \t \t \t \t %s \n",
387 (reg & 0x02) ? "On" : "Off",
388 (reg & 0x04) ? "On" : "Off");
389 } else { /* ATA_133 */
390 p += sprintf(p, "%s \t \t \t \t %s \n",
391 (reg2 & 0x02) ? "On" : "Off",
392 (reg3 & 0x02) ? "On" : "Off");
393 }
394
395/* Operation Mode */
396 pci_read_config_byte(bmide_dev, 0x09, &reg);
397 p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
398 (reg & 0x01) ? "Native" : "Compatible",
399 (reg & 0x04) ? "Native" : "Compatible");
400
401/* 80-pin cable ? */
402 if (chipset_family >= ATA_133) {
403 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
404 (reg2 & 0x01) ? cable_type[1] : cable_type[0],
405 (reg3 & 0x01) ? cable_type[1] : cable_type[0]);
406 } else if (chipset_family > ATA_33) {
407 pci_read_config_byte(bmide_dev, 0x48, &reg);
408 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
409 (reg & 0x10) ? cable_type[1] : cable_type[0],
410 (reg & 0x20) ? cable_type[1] : cable_type[0]);
411 }
412
413/* Prefetch Count */
414 if (chipset_family < ATA_133) {
415 pci_read_config_word(bmide_dev, 0x4c, &reg2);
416 pci_read_config_word(bmide_dev, 0x4e, &reg3);
417 p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
418 reg2, reg3);
419 }
420
421 p = get_masters_info(p);
422 p = get_slaves_info(p);
423
424 len = (p - buffer) - offset;
425 *addr = buffer + offset;
426
427 return len > count ? count : len;
428}
429#endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
430
431static u8 sis5513_ratemask (ide_drive_t *drive)
432{
433 u8 rates[] = { 0, 0, 1, 2, 3, 3, 4, 4 };
434 u8 mode = rates[chipset_family];
435
436 if (!eighty_ninty_three(drive))
437 mode = min(mode, (u8)1);
438 return mode;
439}
440
441/*
442 * Configuration functions
443 */
444/* Enables per-drive prefetch and postwrite */
445static void config_drive_art_rwp (ide_drive_t *drive)
446{
447 ide_hwif_t *hwif = HWIF(drive);
448 struct pci_dev *dev = hwif->pci_dev;
449
450 u8 reg4bh = 0;
451 u8 rw_prefetch = (0x11 << drive->dn);
452
453 if (drive->media != ide_disk)
454 return;
455 pci_read_config_byte(dev, 0x4b, &reg4bh);
456
457 if ((reg4bh & rw_prefetch) != rw_prefetch)
458 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
459}
460
461
462/* Set per-drive active and recovery time */
463static void config_art_rwp_pio (ide_drive_t *drive, u8 pio)
464{
465 ide_hwif_t *hwif = HWIF(drive);
466 struct pci_dev *dev = hwif->pci_dev;
467
468 u8 timing, drive_pci, test1, test2;
469
470 u16 eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
471 u16 xfer_pio = drive->id->eide_pio_modes;
472
473 config_drive_art_rwp(drive);
474 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
475
476 if (xfer_pio> 4)
477 xfer_pio = 0;
478
479 if (drive->id->eide_pio_iordy > 0) {
480 for (xfer_pio = 5;
481 (xfer_pio > 0) &&
482 (drive->id->eide_pio_iordy > eide_pio_timing[xfer_pio]);
483 xfer_pio--);
484 } else {
485 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
486 (drive->id->eide_pio_modes & 2) ? 0x04 :
487 (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
488 }
489
490 timing = (xfer_pio >= pio) ? xfer_pio : pio;
491
492 /* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */
493 drive_pci = 0x40;
494 /* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */
495 if (chipset_family >= ATA_133) {
496 u32 reg54h;
497 pci_read_config_dword(dev, 0x54, &reg54h);
498 if (reg54h & 0x40000000) drive_pci = 0x70;
499 drive_pci += ((drive->dn)*0x4);
500 } else {
501 drive_pci += ((drive->dn)*0x2);
502 }
503
504 /* register layout changed with newer ATA100 chips */
505 if (chipset_family < ATA_100) {
506 pci_read_config_byte(dev, drive_pci, &test1);
507 pci_read_config_byte(dev, drive_pci+1, &test2);
508
509 /* Clear active and recovery timings */
510 test1 &= ~0x0F;
511 test2 &= ~0x07;
512
513 switch(timing) {
514 case 4: test1 |= 0x01; test2 |= 0x03; break;
515 case 3: test1 |= 0x03; test2 |= 0x03; break;
516 case 2: test1 |= 0x04; test2 |= 0x04; break;
517 case 1: test1 |= 0x07; test2 |= 0x06; break;
518 default: break;
519 }
520 pci_write_config_byte(dev, drive_pci, test1);
521 pci_write_config_byte(dev, drive_pci+1, test2);
522 } else if (chipset_family < ATA_133) {
523 switch(timing) { /* active recovery
524 v v */
525 case 4: test1 = 0x30|0x01; break;
526 case 3: test1 = 0x30|0x03; break;
527 case 2: test1 = 0x40|0x04; break;
528 case 1: test1 = 0x60|0x07; break;
d266ab88 529 case 0: test1 = 0x00; break;
1da177e4
LT		 530 default: break;
531 }
532 pci_write_config_byte(dev, drive_pci, test1);
533 } else { /* ATA_133 */
534 u32 test3;
535 pci_read_config_dword(dev, drive_pci, &test3);
536 test3 &= 0xc0c00fff;
537 if (test3 & 0x08) {
538 test3 |= (unsigned long)ini_time_value[ATA_133][timing] << 12;
539 test3 |= (unsigned long)act_time_value[ATA_133][timing] << 16;
540 test3 |= (unsigned long)rco_time_value[ATA_133][timing] << 24;
541 } else {
542 test3 |= (unsigned long)ini_time_value[ATA_100][timing] << 12;
543 test3 |= (unsigned long)act_time_value[ATA_100][timing] << 16;
544 test3 |= (unsigned long)rco_time_value[ATA_100][timing] << 24;
545 }
546 pci_write_config_dword(dev, drive_pci, test3);
547 }
548}
549
550static int config_chipset_for_pio (ide_drive_t *drive, u8 pio)
551{
552 if (pio == 255)
553 pio = ide_find_best_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
554 config_art_rwp_pio(drive, pio);
555 return ide_config_drive_speed(drive, XFER_PIO_0 + min_t(u8, pio, 4));
556}
557
558static int sis5513_tune_chipset (ide_drive_t *drive, u8 xferspeed)
559{
560 ide_hwif_t *hwif = HWIF(drive);
561 struct pci_dev *dev = hwif->pci_dev;
562
563 u8 drive_pci, reg, speed;
564 u32 regdw;
565
566 speed = ide_rate_filter(sis5513_ratemask(drive), xferspeed);
567
568 /* See config_art_rwp_pio for drive pci config registers */
569 drive_pci = 0x40;
570 if (chipset_family >= ATA_133) {
571 u32 reg54h;
572 pci_read_config_dword(dev, 0x54, &reg54h);
573 if (reg54h & 0x40000000) drive_pci = 0x70;
574 drive_pci += ((drive->dn)*0x4);
575 pci_read_config_dword(dev, (unsigned long)drive_pci, &regdw);
576 /* Disable UDMA bit for non UDMA modes on UDMA chips */
577 if (speed < XFER_UDMA_0) {
578 regdw &= 0xfffffffb;
579 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
580 }
581
582 } else {
583 drive_pci += ((drive->dn)*0x2);
584 pci_read_config_byte(dev, drive_pci+1, &reg);
585 /* Disable UDMA bit for non UDMA modes on UDMA chips */
586 if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) {
587 reg &= 0x7F;
588 pci_write_config_byte(dev, drive_pci+1, reg);
589 }
590 }
591
592 /* Config chip for mode */
593 switch(speed) {
594 case XFER_UDMA_6:
595 case XFER_UDMA_5:
596 case XFER_UDMA_4:
597 case XFER_UDMA_3:
598 case XFER_UDMA_2:
599 case XFER_UDMA_1:
600 case XFER_UDMA_0:
601 if (chipset_family >= ATA_133) {
602 regdw |= 0x04;
603 regdw &= 0xfffff00f;
604 /* check if ATA133 enable */
605 if (regdw & 0x08) {
606 regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4;
607 regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8;
608 } else {
609 /* if ATA133 disable, we should not set speed above UDMA5 */
610 if (speed > XFER_UDMA_5)
611 speed = XFER_UDMA_5;
612 regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4;
613 regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8;
614 }
615 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
616 } else {
617 /* Force the UDMA bit on if we want to use UDMA */
618 reg |= 0x80;
619 /* clean reg cycle time bits */
620 reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family]))
621 << cycle_time_offset[chipset_family]);
622 /* set reg cycle time bits */
623 reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0]
624 << cycle_time_offset[chipset_family];
625 pci_write_config_byte(dev, drive_pci+1, reg);
626 }
627 break;
628 case XFER_MW_DMA_2:
629 case XFER_MW_DMA_1:
630 case XFER_MW_DMA_0:
631 case XFER_SW_DMA_2:
632 case XFER_SW_DMA_1:
633 case XFER_SW_DMA_0:
634 break;
635 case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4));
636 case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3));
637 case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2));
638 case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1));
639 case XFER_PIO_0:
640 default: return((int) config_chipset_for_pio(drive, 0));
641 }
642
643 return ((int) ide_config_drive_speed(drive, speed));
644}
645
646static void sis5513_tune_drive (ide_drive_t *drive, u8 pio)
647{
648 (void) config_chipset_for_pio(drive, pio);
649}
650
651/*
652 * ((id->hw_config & 0x4000|0x2000) && (HWIF(drive)->udma_four))
653 */
654static int config_chipset_for_dma (ide_drive_t *drive)
655{
656 u8 speed = ide_dma_speed(drive, sis5513_ratemask(drive));
657
658#ifdef DEBUG
659 printk("SIS5513: config_chipset_for_dma, drive %d, ultra %x\n",
660 drive->dn, drive->id->dma_ultra);
661#endif
662
663 if (!(speed))
664 return 0;
665
666 sis5513_tune_chipset(drive, speed);
667 return ide_dma_enable(drive);
668}
669
670static int sis5513_config_drive_xfer_rate (ide_drive_t *drive)
671{
672 ide_hwif_t *hwif = HWIF(drive);
673 struct hd_driveid *id = drive->id;
674
675 drive->init_speed = 0;
676
677 if (id && (id->capability & 1) && drive->autodma) {
678
679 if (ide_use_dma(drive)) {
680 if (config_chipset_for_dma(drive))
681 return hwif->ide_dma_on(drive);
682 }
683
684 goto fast_ata_pio;
685
686 } else if ((id->capability & 8) || (id->field_valid & 2)) {
687fast_ata_pio:
688 sis5513_tune_drive(drive, 5);
689 return hwif->ide_dma_off_quietly(drive);
690 }
691 /* IORDY not supported */
692 return 0;
693}
694
695/* initiates/aborts (U)DMA read/write operations on a drive. */
696static int sis5513_config_xfer_rate (ide_drive_t *drive)
697{
698 config_drive_art_rwp(drive);
699 config_art_rwp_pio(drive, 5);
700 return sis5513_config_drive_xfer_rate(drive);
701}
702
703/*
704 Future simpler config_xfer_rate :
705 When ide_find_best_mode is made bad-drive aware
706 - remove config_drive_xfer_rate and config_chipset_for_dma,
707 - replace config_xfer_rate with the following
708
709static int sis5513_config_xfer_rate (ide_drive_t *drive)
710{
711 u16 w80 = HWIF(drive)->udma_four;
712 u16 speed;
713
714 config_drive_art_rwp(drive);
715 config_art_rwp_pio(drive, 5);
716
717 speed = ide_find_best_mode(drive,
718 XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
719 (chipset_family >= ATA_33 ? XFER_UDMA : 0) |
720 (w80 && chipset_family >= ATA_66 ? XFER_UDMA_66 : 0) |
721 (w80 && chipset_family >= ATA_100a ? XFER_UDMA_100 : 0) |
722 (w80 && chipset_family >= ATA_133a ? XFER_UDMA_133 : 0));
723
724 sis5513_tune_chipset(drive, speed);
725
726 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
727 return HWIF(drive)->ide_dma_on(drive);
728 return HWIF(drive)->ide_dma_off_quietly(drive);
729}
730*/
731
732/* Chip detection and general config */
2b0c4bed 733static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name)
1da177e4
LT		 734{
735 struct pci_dev *host;
736 int i = 0;
737
738 chipset_family = 0;
739
740 for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
741
742 host = pci_find_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
743
744 if (!host)
745 continue;
746
747 chipset_family = SiSHostChipInfo[i].chipset_family;
748
749 /* Special case for SiS630 : 630S/ET is ATA_100a */
750 if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
751 u8 hostrev;
752 pci_read_config_byte(host, PCI_REVISION_ID, &hostrev);
753 if (hostrev >= 0x30)
754 chipset_family = ATA_100a;
755 }
756
757 printk(KERN_INFO "SIS5513: %s %s controller\n",
758 SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
759 }
760
761 if (!chipset_family) { /* Belongs to pci-quirks */
762
763 u32 idemisc;
764 u16 trueid;
765
766 /* Disable ID masking and register remapping */
767 pci_read_config_dword(dev, 0x54, &idemisc);
768 pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
769 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
770 pci_write_config_dword(dev, 0x54, idemisc);
771
772 if (trueid == 0x5518) {
773 printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
774 chipset_family = ATA_133;
775
776 /* Check for 5513 compability mapping
777 * We must use this, else the port enabled code will fail,
778 * as it expects the enablebits at 0x4a.
779 */
780 if ((idemisc & 0x40000000) == 0) {
781 pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
782 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
783 }
784 }
785 }
786
787 if (!chipset_family) { /* Belongs to pci-quirks */
788
789 struct pci_dev *lpc_bridge;
790 u16 trueid;
791 u8 prefctl;
792 u8 idecfg;
793 u8 sbrev;
794
795 pci_read_config_byte(dev, 0x4a, &idecfg);
796 pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
797 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
798 pci_write_config_byte(dev, 0x4a, idecfg);
799
800 if (trueid == 0x5517) { /* SiS 961/961B */
801
802 lpc_bridge = pci_find_slot(0x00, 0x10); /* Bus 0, Dev 2, Fn 0 */
803 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
804 pci_read_config_byte(dev, 0x49, &prefctl);
805
806 if (sbrev == 0x10 && (prefctl & 0x80)) {
807 printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
808 chipset_family = ATA_133a;
809 } else {
810 printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
811 chipset_family = ATA_100;
812 }
813 }
814 }
815
816 if (!chipset_family)
817 return -1;
818
819 /* Make general config ops here
820 1/ tell IDE channels to operate in Compatibility mode only
821 2/ tell old chips to allow per drive IDE timings */
822
823 {
824 u8 reg;
825 u16 regw;
826
827 switch(chipset_family) {
828 case ATA_133:
829 /* SiS962 operation mode */
830 pci_read_config_word(dev, 0x50, &regw);
831 if (regw & 0x08)
832 pci_write_config_word(dev, 0x50, regw&0xfff7);
833 pci_read_config_word(dev, 0x52, &regw);
834 if (regw & 0x08)
835 pci_write_config_word(dev, 0x52, regw&0xfff7);
836 break;
837 case ATA_133a:
838 case ATA_100:
839 /* Fixup latency */
840 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
841 /* Set compatibility bit */
842 pci_read_config_byte(dev, 0x49, &reg);
843 if (!(reg & 0x01)) {
844 pci_write_config_byte(dev, 0x49, reg|0x01);
845 }
846 break;
847 case ATA_100a:
848 case ATA_66:
849 /* Fixup latency */
850 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
851
852 /* On ATA_66 chips the bit was elsewhere */
853 pci_read_config_byte(dev, 0x52, &reg);
854 if (!(reg & 0x04)) {
855 pci_write_config_byte(dev, 0x52, reg|0x04);
856 }
857 break;
858 case ATA_33:
859 /* On ATA_33 we didn't have a single bit to set */
860 pci_read_config_byte(dev, 0x09, &reg);
861 if ((reg & 0x0f) != 0x00) {
862 pci_write_config_byte(dev, 0x09, reg&0xf0);
863 }
864 case ATA_16:
865 /* force per drive recovery and active timings
866 needed on ATA_33 and below chips */
867 pci_read_config_byte(dev, 0x52, &reg);
868 if (!(reg & 0x08)) {
869 pci_write_config_byte(dev, 0x52, reg|0x08);
870 }
871 break;
872 }
873
874#if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
875 if (!sis_proc) {
876 sis_proc = 1;
877 bmide_dev = dev;
878 ide_pci_create_host_proc("sis", sis_get_info);
879 }
880#endif
881 }
882
883 return 0;
884}
885
2b0c4bed 886static unsigned int __devinit ata66_sis5513 (ide_hwif_t *hwif)
1da177e4
LT		 887{
888 u8 ata66 = 0;
889
890 if (chipset_family >= ATA_133) {
891 u16 regw = 0;
892 u16 reg_addr = hwif->channel ? 0x52: 0x50;
893 pci_read_config_word(hwif->pci_dev, reg_addr, &regw);
894 ata66 = (regw & 0x8000) ? 0 : 1;
895 } else if (chipset_family >= ATA_66) {
896 u8 reg48h = 0;
897 u8 mask = hwif->channel ? 0x20 : 0x10;
898 pci_read_config_byte(hwif->pci_dev, 0x48, &reg48h);
899 ata66 = (reg48h & mask) ? 0 : 1;
900 }
901 return ata66;
902}
903
2b0c4bed 904static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
1da177e4
LT		 905{
906 hwif->autodma = 0;
907
908 if (!hwif->irq)
909 hwif->irq = hwif->channel ? 15 : 14;
910
911 hwif->tuneproc = &sis5513_tune_drive;
912 hwif->speedproc = &sis5513_tune_chipset;
913
914 if (!(hwif->dma_base)) {
915 hwif->drives[0].autotune = 1;
916 hwif->drives[1].autotune = 1;
917 return;
918 }
919
920 hwif->atapi_dma = 1;
921 hwif->ultra_mask = 0x7f;
922 hwif->mwdma_mask = 0x07;
923 hwif->swdma_mask = 0x07;
924
925 if (!chipset_family)
926 return;
927
928 if (!(hwif->udma_four))
929 hwif->udma_four = ata66_sis5513(hwif);
930
931 if (chipset_family > ATA_16) {
932 hwif->ide_dma_check = &sis5513_config_xfer_rate;
933 if (!noautodma)
934 hwif->autodma = 1;
935 }
936 hwif->drives[0].autodma = hwif->autodma;
937 hwif->drives[1].autodma = hwif->autodma;
938 return;
939}
940
941static ide_pci_device_t sis5513_chipset __devinitdata = {
942 .name = "SIS5513",
943 .init_chipset = init_chipset_sis5513,
944 .init_hwif = init_hwif_sis5513,
945 .channels = 2,
946 .autodma = NOAUTODMA,
947 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
948 .bootable = ON_BOARD,
949};
950
951static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
952{
953 return ide_setup_pci_device(dev, &sis5513_chipset);
954}
955
956static struct pci_device_id sis5513_pci_tbl[] = {
957 { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
958 { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5518, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
959 { 0, },
960};
961MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
962
963static struct pci_driver driver = {
964 .name = "SIS_IDE",
965 .id_table = sis5513_pci_tbl,
966 .probe = sis5513_init_one,
967};
968
969static int sis5513_ide_init(void)
970{
971 return ide_pci_register_driver(&driver);
972}
973
974module_init(sis5513_ide_init);
975
976MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
977MODULE_DESCRIPTION("PCI driver module for SIS IDE");
978MODULE_LICENSE("GPL");
979
980/*
981 * TODO:
982 * - CLEANUP
983 * - Use drivers/ide/ide-timing.h !
984 * - More checks in the config registers (force values instead of
985 * relying on the BIOS setting them correctly).
986 * - Further optimisations ?
987 * . for example ATA66+ regs 0x48 & 0x4A
988 */
kernel source for telekom puls (alcatel/mediatek)