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ide: mode limiting fixes for user requested speed changes
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / sis5513.c
CommitLineData
1da177e4 1/*
f2befd9e 2 * linux/drivers/ide/pci/sis5513.c Version 0.25 Jun 10, 2007
1da177e4
LT		 3 *
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
6 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
6b8cf772
BZ		 7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
8 *
1da177e4
LT		 9 * May be copied or modified under the terms of the GNU General Public License
10 *
11 *
12 * Thanks :
13 *
14 * SiS Taiwan : for direct support and hardware.
15 * Daniela Engert : for initial ATA100 advices and numerous others.
16 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
17 * for checking code correctness, providing patches.
18 *
19 *
20 * Original tests and design on the SiS620 chipset.
21 * ATA100 tests and design on the SiS735 chipset.
22 * ATA16/33 support from specs
23 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
24 * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
25 *
26 * Documentation:
27 * SiS chipset documentation available under NDA to companies only
28 * (not to individuals).
29 */
30
31/*
32 * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
33 * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
34 * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
35 *
36 * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
37 * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
38 * can figure out that we have a more modern and more capable 5513 by looking
39 * for the respective NorthBridge IDs.
40 *
41 * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
42 * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
43 * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
44 * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
45 * bits, changing its device id to the true one - 5517 for 961 and 5518 for
46 * 962/963.
47 */
48
1da177e4
LT		 49#include <linux/types.h>
50#include <linux/module.h>
51#include <linux/kernel.h>
52#include <linux/delay.h>
53#include <linux/timer.h>
54#include <linux/mm.h>
55#include <linux/ioport.h>
56#include <linux/blkdev.h>
57#include <linux/hdreg.h>
58
59#include <linux/interrupt.h>
60#include <linux/pci.h>
61#include <linux/init.h>
62#include <linux/ide.h>
63
64#include <asm/irq.h>
65
66#include "ide-timing.h"
67
68#define DISPLAY_SIS_TIMINGS
69
70/* registers layout and init values are chipset family dependant */
71
72#define ATA_16 0x01
73#define ATA_33 0x02
74#define ATA_66 0x03
75#define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
76#define ATA_100 0x05
77#define ATA_133a 0x06 // SiS961b with 133 support
78#define ATA_133 0x07 // SiS962/963
79
80static u8 chipset_family;
81
82/*
83 * Devices supported
84 */
85static const struct {
86 const char *name;
87 u16 host_id;
88 u8 chipset_family;
89 u8 flags;
90} SiSHostChipInfo[] = {
47d4b906
DW		 91 { "SiS968", PCI_DEVICE_ID_SI_968, ATA_133 },
92 { "SiS966", PCI_DEVICE_ID_SI_966, ATA_133 },
14351f8e 93 { "SiS965", PCI_DEVICE_ID_SI_965, ATA_133 },
1da177e4
LT		 94 { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
95 { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
96 { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
97 { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
98 { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
99
100 { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
101 { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
102
103 { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
104 { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
105 { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
106 { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
107 { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
108
109 { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
110 { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
111 { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
112 { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
113 { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
114 { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
115
116 { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
117 { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
d266ab88 118 { "SiS5517", PCI_DEVICE_ID_SI_5517, ATA_16 },
1da177e4
LT		 119 { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
120};
121
122/* Cycle time bits and values vary across chip dma capabilities
123 These three arrays hold the register layout and the values to set.
124 Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
125
126/* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
127static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
128static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
129static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
130 {0,0,0,0,0,0,0}, /* no udma */
131 {0,0,0,0,0,0,0}, /* no udma */
132 {3,2,1,0,0,0,0}, /* ATA_33 */
133 {7,5,3,2,1,0,0}, /* ATA_66 */
134 {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
135 {11,7,5,4,2,1,0}, /* ATA_100 */
136 {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
137 {15,10,7,5,3,2,1}, /* ATA_133 */
138};
139/* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
140 See SiS962 data sheet for more detail */
141static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
142 {0,0,0,0,0,0,0}, /* no udma */
143 {0,0,0,0,0,0,0}, /* no udma */
144 {2,1,1,0,0,0,0},
145 {4,3,2,1,0,0,0},
146 {4,3,2,1,0,0,0},
147 {6,4,3,1,1,1,0},
148 {9,6,4,2,2,2,2},
149 {9,6,4,2,2,2,2},
150};
151/* Initialize time, Active time, Recovery time vary across
152 IDE clock settings. These 3 arrays hold the register value
153 for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
154static u8 ini_time_value[][8] = {
155 {0,0,0,0,0,0,0,0},
156 {0,0,0,0,0,0,0,0},
157 {2,1,0,0,0,1,0,0},
158 {4,3,1,1,1,3,1,1},
159 {4,3,1,1,1,3,1,1},
160 {6,4,2,2,2,4,2,2},
161 {9,6,3,3,3,6,3,3},
162 {9,6,3,3,3,6,3,3},
163};
164static u8 act_time_value[][8] = {
165 {0,0,0,0,0,0,0,0},
166 {0,0,0,0,0,0,0,0},
167 {9,9,9,2,2,7,2,2},
168 {19,19,19,5,4,14,5,4},
169 {19,19,19,5,4,14,5,4},
170 {28,28,28,7,6,21,7,6},
171 {38,38,38,10,9,28,10,9},
172 {38,38,38,10,9,28,10,9},
173};
174static u8 rco_time_value[][8] = {
175 {0,0,0,0,0,0,0,0},
176 {0,0,0,0,0,0,0,0},
177 {9,2,0,2,0,7,1,1},
178 {19,5,1,5,2,16,3,2},
179 {19,5,1,5,2,16,3,2},
180 {30,9,3,9,4,25,6,4},
181 {40,12,4,12,5,34,12,5},
182 {40,12,4,12,5,34,12,5},
183};
184
185/*
186 * Printing configuration
187 */
188/* Used for chipset type printing at boot time */
189static char* chipset_capability[] = {
190 "ATA", "ATA 16",
191 "ATA 33", "ATA 66",
192 "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
193 "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
194};
195
ecfd80e4 196#if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
1da177e4
LT		 197#include <linux/stat.h>
198#include <linux/proc_fs.h>
199
200static u8 sis_proc = 0;
201
202static struct pci_dev *bmide_dev;
203
204static char* cable_type[] = {
205 "80 pins",
206 "40 pins"
207};
208
209static char* recovery_time[] ={
210 "12 PCICLK", "1 PCICLK",
211 "2 PCICLK", "3 PCICLK",
212 "4 PCICLK", "5 PCICLCK",
213 "6 PCICLK", "7 PCICLCK",
214 "8 PCICLK", "9 PCICLCK",
215 "10 PCICLK", "11 PCICLK",
216 "13 PCICLK", "14 PCICLK",
217 "15 PCICLK", "15 PCICLK"
218};
219
220static char* active_time[] = {
221 "8 PCICLK", "1 PCICLCK",
222 "2 PCICLK", "3 PCICLK",
223 "4 PCICLK", "5 PCICLK",
224 "6 PCICLK", "12 PCICLK"
225};
226
227static char* cycle_time[] = {
228 "Reserved", "2 CLK",
229 "3 CLK", "4 CLK",
230 "5 CLK", "6 CLK",
231 "7 CLK", "8 CLK",
232 "9 CLK", "10 CLK",
233 "11 CLK", "12 CLK",
234 "13 CLK", "14 CLK",
235 "15 CLK", "16 CLK"
236};
237
238/* Generic add master or slave info function */
239static char* get_drives_info (char *buffer, u8 pos)
240{
241 u8 reg00, reg01, reg10, reg11; /* timing registers */
242 u32 regdw0, regdw1;
243 char* p = buffer;
244
245/* Postwrite/Prefetch */
246 if (chipset_family < ATA_133) {
247 pci_read_config_byte(bmide_dev, 0x4b, &reg00);
248 p += sprintf(p, "Drive %d: Postwrite %s \t \t Postwrite %s\n",
249 pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled",
250 (reg00 & (0x40 << pos)) ? "Enabled" : "Disabled");
251 p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
252 (reg00 & (0x01 << pos)) ? "Enabled" : "Disabled",
253 (reg00 & (0x04 << pos)) ? "Enabled" : "Disabled");
254 pci_read_config_byte(bmide_dev, 0x40+2*pos, &reg00);
255 pci_read_config_byte(bmide_dev, 0x41+2*pos, &reg01);
256 pci_read_config_byte(bmide_dev, 0x44+2*pos, &reg10);
257 pci_read_config_byte(bmide_dev, 0x45+2*pos, &reg11);
258 } else {
259 u32 reg54h;
260 u8 drive_pci = 0x40;
261 pci_read_config_dword(bmide_dev, 0x54, &reg54h);
262 if (reg54h & 0x40000000) {
263 // Configuration space remapped to 0x70
264 drive_pci = 0x70;
265 }
266 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos, &regdw0);
267 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos+8, &regdw1);
268
269 p += sprintf(p, "Drive %d:\n", pos);
270 }
271
272
273/* UDMA */
274 if (chipset_family >= ATA_133) {
275 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
276 (regdw0 & 0x04) ? "Enabled" : "Disabled",
277 (regdw1 & 0x04) ? "Enabled" : "Disabled");
278 p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
279 cycle_time[(regdw0 & 0xF0) >> 4],
280 cycle_time[(regdw1 & 0xF0) >> 4]);
281 } else if (chipset_family >= ATA_33) {
282 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
283 (reg01 & 0x80) ? "Enabled" : "Disabled",
284 (reg11 & 0x80) ? "Enabled" : "Disabled");
285
286 p += sprintf(p, " UDMA Cycle Time ");
287 switch(chipset_family) {
288 case ATA_33: p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break;
289 case ATA_66:
290 case ATA_100a: p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break;
291 case ATA_100:
292 case ATA_133a: p += sprintf(p, cycle_time[reg01 & 0x0F]); break;
293 default: p += sprintf(p, "?"); break;
294 }
295 p += sprintf(p, " \t UDMA Cycle Time ");
296 switch(chipset_family) {
297 case ATA_33: p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break;
298 case ATA_66:
299 case ATA_100a: p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break;
300 case ATA_100:
301 case ATA_133a: p += sprintf(p, cycle_time[reg11 & 0x0F]); break;
302 default: p += sprintf(p, "?"); break;
303 }
304 p += sprintf(p, "\n");
305 }
306
307
308 if (chipset_family < ATA_133) { /* else case TODO */
309
310/* Data Active */
311 p += sprintf(p, " Data Active Time ");
312 switch(chipset_family) {
313 case ATA_16: /* confirmed */
314 case ATA_33:
315 case ATA_66:
316 case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break;
317 case ATA_100:
318 case ATA_133a: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break;
319 default: p += sprintf(p, "?"); break;
320 }
321 p += sprintf(p, " \t Data Active Time ");
322 switch(chipset_family) {
323 case ATA_16:
324 case ATA_33:
325 case ATA_66:
326 case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break;
327 case ATA_100:
328 case ATA_133a: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break;
329 default: p += sprintf(p, "?"); break;
330 }
331 p += sprintf(p, "\n");
332
333/* Data Recovery */
334 /* warning: may need (reg&0x07) for pre ATA66 chips */
335 p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
336 recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]);
337 }
338
339 return p;
340}
341
342static char* get_masters_info(char* buffer)
343{
344 return get_drives_info(buffer, 0);
345}
346
347static char* get_slaves_info(char* buffer)
348{
349 return get_drives_info(buffer, 1);
350}
351
352/* Main get_info, called on /proc/ide/sis reads */
353static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
354{
355 char *p = buffer;
356 int len;
357 u8 reg;
358 u16 reg2, reg3;
359
360 p += sprintf(p, "\nSiS 5513 ");
361 switch(chipset_family) {
362 case ATA_16: p += sprintf(p, "DMA 16"); break;
363 case ATA_33: p += sprintf(p, "Ultra 33"); break;
364 case ATA_66: p += sprintf(p, "Ultra 66"); break;
365 case ATA_100a:
366 case ATA_100: p += sprintf(p, "Ultra 100"); break;
367 case ATA_133a:
368 case ATA_133: p += sprintf(p, "Ultra 133"); break;
369 default: p+= sprintf(p, "Unknown???"); break;
370 }
371 p += sprintf(p, " chipset\n");
372 p += sprintf(p, "--------------- Primary Channel "
373 "---------------- Secondary Channel "
374 "-------------\n");
375
376/* Status */
377 pci_read_config_byte(bmide_dev, 0x4a, &reg);
378 if (chipset_family == ATA_133) {
379 pci_read_config_word(bmide_dev, 0x50, &reg2);
380 pci_read_config_word(bmide_dev, 0x52, &reg3);
381 }
382 p += sprintf(p, "Channel Status: ");
383 if (chipset_family < ATA_66) {
384 p += sprintf(p, "%s \t \t \t \t %s\n",
385 (reg & 0x04) ? "On" : "Off",
386 (reg & 0x02) ? "On" : "Off");
387 } else if (chipset_family < ATA_133) {
388 p += sprintf(p, "%s \t \t \t \t %s \n",
389 (reg & 0x02) ? "On" : "Off",
390 (reg & 0x04) ? "On" : "Off");
391 } else { /* ATA_133 */
392 p += sprintf(p, "%s \t \t \t \t %s \n",
393 (reg2 & 0x02) ? "On" : "Off",
394 (reg3 & 0x02) ? "On" : "Off");
395 }
396
397/* Operation Mode */
398 pci_read_config_byte(bmide_dev, 0x09, &reg);
399 p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
400 (reg & 0x01) ? "Native" : "Compatible",
401 (reg & 0x04) ? "Native" : "Compatible");
402
403/* 80-pin cable ? */
404 if (chipset_family >= ATA_133) {
405 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
406 (reg2 & 0x01) ? cable_type[1] : cable_type[0],
407 (reg3 & 0x01) ? cable_type[1] : cable_type[0]);
408 } else if (chipset_family > ATA_33) {
409 pci_read_config_byte(bmide_dev, 0x48, &reg);
410 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
411 (reg & 0x10) ? cable_type[1] : cable_type[0],
412 (reg & 0x20) ? cable_type[1] : cable_type[0]);
413 }
414
415/* Prefetch Count */
416 if (chipset_family < ATA_133) {
417 pci_read_config_word(bmide_dev, 0x4c, &reg2);
418 pci_read_config_word(bmide_dev, 0x4e, &reg3);
419 p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
420 reg2, reg3);
421 }
422
423 p = get_masters_info(p);
424 p = get_slaves_info(p);
425
426 len = (p - buffer) - offset;
427 *addr = buffer + offset;
428
429 return len > count ? count : len;
430}
ecfd80e4 431#endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
1da177e4 432
1da177e4
LT		 433/*
434 * Configuration functions
435 */
436/* Enables per-drive prefetch and postwrite */
437static void config_drive_art_rwp (ide_drive_t *drive)
438{
439 ide_hwif_t *hwif = HWIF(drive);
440 struct pci_dev *dev = hwif->pci_dev;
441
442 u8 reg4bh = 0;
443 u8 rw_prefetch = (0x11 << drive->dn);
444
445 if (drive->media != ide_disk)
446 return;
447 pci_read_config_byte(dev, 0x4b, &reg4bh);
448
449 if ((reg4bh & rw_prefetch) != rw_prefetch)
450 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
451}
452
1da177e4
LT		 453/* Set per-drive active and recovery time */
454static void config_art_rwp_pio (ide_drive_t *drive, u8 pio)
455{
456 ide_hwif_t *hwif = HWIF(drive);
457 struct pci_dev *dev = hwif->pci_dev;
458
6b8cf772 459 u8 drive_pci, test1, test2;
1da177e4
LT		 460
461 config_drive_art_rwp(drive);
1da177e4
LT		 462
463 /* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */
464 drive_pci = 0x40;
465 /* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */
466 if (chipset_family >= ATA_133) {
467 u32 reg54h;
468 pci_read_config_dword(dev, 0x54, &reg54h);
469 if (reg54h & 0x40000000) drive_pci = 0x70;
470 drive_pci += ((drive->dn)*0x4);
471 } else {
472 drive_pci += ((drive->dn)*0x2);
473 }
474
475 /* register layout changed with newer ATA100 chips */
476 if (chipset_family < ATA_100) {
477 pci_read_config_byte(dev, drive_pci, &test1);
478 pci_read_config_byte(dev, drive_pci+1, &test2);
479
480 /* Clear active and recovery timings */
481 test1 &= ~0x0F;
482 test2 &= ~0x07;
483
6b8cf772 484 switch(pio) {
1da177e4
LT		 485 case 4: test1 |= 0x01; test2 |= 0x03; break;
486 case 3: test1 |= 0x03; test2 |= 0x03; break;
487 case 2: test1 |= 0x04; test2 |= 0x04; break;
488 case 1: test1 |= 0x07; test2 |= 0x06; break;
6b8cf772 489 case 0: /* PIO0: register setting == X000 */
1da177e4
LT		 490 default: break;
491 }
492 pci_write_config_byte(dev, drive_pci, test1);
493 pci_write_config_byte(dev, drive_pci+1, test2);
494 } else if (chipset_family < ATA_133) {
6b8cf772 495 switch(pio) { /* active recovery
1da177e4
LT		 496 v v */
497 case 4: test1 = 0x30|0x01; break;
498 case 3: test1 = 0x30|0x03; break;
499 case 2: test1 = 0x40|0x04; break;
500 case 1: test1 = 0x60|0x07; break;
d266ab88 501 case 0: test1 = 0x00; break;
1da177e4
LT		 502 default: break;
503 }
504 pci_write_config_byte(dev, drive_pci, test1);
505 } else { /* ATA_133 */
506 u32 test3;
507 pci_read_config_dword(dev, drive_pci, &test3);
508 test3 &= 0xc0c00fff;
509 if (test3 & 0x08) {
6b8cf772
BZ		 510 test3 |= ini_time_value[ATA_133][pio] << 12;
511 test3 |= act_time_value[ATA_133][pio] << 16;
512 test3 |= rco_time_value[ATA_133][pio] << 24;
1da177e4 513 } else {
6b8cf772
BZ		 514 test3 |= ini_time_value[ATA_100][pio] << 12;
515 test3 |= act_time_value[ATA_100][pio] << 16;
516 test3 |= rco_time_value[ATA_100][pio] << 24;
1da177e4
LT		 517 }
518 pci_write_config_dword(dev, drive_pci, test3);
519 }
520}
521
6b8cf772 522static int sis5513_tune_drive(ide_drive_t *drive, u8 pio)
1da177e4 523{
2134758d 524 pio = ide_get_best_pio_mode(drive, pio, 4);
1da177e4 525 config_art_rwp_pio(drive, pio);
6b8cf772
BZ		 526 return ide_config_drive_speed(drive, XFER_PIO_0 + pio);
527}
528
529static void sis5513_tuneproc(ide_drive_t *drive, u8 pio)
530{
531 (void)sis5513_tune_drive(drive, pio);
1da177e4
LT		 532}
533
534static int sis5513_tune_chipset (ide_drive_t *drive, u8 xferspeed)
535{
536 ide_hwif_t *hwif = HWIF(drive);
537 struct pci_dev *dev = hwif->pci_dev;
538
539 u8 drive_pci, reg, speed;
540 u32 regdw;
541
2d5eaa6d 542 speed = ide_rate_filter(drive, xferspeed);
1da177e4
LT		 543
544 /* See config_art_rwp_pio for drive pci config registers */
545 drive_pci = 0x40;
546 if (chipset_family >= ATA_133) {
547 u32 reg54h;
548 pci_read_config_dword(dev, 0x54, &reg54h);
549 if (reg54h & 0x40000000) drive_pci = 0x70;
550 drive_pci += ((drive->dn)*0x4);
551 pci_read_config_dword(dev, (unsigned long)drive_pci, &regdw);
552 /* Disable UDMA bit for non UDMA modes on UDMA chips */
553 if (speed < XFER_UDMA_0) {
554 regdw &= 0xfffffffb;
555 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
556 }
557
558 } else {
559 drive_pci += ((drive->dn)*0x2);
560 pci_read_config_byte(dev, drive_pci+1, &reg);
561 /* Disable UDMA bit for non UDMA modes on UDMA chips */
562 if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) {
563 reg &= 0x7F;
564 pci_write_config_byte(dev, drive_pci+1, reg);
565 }
566 }
567
568 /* Config chip for mode */
569 switch(speed) {
570 case XFER_UDMA_6:
571 case XFER_UDMA_5:
572 case XFER_UDMA_4:
573 case XFER_UDMA_3:
574 case XFER_UDMA_2:
575 case XFER_UDMA_1:
576 case XFER_UDMA_0:
577 if (chipset_family >= ATA_133) {
578 regdw |= 0x04;
579 regdw &= 0xfffff00f;
580 /* check if ATA133 enable */
581 if (regdw & 0x08) {
582 regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4;
583 regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8;
584 } else {
585 /* if ATA133 disable, we should not set speed above UDMA5 */
586 if (speed > XFER_UDMA_5)
587 speed = XFER_UDMA_5;
588 regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4;
589 regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8;
590 }
591 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
592 } else {
593 /* Force the UDMA bit on if we want to use UDMA */
594 reg |= 0x80;
595 /* clean reg cycle time bits */
596 reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family]))
597 << cycle_time_offset[chipset_family]);
598 /* set reg cycle time bits */
599 reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0]
600 << cycle_time_offset[chipset_family];
601 pci_write_config_byte(dev, drive_pci+1, reg);
602 }
603 break;
604 case XFER_MW_DMA_2:
605 case XFER_MW_DMA_1:
606 case XFER_MW_DMA_0:
607 case XFER_SW_DMA_2:
608 case XFER_SW_DMA_1:
609 case XFER_SW_DMA_0:
610 break;
6b8cf772
BZ		 611 case XFER_PIO_4:
612 case XFER_PIO_3:
613 case XFER_PIO_2:
614 case XFER_PIO_1:
1da177e4 615 case XFER_PIO_0:
6b8cf772
BZ		 616 return sis5513_tune_drive(drive, speed - XFER_PIO_0);
617 default:
618 BUG();
619 break;
1da177e4
LT		 620 }
621
6b8cf772 622 return ide_config_drive_speed(drive, speed);
1da177e4
LT		 623}
624
ac4a3065 625static int sis5513_config_xfer_rate(ide_drive_t *drive)
1da177e4 626{
6b8cf772
BZ		 627 /*
628 * TODO: always set PIO mode and remove this
629 */
630 sis5513_tuneproc(drive, 255);
ac4a3065 631
1da177e4
LT		 632 drive->init_speed = 0;
633
29e744d0 634 if (ide_tune_dma(drive))
3608b5d7 635 return 0;
1da177e4 636
d8f4469d 637 if (ide_use_fast_pio(drive))
6b8cf772 638 sis5513_tuneproc(drive, 255);
d8f4469d 639
3608b5d7 640 return -1;
1da177e4
LT		 641}
642
1da177e4 643/* Chip detection and general config */
2b0c4bed 644static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name)
1da177e4
LT		 645{
646 struct pci_dev *host;
647 int i = 0;
648
649 chipset_family = 0;
650
651 for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
652
40cddf2c 653 host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
1da177e4
LT		 654
655 if (!host)
656 continue;
657
658 chipset_family = SiSHostChipInfo[i].chipset_family;
659
660 /* Special case for SiS630 : 630S/ET is ATA_100a */
661 if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
44c10138 662 if (host->revision >= 0x30)
1da177e4
LT		 663 chipset_family = ATA_100a;
664 }
40cddf2c 665 pci_dev_put(host);
1da177e4
LT		 666
667 printk(KERN_INFO "SIS5513: %s %s controller\n",
668 SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
669 }
670
671 if (!chipset_family) { /* Belongs to pci-quirks */
672
673 u32 idemisc;
674 u16 trueid;
675
676 /* Disable ID masking and register remapping */
677 pci_read_config_dword(dev, 0x54, &idemisc);
678 pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
679 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
680 pci_write_config_dword(dev, 0x54, idemisc);
681
682 if (trueid == 0x5518) {
683 printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
684 chipset_family = ATA_133;
685
686 /* Check for 5513 compability mapping
687 * We must use this, else the port enabled code will fail,
688 * as it expects the enablebits at 0x4a.
689 */
690 if ((idemisc & 0x40000000) == 0) {
691 pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
692 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
693 }
694 }
695 }
696
697 if (!chipset_family) { /* Belongs to pci-quirks */
698
699 struct pci_dev *lpc_bridge;
700 u16 trueid;
701 u8 prefctl;
702 u8 idecfg;
1da177e4
LT		 703
704 pci_read_config_byte(dev, 0x4a, &idecfg);
705 pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
706 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
707 pci_write_config_byte(dev, 0x4a, idecfg);
708
709 if (trueid == 0x5517) { /* SiS 961/961B */
710
b1489009 711 lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
1da177e4 712 pci_read_config_byte(dev, 0x49, &prefctl);
b1489009 713 pci_dev_put(lpc_bridge);
1da177e4 714
44c10138 715 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
1da177e4
LT		 716 printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
717 chipset_family = ATA_133a;
718 } else {
719 printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
720 chipset_family = ATA_100;
721 }
722 }
723 }
724
725 if (!chipset_family)
726 return -1;
727
728 /* Make general config ops here
729 1/ tell IDE channels to operate in Compatibility mode only
730 2/ tell old chips to allow per drive IDE timings */
731
732 {
733 u8 reg;
734 u16 regw;
735
736 switch(chipset_family) {
737 case ATA_133:
738 /* SiS962 operation mode */
739 pci_read_config_word(dev, 0x50, &regw);
740 if (regw & 0x08)
741 pci_write_config_word(dev, 0x50, regw&0xfff7);
742 pci_read_config_word(dev, 0x52, &regw);
743 if (regw & 0x08)
744 pci_write_config_word(dev, 0x52, regw&0xfff7);
745 break;
746 case ATA_133a:
747 case ATA_100:
748 /* Fixup latency */
749 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
750 /* Set compatibility bit */
751 pci_read_config_byte(dev, 0x49, &reg);
752 if (!(reg & 0x01)) {
753 pci_write_config_byte(dev, 0x49, reg|0x01);
754 }
755 break;
756 case ATA_100a:
757 case ATA_66:
758 /* Fixup latency */
759 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
760
761 /* On ATA_66 chips the bit was elsewhere */
762 pci_read_config_byte(dev, 0x52, &reg);
763 if (!(reg & 0x04)) {
764 pci_write_config_byte(dev, 0x52, reg|0x04);
765 }
766 break;
767 case ATA_33:
768 /* On ATA_33 we didn't have a single bit to set */
769 pci_read_config_byte(dev, 0x09, &reg);
770 if ((reg & 0x0f) != 0x00) {
771 pci_write_config_byte(dev, 0x09, reg&0xf0);
772 }
773 case ATA_16:
774 /* force per drive recovery and active timings
775 needed on ATA_33 and below chips */
776 pci_read_config_byte(dev, 0x52, &reg);
777 if (!(reg & 0x08)) {
778 pci_write_config_byte(dev, 0x52, reg|0x08);
779 }
780 break;
781 }
782
ecfd80e4 783#if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
1da177e4
LT		 784 if (!sis_proc) {
785 sis_proc = 1;
786 bmide_dev = dev;
787 ide_pci_create_host_proc("sis", sis_get_info);
788 }
789#endif
790 }
791
792 return 0;
793}
794
f2befd9e
BZ		 795struct sis_laptop {
796 u16 device;
797 u16 subvendor;
798 u16 subdevice;
799};
800
801static const struct sis_laptop sis_laptop[] = {
802 /* devid, subvendor, subdev */
803 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
1955f681 804 { 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */
f2befd9e
BZ		 805 /* end marker */
806 { 0, }
807};
808
49521f97 809static u8 __devinit ata66_sis5513(ide_hwif_t *hwif)
1da177e4 810{
f2befd9e
BZ		 811 struct pci_dev *pdev = hwif->pci_dev;
812 const struct sis_laptop *lap = &sis_laptop[0];
1da177e4
LT		 813 u8 ata66 = 0;
814
f2befd9e
BZ		 815 while (lap->device) {
816 if (lap->device == pdev->device &&
817 lap->subvendor == pdev->subsystem_vendor &&
818 lap->subdevice == pdev->subsystem_device)
819 return ATA_CBL_PATA40_SHORT;
820 lap++;
821 }
822
1da177e4
LT		 823 if (chipset_family >= ATA_133) {
824 u16 regw = 0;
825 u16 reg_addr = hwif->channel ? 0x52: 0x50;
826 pci_read_config_word(hwif->pci_dev, reg_addr, &regw);
827 ata66 = (regw & 0x8000) ? 0 : 1;
828 } else if (chipset_family >= ATA_66) {
829 u8 reg48h = 0;
830 u8 mask = hwif->channel ? 0x20 : 0x10;
831 pci_read_config_byte(hwif->pci_dev, 0x48, &reg48h);
832 ata66 = (reg48h & mask) ? 0 : 1;
833 }
49521f97
BZ		 834
835 return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
1da177e4
LT		 836}
837
2b0c4bed 838static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
1da177e4 839{
18137207
BZ		 840 u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
841
1da177e4
LT		 842 hwif->autodma = 0;
843
844 if (!hwif->irq)
845 hwif->irq = hwif->channel ? 15 : 14;
846
6b8cf772 847 hwif->tuneproc = &sis5513_tuneproc;
1da177e4
LT		 848 hwif->speedproc = &sis5513_tune_chipset;
849
850 if (!(hwif->dma_base)) {
851 hwif->drives[0].autotune = 1;
852 hwif->drives[1].autotune = 1;
853 return;
854 }
855
856 hwif->atapi_dma = 1;
18137207
BZ		 857
858 hwif->ultra_mask = udma_rates[chipset_family];
1da177e4
LT		 859 hwif->mwdma_mask = 0x07;
860 hwif->swdma_mask = 0x07;
861
862 if (!chipset_family)
863 return;
864
49521f97
BZ		 865 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
866 hwif->cbl = ata66_sis5513(hwif);
1da177e4
LT		 867
868 if (chipset_family > ATA_16) {
869 hwif->ide_dma_check = &sis5513_config_xfer_rate;
870 if (!noautodma)
871 hwif->autodma = 1;
872 }
873 hwif->drives[0].autodma = hwif->autodma;
874 hwif->drives[1].autodma = hwif->autodma;
875 return;
876}
877
878static ide_pci_device_t sis5513_chipset __devinitdata = {
879 .name = "SIS5513",
880 .init_chipset = init_chipset_sis5513,
881 .init_hwif = init_hwif_sis5513,
1da177e4
LT		 882 .autodma = NOAUTODMA,
883 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
884 .bootable = ON_BOARD,
4099d143 885 .pio_mask = ATA_PIO4,
1da177e4
LT		 886};
887
888static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
889{
890 return ide_setup_pci_device(dev, &sis5513_chipset);
891}
892
893static struct pci_device_id sis5513_pci_tbl[] = {
894 { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
895 { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5518, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
4c6c914e 896 { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_1180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4
LT		 897 { 0, },
898};
899MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
900
901static struct pci_driver driver = {
902 .name = "SIS_IDE",
903 .id_table = sis5513_pci_tbl,
904 .probe = sis5513_init_one,
905};
906
82ab1eec 907static int __init sis5513_ide_init(void)
1da177e4
LT		 908{
909 return ide_pci_register_driver(&driver);
910}
911
912module_init(sis5513_ide_init);
913
914MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
915MODULE_DESCRIPTION("PCI driver module for SIS IDE");
916MODULE_LICENSE("GPL");
917
918/*
919 * TODO:
920 * - CLEANUP
921 * - Use drivers/ide/ide-timing.h !
922 * - More checks in the config registers (force values instead of
923 * relying on the BIOS setting them correctly).
924 * - Further optimisations ?
925 * . for example ATA66+ regs 0x48 & 0x4A
926 */
kernel source for telekom puls (alcatel/mediatek)