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1da177e4 | 1 | /* |
a718122c | 2 | * linux/drivers/ide/pci/sis5513.c Version 0.31 Aug 9, 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
5 | * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer | |
6 | * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> | |
6b8cf772 BZ |
7 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
8 | * | |
1da177e4 LT |
9 | * May be copied or modified under the terms of the GNU General Public License |
10 | * | |
11 | * | |
12 | * Thanks : | |
13 | * | |
14 | * SiS Taiwan : for direct support and hardware. | |
15 | * Daniela Engert : for initial ATA100 advices and numerous others. | |
16 | * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : | |
17 | * for checking code correctness, providing patches. | |
18 | * | |
19 | * | |
20 | * Original tests and design on the SiS620 chipset. | |
21 | * ATA100 tests and design on the SiS735 chipset. | |
22 | * ATA16/33 support from specs | |
23 | * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> | |
24 | * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz> | |
25 | * | |
26 | * Documentation: | |
27 | * SiS chipset documentation available under NDA to companies only | |
28 | * (not to individuals). | |
29 | */ | |
30 | ||
31 | /* | |
32 | * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original | |
33 | * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511 | |
34 | * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip. | |
35 | * | |
36 | * Later SiS chipsets integrated the 5513 functionality into the NorthBridge, | |
37 | * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We | |
38 | * can figure out that we have a more modern and more capable 5513 by looking | |
39 | * for the respective NorthBridge IDs. | |
40 | * | |
41 | * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513 | |
42 | * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI | |
43 | * ID, while the now ATA-133 capable 5513 still has the same PCI ID. | |
44 | * Fortunately the 5513 can be 'unmasked' by fiddling with some config space | |
45 | * bits, changing its device id to the true one - 5517 for 961 and 5518 for | |
46 | * 962/963. | |
47 | */ | |
48 | ||
1da177e4 LT |
49 | #include <linux/types.h> |
50 | #include <linux/module.h> | |
51 | #include <linux/kernel.h> | |
52 | #include <linux/delay.h> | |
53 | #include <linux/timer.h> | |
54 | #include <linux/mm.h> | |
55 | #include <linux/ioport.h> | |
56 | #include <linux/blkdev.h> | |
57 | #include <linux/hdreg.h> | |
58 | ||
59 | #include <linux/interrupt.h> | |
60 | #include <linux/pci.h> | |
61 | #include <linux/init.h> | |
62 | #include <linux/ide.h> | |
63 | ||
64 | #include <asm/irq.h> | |
65 | ||
66 | #include "ide-timing.h" | |
67 | ||
1da177e4 LT |
68 | /* registers layout and init values are chipset family dependant */ |
69 | ||
70 | #define ATA_16 0x01 | |
71 | #define ATA_33 0x02 | |
72 | #define ATA_66 0x03 | |
73 | #define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout | |
74 | #define ATA_100 0x05 | |
75 | #define ATA_133a 0x06 // SiS961b with 133 support | |
76 | #define ATA_133 0x07 // SiS962/963 | |
77 | ||
78 | static u8 chipset_family; | |
79 | ||
80 | /* | |
81 | * Devices supported | |
82 | */ | |
83 | static const struct { | |
84 | const char *name; | |
85 | u16 host_id; | |
86 | u8 chipset_family; | |
87 | u8 flags; | |
88 | } SiSHostChipInfo[] = { | |
47d4b906 DW |
89 | { "SiS968", PCI_DEVICE_ID_SI_968, ATA_133 }, |
90 | { "SiS966", PCI_DEVICE_ID_SI_966, ATA_133 }, | |
14351f8e | 91 | { "SiS965", PCI_DEVICE_ID_SI_965, ATA_133 }, |
1da177e4 LT |
92 | { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 }, |
93 | { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 }, | |
94 | { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 }, | |
95 | { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 }, | |
96 | { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 }, | |
97 | ||
98 | { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a }, | |
99 | { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a }, | |
100 | ||
101 | { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 }, | |
102 | { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 }, | |
103 | { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 }, | |
104 | { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 }, | |
105 | { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 }, | |
106 | ||
107 | { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 }, | |
108 | { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 }, | |
109 | { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 }, | |
110 | { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 }, | |
111 | { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 }, | |
112 | { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 }, | |
113 | ||
114 | { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 }, | |
115 | { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 }, | |
d266ab88 | 116 | { "SiS5517", PCI_DEVICE_ID_SI_5517, ATA_16 }, |
1da177e4 LT |
117 | { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 }, |
118 | }; | |
119 | ||
120 | /* Cycle time bits and values vary across chip dma capabilities | |
121 | These three arrays hold the register layout and the values to set. | |
122 | Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */ | |
123 | ||
124 | /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */ | |
125 | static u8 cycle_time_offset[] = {0,0,5,4,4,0,0}; | |
126 | static u8 cycle_time_range[] = {0,0,2,3,3,4,4}; | |
127 | static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = { | |
128 | {0,0,0,0,0,0,0}, /* no udma */ | |
129 | {0,0,0,0,0,0,0}, /* no udma */ | |
130 | {3,2,1,0,0,0,0}, /* ATA_33 */ | |
131 | {7,5,3,2,1,0,0}, /* ATA_66 */ | |
132 | {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */ | |
133 | {11,7,5,4,2,1,0}, /* ATA_100 */ | |
134 | {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */ | |
135 | {15,10,7,5,3,2,1}, /* ATA_133 */ | |
136 | }; | |
137 | /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133 | |
138 | See SiS962 data sheet for more detail */ | |
139 | static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = { | |
140 | {0,0,0,0,0,0,0}, /* no udma */ | |
141 | {0,0,0,0,0,0,0}, /* no udma */ | |
142 | {2,1,1,0,0,0,0}, | |
143 | {4,3,2,1,0,0,0}, | |
144 | {4,3,2,1,0,0,0}, | |
145 | {6,4,3,1,1,1,0}, | |
146 | {9,6,4,2,2,2,2}, | |
147 | {9,6,4,2,2,2,2}, | |
148 | }; | |
149 | /* Initialize time, Active time, Recovery time vary across | |
150 | IDE clock settings. These 3 arrays hold the register value | |
151 | for PIO0/1/2/3/4 and DMA0/1/2 mode in order */ | |
152 | static u8 ini_time_value[][8] = { | |
153 | {0,0,0,0,0,0,0,0}, | |
154 | {0,0,0,0,0,0,0,0}, | |
155 | {2,1,0,0,0,1,0,0}, | |
156 | {4,3,1,1,1,3,1,1}, | |
157 | {4,3,1,1,1,3,1,1}, | |
158 | {6,4,2,2,2,4,2,2}, | |
159 | {9,6,3,3,3,6,3,3}, | |
160 | {9,6,3,3,3,6,3,3}, | |
161 | }; | |
162 | static u8 act_time_value[][8] = { | |
163 | {0,0,0,0,0,0,0,0}, | |
164 | {0,0,0,0,0,0,0,0}, | |
165 | {9,9,9,2,2,7,2,2}, | |
166 | {19,19,19,5,4,14,5,4}, | |
167 | {19,19,19,5,4,14,5,4}, | |
168 | {28,28,28,7,6,21,7,6}, | |
169 | {38,38,38,10,9,28,10,9}, | |
170 | {38,38,38,10,9,28,10,9}, | |
171 | }; | |
172 | static u8 rco_time_value[][8] = { | |
173 | {0,0,0,0,0,0,0,0}, | |
174 | {0,0,0,0,0,0,0,0}, | |
175 | {9,2,0,2,0,7,1,1}, | |
176 | {19,5,1,5,2,16,3,2}, | |
177 | {19,5,1,5,2,16,3,2}, | |
178 | {30,9,3,9,4,25,6,4}, | |
179 | {40,12,4,12,5,34,12,5}, | |
180 | {40,12,4,12,5,34,12,5}, | |
181 | }; | |
182 | ||
183 | /* | |
184 | * Printing configuration | |
185 | */ | |
186 | /* Used for chipset type printing at boot time */ | |
187 | static char* chipset_capability[] = { | |
188 | "ATA", "ATA 16", | |
189 | "ATA 33", "ATA 66", | |
190 | "ATA 100 (1st gen)", "ATA 100 (2nd gen)", | |
191 | "ATA 133 (1st gen)", "ATA 133 (2nd gen)" | |
192 | }; | |
193 | ||
1da177e4 LT |
194 | /* |
195 | * Configuration functions | |
196 | */ | |
c77a89cd BZ |
197 | |
198 | static u8 sis_ata133_get_base(ide_drive_t *drive) | |
199 | { | |
200 | struct pci_dev *dev = drive->hwif->pci_dev; | |
201 | u32 reg54 = 0; | |
202 | ||
203 | pci_read_config_dword(dev, 0x54, ®54); | |
204 | ||
205 | return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4; | |
206 | } | |
207 | ||
208 | static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode) | |
209 | { | |
210 | struct pci_dev *dev = drive->hwif->pci_dev; | |
211 | u16 t1 = 0; | |
212 | u8 drive_pci = 0x40 + drive->dn * 2; | |
213 | ||
214 | const u16 pio_timings[] = { 0x000, 0x607, 0x404, 0x303, 0x301 }; | |
215 | const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 }; | |
216 | ||
217 | pci_read_config_word(dev, drive_pci, &t1); | |
218 | ||
219 | /* clear active/recovery timings */ | |
220 | t1 &= ~0x070f; | |
221 | if (mode >= XFER_MW_DMA_0) { | |
222 | if (chipset_family > ATA_16) | |
223 | t1 &= ~0x8000; /* disable UDMA */ | |
224 | t1 |= mwdma_timings[mode - XFER_MW_DMA_0]; | |
225 | } else | |
226 | t1 |= pio_timings[mode - XFER_PIO_0]; | |
227 | ||
228 | pci_write_config_word(dev, drive_pci, t1); | |
229 | } | |
230 | ||
231 | static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode) | |
232 | { | |
233 | struct pci_dev *dev = drive->hwif->pci_dev; | |
234 | u8 t1, drive_pci = 0x40 + drive->dn * 2; | |
235 | ||
236 | /* timing bits: 7:4 active 3:0 recovery */ | |
237 | const u8 pio_timings[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; | |
238 | const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 }; | |
239 | ||
240 | if (mode >= XFER_MW_DMA_0) { | |
241 | u8 t2 = 0; | |
242 | ||
243 | pci_read_config_byte(dev, drive_pci, &t2); | |
244 | t2 &= ~0x80; /* disable UDMA */ | |
245 | pci_write_config_byte(dev, drive_pci, t2); | |
246 | ||
247 | t1 = mwdma_timings[mode - XFER_MW_DMA_0]; | |
248 | } else | |
249 | t1 = pio_timings[mode - XFER_PIO_0]; | |
250 | ||
251 | pci_write_config_byte(dev, drive_pci + 1, t1); | |
252 | } | |
253 | ||
254 | static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode) | |
255 | { | |
256 | struct pci_dev *dev = drive->hwif->pci_dev; | |
257 | u32 t1 = 0; | |
258 | u8 drive_pci = sis_ata133_get_base(drive), clk, idx; | |
259 | ||
260 | pci_read_config_dword(dev, drive_pci, &t1); | |
261 | ||
262 | t1 &= 0xc0c00fff; | |
263 | clk = (t1 & 0x08) ? ATA_133 : ATA_100; | |
264 | if (mode >= XFER_MW_DMA_0) { | |
265 | t1 &= ~0x04; /* disable UDMA */ | |
266 | idx = mode - XFER_MW_DMA_0 + 5; | |
3dfd6433 | 267 | } else |
c77a89cd BZ |
268 | idx = mode - XFER_PIO_0; |
269 | t1 |= ini_time_value[clk][idx] << 12; | |
270 | t1 |= act_time_value[clk][idx] << 16; | |
271 | t1 |= rco_time_value[clk][idx] << 24; | |
272 | ||
273 | pci_write_config_dword(dev, drive_pci, t1); | |
274 | } | |
275 | ||
276 | static void sis_program_timings(ide_drive_t *drive, const u8 mode) | |
277 | { | |
278 | if (chipset_family < ATA_100) /* ATA_16/33/66/100a */ | |
279 | sis_ata16_program_timings(drive, mode); | |
280 | else if (chipset_family < ATA_133) /* ATA_100/133a */ | |
281 | sis_ata100_program_timings(drive, mode); | |
282 | else /* ATA_133 */ | |
283 | sis_ata133_program_timings(drive, mode); | |
284 | } | |
285 | ||
1da177e4 LT |
286 | static void config_drive_art_rwp (ide_drive_t *drive) |
287 | { | |
288 | ide_hwif_t *hwif = HWIF(drive); | |
289 | struct pci_dev *dev = hwif->pci_dev; | |
1da177e4 | 290 | u8 reg4bh = 0; |
d83fca58 | 291 | u8 rw_prefetch = 0; |
1da177e4 | 292 | |
1da177e4 LT |
293 | pci_read_config_byte(dev, 0x4b, ®4bh); |
294 | ||
d83fca58 BZ |
295 | if (drive->media == ide_disk) |
296 | rw_prefetch = 0x11 << drive->dn; | |
297 | ||
298 | if ((reg4bh & (0x11 << drive->dn)) != rw_prefetch) | |
1da177e4 LT |
299 | pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch); |
300 | } | |
301 | ||
88b2b32b | 302 | static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 303 | { |
1da177e4 | 304 | config_drive_art_rwp(drive); |
c77a89cd | 305 | sis_program_timings(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
306 | } |
307 | ||
428c6440 | 308 | static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode) |
1da177e4 | 309 | { |
428c6440 BZ |
310 | struct pci_dev *dev = drive->hwif->pci_dev; |
311 | u32 regdw = 0; | |
312 | u8 drive_pci = sis_ata133_get_base(drive), clk, idx; | |
313 | ||
314 | pci_read_config_dword(dev, drive_pci, ®dw); | |
315 | ||
316 | regdw |= 0x04; | |
317 | regdw &= 0xfffff00f; | |
318 | /* check if ATA133 enable */ | |
319 | clk = (regdw & 0x08) ? ATA_133 : ATA_100; | |
320 | idx = mode - XFER_UDMA_0; | |
321 | regdw |= cycle_time_value[clk][idx] << 4; | |
322 | regdw |= cvs_time_value[clk][idx] << 8; | |
323 | ||
324 | pci_write_config_dword(dev, drive_pci, regdw); | |
325 | } | |
326 | ||
327 | static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode) | |
328 | { | |
329 | struct pci_dev *dev = drive->hwif->pci_dev; | |
330 | u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family; | |
331 | ||
332 | pci_read_config_byte(dev, drive_pci + 1, ®); | |
333 | ||
334 | /* force the UDMA bit on if we want to use UDMA */ | |
335 | reg |= 0x80; | |
336 | /* clean reg cycle time bits */ | |
337 | reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]); | |
338 | /* set reg cycle time bits */ | |
339 | reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i]; | |
340 | ||
341 | pci_write_config_byte(dev, drive_pci + 1, reg); | |
342 | } | |
1da177e4 | 343 | |
428c6440 BZ |
344 | static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode) |
345 | { | |
346 | if (chipset_family >= ATA_133) /* ATA_133 */ | |
347 | sis_ata133_program_udma_timings(drive, mode); | |
348 | else /* ATA_33/66/100a/100/133a */ | |
349 | sis_ata33_program_udma_timings(drive, mode); | |
350 | } | |
351 | ||
352 | static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed) | |
353 | { | |
4db90a14 BZ |
354 | if (speed >= XFER_UDMA_0) |
355 | sis_program_udma_timings(drive, speed); | |
356 | else | |
357 | sis_program_timings(drive, speed); | |
1da177e4 LT |
358 | } |
359 | ||
3160d541 BZ |
360 | static u8 sis5513_ata133_udma_filter(ide_drive_t *drive) |
361 | { | |
362 | struct pci_dev *dev = drive->hwif->pci_dev; | |
c77a89cd BZ |
363 | u32 regdw = 0; |
364 | u8 drive_pci = sis_ata133_get_base(drive); | |
3160d541 | 365 | |
3160d541 BZ |
366 | pci_read_config_dword(dev, drive_pci, ®dw); |
367 | ||
368 | /* if ATA133 disable, we should not set speed above UDMA5 */ | |
369 | return (regdw & 0x08) ? ATA_UDMA6 : ATA_UDMA5; | |
370 | } | |
371 | ||
1da177e4 | 372 | /* Chip detection and general config */ |
2b0c4bed | 373 | static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name) |
1da177e4 LT |
374 | { |
375 | struct pci_dev *host; | |
376 | int i = 0; | |
377 | ||
378 | chipset_family = 0; | |
379 | ||
380 | for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) { | |
381 | ||
40cddf2c | 382 | host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL); |
1da177e4 LT |
383 | |
384 | if (!host) | |
385 | continue; | |
386 | ||
387 | chipset_family = SiSHostChipInfo[i].chipset_family; | |
388 | ||
389 | /* Special case for SiS630 : 630S/ET is ATA_100a */ | |
390 | if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) { | |
44c10138 | 391 | if (host->revision >= 0x30) |
1da177e4 LT |
392 | chipset_family = ATA_100a; |
393 | } | |
40cddf2c | 394 | pci_dev_put(host); |
1da177e4 LT |
395 | |
396 | printk(KERN_INFO "SIS5513: %s %s controller\n", | |
397 | SiSHostChipInfo[i].name, chipset_capability[chipset_family]); | |
398 | } | |
399 | ||
400 | if (!chipset_family) { /* Belongs to pci-quirks */ | |
401 | ||
402 | u32 idemisc; | |
403 | u16 trueid; | |
404 | ||
405 | /* Disable ID masking and register remapping */ | |
406 | pci_read_config_dword(dev, 0x54, &idemisc); | |
407 | pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff)); | |
408 | pci_read_config_word(dev, PCI_DEVICE_ID, &trueid); | |
409 | pci_write_config_dword(dev, 0x54, idemisc); | |
410 | ||
411 | if (trueid == 0x5518) { | |
412 | printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n"); | |
413 | chipset_family = ATA_133; | |
414 | ||
415 | /* Check for 5513 compability mapping | |
416 | * We must use this, else the port enabled code will fail, | |
417 | * as it expects the enablebits at 0x4a. | |
418 | */ | |
419 | if ((idemisc & 0x40000000) == 0) { | |
420 | pci_write_config_dword(dev, 0x54, idemisc | 0x40000000); | |
421 | printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); | |
422 | } | |
423 | } | |
424 | } | |
425 | ||
426 | if (!chipset_family) { /* Belongs to pci-quirks */ | |
427 | ||
428 | struct pci_dev *lpc_bridge; | |
429 | u16 trueid; | |
430 | u8 prefctl; | |
431 | u8 idecfg; | |
1da177e4 LT |
432 | |
433 | pci_read_config_byte(dev, 0x4a, &idecfg); | |
434 | pci_write_config_byte(dev, 0x4a, idecfg | 0x10); | |
435 | pci_read_config_word(dev, PCI_DEVICE_ID, &trueid); | |
436 | pci_write_config_byte(dev, 0x4a, idecfg); | |
437 | ||
438 | if (trueid == 0x5517) { /* SiS 961/961B */ | |
439 | ||
b1489009 | 440 | lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */ |
1da177e4 | 441 | pci_read_config_byte(dev, 0x49, &prefctl); |
b1489009 | 442 | pci_dev_put(lpc_bridge); |
1da177e4 | 443 | |
44c10138 | 444 | if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { |
1da177e4 LT |
445 | printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n"); |
446 | chipset_family = ATA_133a; | |
447 | } else { | |
448 | printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n"); | |
449 | chipset_family = ATA_100; | |
450 | } | |
451 | } | |
452 | } | |
453 | ||
454 | if (!chipset_family) | |
455 | return -1; | |
456 | ||
457 | /* Make general config ops here | |
458 | 1/ tell IDE channels to operate in Compatibility mode only | |
459 | 2/ tell old chips to allow per drive IDE timings */ | |
460 | ||
461 | { | |
462 | u8 reg; | |
463 | u16 regw; | |
464 | ||
465 | switch(chipset_family) { | |
466 | case ATA_133: | |
467 | /* SiS962 operation mode */ | |
468 | pci_read_config_word(dev, 0x50, ®w); | |
469 | if (regw & 0x08) | |
470 | pci_write_config_word(dev, 0x50, regw&0xfff7); | |
471 | pci_read_config_word(dev, 0x52, ®w); | |
472 | if (regw & 0x08) | |
473 | pci_write_config_word(dev, 0x52, regw&0xfff7); | |
474 | break; | |
475 | case ATA_133a: | |
476 | case ATA_100: | |
477 | /* Fixup latency */ | |
478 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80); | |
479 | /* Set compatibility bit */ | |
480 | pci_read_config_byte(dev, 0x49, ®); | |
481 | if (!(reg & 0x01)) { | |
482 | pci_write_config_byte(dev, 0x49, reg|0x01); | |
483 | } | |
484 | break; | |
485 | case ATA_100a: | |
486 | case ATA_66: | |
487 | /* Fixup latency */ | |
488 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10); | |
489 | ||
490 | /* On ATA_66 chips the bit was elsewhere */ | |
491 | pci_read_config_byte(dev, 0x52, ®); | |
492 | if (!(reg & 0x04)) { | |
493 | pci_write_config_byte(dev, 0x52, reg|0x04); | |
494 | } | |
495 | break; | |
496 | case ATA_33: | |
497 | /* On ATA_33 we didn't have a single bit to set */ | |
498 | pci_read_config_byte(dev, 0x09, ®); | |
499 | if ((reg & 0x0f) != 0x00) { | |
500 | pci_write_config_byte(dev, 0x09, reg&0xf0); | |
501 | } | |
502 | case ATA_16: | |
503 | /* force per drive recovery and active timings | |
504 | needed on ATA_33 and below chips */ | |
505 | pci_read_config_byte(dev, 0x52, ®); | |
506 | if (!(reg & 0x08)) { | |
507 | pci_write_config_byte(dev, 0x52, reg|0x08); | |
508 | } | |
509 | break; | |
510 | } | |
1da177e4 LT |
511 | } |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
f2befd9e BZ |
516 | struct sis_laptop { |
517 | u16 device; | |
518 | u16 subvendor; | |
519 | u16 subdevice; | |
520 | }; | |
521 | ||
522 | static const struct sis_laptop sis_laptop[] = { | |
523 | /* devid, subvendor, subdev */ | |
524 | { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ | |
1955f681 | 525 | { 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */ |
a1d85864 | 526 | { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ |
f2befd9e BZ |
527 | /* end marker */ |
528 | { 0, } | |
529 | }; | |
530 | ||
49521f97 | 531 | static u8 __devinit ata66_sis5513(ide_hwif_t *hwif) |
1da177e4 | 532 | { |
f2befd9e BZ |
533 | struct pci_dev *pdev = hwif->pci_dev; |
534 | const struct sis_laptop *lap = &sis_laptop[0]; | |
1da177e4 LT |
535 | u8 ata66 = 0; |
536 | ||
f2befd9e BZ |
537 | while (lap->device) { |
538 | if (lap->device == pdev->device && | |
539 | lap->subvendor == pdev->subsystem_vendor && | |
540 | lap->subdevice == pdev->subsystem_device) | |
541 | return ATA_CBL_PATA40_SHORT; | |
542 | lap++; | |
543 | } | |
544 | ||
1da177e4 LT |
545 | if (chipset_family >= ATA_133) { |
546 | u16 regw = 0; | |
547 | u16 reg_addr = hwif->channel ? 0x52: 0x50; | |
548 | pci_read_config_word(hwif->pci_dev, reg_addr, ®w); | |
549 | ata66 = (regw & 0x8000) ? 0 : 1; | |
550 | } else if (chipset_family >= ATA_66) { | |
551 | u8 reg48h = 0; | |
552 | u8 mask = hwif->channel ? 0x20 : 0x10; | |
553 | pci_read_config_byte(hwif->pci_dev, 0x48, ®48h); | |
554 | ata66 = (reg48h & mask) ? 0 : 1; | |
555 | } | |
49521f97 BZ |
556 | |
557 | return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40; | |
1da177e4 LT |
558 | } |
559 | ||
2b0c4bed | 560 | static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif) |
1da177e4 | 561 | { |
18137207 BZ |
562 | u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f }; |
563 | ||
26bcb879 | 564 | hwif->set_pio_mode = &sis_set_pio_mode; |
88b2b32b | 565 | hwif->set_dma_mode = &sis_set_dma_mode; |
1da177e4 | 566 | |
3160d541 BZ |
567 | if (chipset_family >= ATA_133) |
568 | hwif->udma_filter = sis5513_ata133_udma_filter; | |
569 | ||
4960ab7c | 570 | if (hwif->dma_base == 0) |
1da177e4 | 571 | return; |
1da177e4 | 572 | |
18137207 | 573 | hwif->ultra_mask = udma_rates[chipset_family]; |
1da177e4 | 574 | |
49521f97 BZ |
575 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
576 | hwif->cbl = ata66_sis5513(hwif); | |
1da177e4 LT |
577 | } |
578 | ||
85620436 | 579 | static const struct ide_port_info sis5513_chipset __devinitdata = { |
1da177e4 LT |
580 | .name = "SIS5513", |
581 | .init_chipset = init_chipset_sis5513, | |
582 | .init_hwif = init_hwif_sis5513, | |
1da177e4 | 583 | .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, |
3985ee3b BZ |
584 | .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA | |
585 | IDE_HFLAG_BOOTABLE, | |
4099d143 | 586 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 587 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
588 | }; |
589 | ||
590 | static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
591 | { | |
592 | return ide_setup_pci_device(dev, &sis5513_chipset); | |
593 | } | |
594 | ||
9cbcc5e3 BZ |
595 | static const struct pci_device_id sis5513_pci_tbl[] = { |
596 | { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5513), 0 }, | |
597 | { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5518), 0 }, | |
598 | { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_1180), 0 }, | |
1da177e4 LT |
599 | { 0, }, |
600 | }; | |
601 | MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl); | |
602 | ||
603 | static struct pci_driver driver = { | |
604 | .name = "SIS_IDE", | |
605 | .id_table = sis5513_pci_tbl, | |
606 | .probe = sis5513_init_one, | |
607 | }; | |
608 | ||
82ab1eec | 609 | static int __init sis5513_ide_init(void) |
1da177e4 LT |
610 | { |
611 | return ide_pci_register_driver(&driver); | |
612 | } | |
613 | ||
614 | module_init(sis5513_ide_init); | |
615 | ||
616 | MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik"); | |
617 | MODULE_DESCRIPTION("PCI driver module for SIS IDE"); | |
618 | MODULE_LICENSE("GPL"); | |
619 | ||
620 | /* | |
621 | * TODO: | |
622 | * - CLEANUP | |
623 | * - Use drivers/ide/ide-timing.h ! | |
624 | * - More checks in the config registers (force values instead of | |
625 | * relying on the BIOS setting them correctly). | |
626 | * - Further optimisations ? | |
627 | * . for example ATA66+ regs 0x48 & 0x4A | |
628 | */ |