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pdc202xx_new: check ide_config_drive_speed() return value
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / siimage.c
CommitLineData
1da177e4 1/*
ffe5415c 2 * linux/drivers/ide/pci/siimage.c Version 1.16 Jul 13 2007
1da177e4
LT		 3 *
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
075cb655 6 * Copyright (C) 2007 MontaVista Software, Inc.
328dcbb6 7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4
LT		 8 *
9 * May be copied or modified under the terms of the GNU General Public License
10 *
bf4c796d
JG		 11 * Documentation for CMD680:
12 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
13 *
14 * Documentation for SiI 3112:
15 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
16 *
17 * Errata and other documentation only available under NDA.
1da177e4
LT		 18 *
19 *
20 * FAQ Items:
21 * If you are using Marvell SATA-IDE adapters with Maxtor drives
22 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
23 *
24 * If you are using WD drives with SATA bridges you must set the
25 * drive to "Single". "Master" will hang
26 *
27 * If you have strange problems with nVidia chipset systems please
28 * see the SI support documentation and update your system BIOS
29 * if neccessary
8693d3e4
AC		 30 *
31 * The Dell DRAC4 has some interesting features including effectively hot
32 * unplugging/replugging the virtual CD interface when the DRAC is reset.
33 * This often causes drivers/ide/siimage to panic but is ok with the rather
34 * smarter code in libata.
328dcbb6
BZ		 35 *
36 * TODO:
37 * - IORDY fixes
38 * - VDMA support
1da177e4
LT		 39 */
40
1da177e4
LT		 41#include <linux/types.h>
42#include <linux/module.h>
43#include <linux/pci.h>
44#include <linux/delay.h>
45#include <linux/hdreg.h>
46#include <linux/ide.h>
47#include <linux/init.h>
48
49#include <asm/io.h>
50
1da177e4
LT		 51/**
52 * pdev_is_sata - check if device is SATA
53 * @pdev: PCI device to check
54 *
55 * Returns true if this is a SATA controller
56 */
57
58static int pdev_is_sata(struct pci_dev *pdev)
59{
60 switch(pdev->device)
61 {
62 case PCI_DEVICE_ID_SII_3112:
63 case PCI_DEVICE_ID_SII_1210SA:
64 return 1;
65 case PCI_DEVICE_ID_SII_680:
66 return 0;
67 }
68 BUG();
69 return 0;
70}
71
72/**
73 * is_sata - check if hwif is SATA
74 * @hwif: interface to check
75 *
76 * Returns true if this is a SATA controller
77 */
78
79static inline int is_sata(ide_hwif_t *hwif)
80{
81 return pdev_is_sata(hwif->pci_dev);
82}
83
84/**
85 * siimage_selreg - return register base
86 * @hwif: interface
87 * @r: config offset
88 *
89 * Turn a config register offset into the right address in either
90 * PCI space or MMIO space to access the control register in question
91 * Thankfully this is a configuration operation so isnt performance
92 * criticial.
93 */
94
95static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
96{
97 unsigned long base = (unsigned long)hwif->hwif_data;
98 base += 0xA0 + r;
99 if(hwif->mmio)
100 base += (hwif->channel << 6);
101 else
102 base += (hwif->channel << 4);
103 return base;
104}
105
106/**
107 * siimage_seldev - return register base
108 * @hwif: interface
109 * @r: config offset
110 *
111 * Turn a config register offset into the right address in either
112 * PCI space or MMIO space to access the control register in question
113 * including accounting for the unit shift.
114 */
115
116static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
117{
118 ide_hwif_t *hwif = HWIF(drive);
119 unsigned long base = (unsigned long)hwif->hwif_data;
120 base += 0xA0 + r;
121 if(hwif->mmio)
122 base += (hwif->channel << 6);
123 else
124 base += (hwif->channel << 4);
125 base |= drive->select.b.unit << drive->select.b.unit;
126 return base;
127}
128
129/**
2d5eaa6d
BZ		 130 * sil_udma_filter - compute UDMA mask
131 * @drive: IDE device
132 *
133 * Compute the available UDMA speeds for the device on the interface.
1da177e4 134 *
1da177e4 135 * For the CMD680 this depends on the clocking mode (scsc), for the
2d5eaa6d 136 * SI3112 SATA controller life is a bit simpler.
1da177e4 137 */
2d5eaa6d
BZ		 138
139static u8 sil_udma_filter(ide_drive_t *drive)
1da177e4 140{
2d5eaa6d 141 ide_hwif_t *hwif = drive->hwif;
1da177e4 142 unsigned long base = (unsigned long) hwif->hwif_data;
2d5eaa6d 143 u8 mask = 0, scsc = 0;
1da177e4
LT		 144
145 if (hwif->mmio)
146 scsc = hwif->INB(base + 0x4A);
147 else
148 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
149
2d5eaa6d
BZ		 150 if (is_sata(hwif)) {
151 mask = strstr(drive->id->model, "Maxtor") ? 0x3f : 0x7f;
152 goto out;
1da177e4 153 }
2d5eaa6d 154
1da177e4 155 if ((scsc & 0x30) == 0x10) /* 133 */
2d5eaa6d 156 mask = 0x7f;
1da177e4 157 else if ((scsc & 0x30) == 0x20) /* 2xPCI */
2d5eaa6d 158 mask = 0x7f;
1da177e4 159 else if ((scsc & 0x30) == 0x00) /* 100 */
2d5eaa6d 160 mask = 0x3f;
1da177e4
LT		 161 else /* Disabled ? */
162 BUG();
2d5eaa6d
BZ		 163out:
164 return mask;
1da177e4
LT		 165}
166
167/**
328dcbb6 168 * sil_tune_pio - tune a drive
1da177e4 169 * @drive: drive to tune
328dcbb6 170 * @pio: the desired PIO mode
1da177e4
LT		 171 *
172 * Load the timing settings for this device mode into the
173 * controller. If we are in PIO mode 3 or 4 turn on IORDY
174 * monitoring (bit 9). The TF timing is bits 31:16
175 */
328dcbb6
BZ		 176
177static void sil_tune_pio(ide_drive_t *drive, u8 pio)
1da177e4 178{
328dcbb6
BZ		 179 const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
180 const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
181
1da177e4 182 ide_hwif_t *hwif = HWIF(drive);
328dcbb6 183 ide_drive_t *pair = &hwif->drives[drive->dn ^ 1];
1da177e4
LT		 184 u32 speedt = 0;
185 u16 speedp = 0;
186 unsigned long addr = siimage_seldev(drive, 0x04);
187 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
ffe5415c 188 unsigned long base = (unsigned long)hwif->hwif_data;
328dcbb6 189 u8 tf_pio = pio;
ffe5415c
BZ		 190 u8 addr_mask = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84)
191 : (hwif->mmio ? 0xB4 : 0x80);
192 u8 mode = 0;
193 u8 unit = drive->select.b.unit;
328dcbb6
BZ		 194
195 /* trim *taskfile* PIO to the slowest of the master/slave */
196 if (pair->present) {
2134758d 197 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
328dcbb6
BZ		 198
199 if (pair_pio < tf_pio)
200 tf_pio = pair_pio;
1da177e4 201 }
075cb655 202
328dcbb6
BZ		 203 /* cheat for now and use the docs */
204 speedp = data_speed[pio];
205 speedt = tf_speed[tf_pio];
206
075cb655
SS		 207 if (hwif->mmio) {
208 hwif->OUTW(speedp, addr);
209 hwif->OUTW(speedt, tfaddr);
1da177e4 210 /* Now set up IORDY */
328dcbb6 211 if (pio > 2)
1da177e4
LT		 212 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
213 else
214 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
ffe5415c
BZ		 215
216 mode = hwif->INB(base + addr_mask);
217 mode &= ~(unit ? 0x30 : 0x03);
218 mode |= (unit ? 0x10 : 0x01);
219 hwif->OUTB(mode, base + addr_mask);
075cb655 220 } else {
1da177e4
LT		 221 pci_write_config_word(hwif->pci_dev, addr, speedp);
222 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
223 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
224 speedp &= ~0x200;
225 /* Set IORDY for mode 3 or 4 */
328dcbb6 226 if (pio > 2)
1da177e4
LT		 227 speedp |= 0x200;
228 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
ffe5415c
BZ		 229
230 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
231 mode &= ~(unit ? 0x30 : 0x03);
232 mode |= (unit ? 0x10 : 0x01);
233 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
1da177e4
LT		 234 }
235}
236
26bcb879 237static void sil_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 238{
328dcbb6
BZ		 239 sil_tune_pio(drive, pio);
240 (void)ide_config_drive_speed(drive, XFER_PIO_0 + pio);
1da177e4
LT		 241}
242
1da177e4
LT		 243/**
244 * siimage_tune_chipset - set controller timings
245 * @drive: Drive to set up
f212ff28 246 * @speed: speed we want to achieve
1da177e4 247 *
f212ff28 248 * Tune the SII chipset for the desired mode.
1da177e4 249 */
f212ff28
BZ		 250
251static int siimage_tune_chipset(ide_drive_t *drive, const u8 speed)
1da177e4
LT		 252{
253 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
254 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
255 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
256
257 ide_hwif_t *hwif = HWIF(drive);
258 u16 ultra = 0, multi = 0;
259 u8 mode = 0, unit = drive->select.b.unit;
1da177e4
LT		 260 unsigned long base = (unsigned long)hwif->hwif_data;
261 u8 scsc = 0, addr_mask = ((hwif->channel) ?
262 ((hwif->mmio) ? 0xF4 : 0x84) :
263 ((hwif->mmio) ? 0xB4 : 0x80));
264
265 unsigned long ma = siimage_seldev(drive, 0x08);
266 unsigned long ua = siimage_seldev(drive, 0x0C);
267
268 if (hwif->mmio) {
269 scsc = hwif->INB(base + 0x4A);
270 mode = hwif->INB(base + addr_mask);
271 multi = hwif->INW(ma);
272 ultra = hwif->INW(ua);
273 } else {
274 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
275 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
276 pci_read_config_word(hwif->pci_dev, ma, &multi);
277 pci_read_config_word(hwif->pci_dev, ua, &ultra);
278 }
279
280 mode &= ~((unit) ? 0x30 : 0x03);
281 ultra &= ~0x3F;
282 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
283
284 scsc = is_sata(hwif) ? 1 : scsc;
285
286 switch(speed) {
1da177e4
LT		 287 case XFER_MW_DMA_2:
288 case XFER_MW_DMA_1:
289 case XFER_MW_DMA_0:
290 multi = dma[speed - XFER_MW_DMA_0];
291 mode |= ((unit) ? 0x20 : 0x02);
1da177e4
LT		 292 break;
293 case XFER_UDMA_6:
294 case XFER_UDMA_5:
295 case XFER_UDMA_4:
296 case XFER_UDMA_3:
297 case XFER_UDMA_2:
298 case XFER_UDMA_1:
299 case XFER_UDMA_0:
300 multi = dma[2];
301 ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
302 (ultra5[speed - XFER_UDMA_0]));
303 mode |= ((unit) ? 0x30 : 0x03);
1da177e4
LT		 304 break;
305 default:
306 return 1;
307 }
308
309 if (hwif->mmio) {
310 hwif->OUTB(mode, base + addr_mask);
311 hwif->OUTW(multi, ma);
312 hwif->OUTW(ultra, ua);
313 } else {
314 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
315 pci_write_config_word(hwif->pci_dev, ma, multi);
316 pci_write_config_word(hwif->pci_dev, ua, ultra);
317 }
318 return (ide_config_drive_speed(drive, speed));
319}
320
1da177e4
LT		 321/**
322 * siimage_configure_drive_for_dma - set up for DMA transfers
323 * @drive: drive we are going to set up
324 *
325 * Set up the drive for DMA, tune the controller and drive as
326 * required. If the drive isn't suitable for DMA or we hit
327 * other problems then we will drop down to PIO and set up
328 * PIO appropriately
329 */
330
331static int siimage_config_drive_for_dma (ide_drive_t *drive)
332{
4728d546 333 if (ide_tune_dma(drive))
3608b5d7 334 return 0;
1da177e4 335
d8f4469d 336 if (ide_use_fast_pio(drive))
26bcb879 337 ide_set_max_pio(drive);
d8f4469d 338
3608b5d7 339 return -1;
1da177e4
LT		 340}
341
342/* returns 1 if dma irq issued, 0 otherwise */
343static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
344{
345 ide_hwif_t *hwif = HWIF(drive);
346 u8 dma_altstat = 0;
347 unsigned long addr = siimage_selreg(hwif, 1);
348
349 /* return 1 if INTR asserted */
350 if ((hwif->INB(hwif->dma_status) & 4) == 4)
351 return 1;
352
353 /* return 1 if Device INTR asserted */
354 pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
355 if (dma_altstat & 8)
356 return 0; //return 1;
357 return 0;
358}
359
1da177e4
LT		 360/**
361 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
362 * @drive: drive we are testing
363 *
364 * Check if we caused an IDE DMA interrupt. We may also have caused
365 * SATA status interrupts, if so we clean them up and continue.
366 */
367
368static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
369{
370 ide_hwif_t *hwif = HWIF(drive);
371 unsigned long base = (unsigned long)hwif->hwif_data;
372 unsigned long addr = siimage_selreg(hwif, 0x1);
373
374 if (SATA_ERROR_REG) {
0ecdca26 375 u32 ext_stat = readl((void __iomem *)(base + 0x10));
1da177e4
LT		 376 u8 watchdog = 0;
377 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
0ecdca26
BZ		 378 u32 sata_error = readl((void __iomem *)SATA_ERROR_REG);
379 writel(sata_error, (void __iomem *)SATA_ERROR_REG);
1da177e4 380 watchdog = (sata_error & 0x00680000) ? 1 : 0;
1da177e4
LT		 381 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
382 "watchdog = %d, %s\n",
383 drive->name, sata_error, watchdog,
384 __FUNCTION__);
1da177e4
LT		 385
386 } else {
387 watchdog = (ext_stat & 0x8000) ? 1 : 0;
388 }
389 ext_stat >>= 16;
390
391 if (!(ext_stat & 0x0404) && !watchdog)
392 return 0;
393 }
394
395 /* return 1 if INTR asserted */
0ecdca26 396 if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04)
1da177e4
LT		 397 return 1;
398
399 /* return 1 if Device INTR asserted */
0ecdca26 400 if ((readb((void __iomem *)addr) & 8) == 8)
1da177e4
LT		 401 return 0; //return 1;
402
403 return 0;
404}
405
406/**
407 * siimage_busproc - bus isolation ioctl
408 * @drive: drive to isolate/restore
409 * @state: bus state to set
410 *
411 * Used by the SII3112 to handle bus isolation. As this is a
412 * SATA controller the work required is quite limited, we
413 * just have to clean up the statistics
414 */
415
416static int siimage_busproc (ide_drive_t * drive, int state)
417{
418 ide_hwif_t *hwif = HWIF(drive);
419 u32 stat_config = 0;
420 unsigned long addr = siimage_selreg(hwif, 0);
421
0ecdca26
BZ		 422 if (hwif->mmio)
423 stat_config = readl((void __iomem *)addr);
424 else
1da177e4
LT		 425 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
426
427 switch (state) {
428 case BUSSTATE_ON:
429 hwif->drives[0].failures = 0;
430 hwif->drives[1].failures = 0;
431 break;
432 case BUSSTATE_OFF:
433 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
434 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
435 break;
436 case BUSSTATE_TRISTATE:
437 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
438 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
439 break;
440 default:
441 return -EINVAL;
442 }
443 hwif->bus_state = state;
444 return 0;
445}
446
447/**
448 * siimage_reset_poll - wait for sata reset
449 * @drive: drive we are resetting
450 *
451 * Poll the SATA phy and see whether it has come back from the dead
452 * yet.
453 */
454
455static int siimage_reset_poll (ide_drive_t *drive)
456{
457 if (SATA_STATUS_REG) {
458 ide_hwif_t *hwif = HWIF(drive);
459
0ecdca26
BZ		 460 /* SATA_STATUS_REG is valid only when in MMIO mode */
461 if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) {
1da177e4 462 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
0ecdca26 463 hwif->name, readl((void __iomem *)SATA_STATUS_REG));
1da177e4
LT		 464 HWGROUP(drive)->polling = 0;
465 return ide_started;
466 }
467 return 0;
468 } else {
469 return 0;
470 }
471}
472
473/**
474 * siimage_pre_reset - reset hook
475 * @drive: IDE device being reset
476 *
477 * For the SATA devices we need to handle recalibration/geometry
478 * differently
479 */
480
481static void siimage_pre_reset (ide_drive_t *drive)
482{
483 if (drive->media != ide_disk)
484 return;
485
486 if (is_sata(HWIF(drive)))
487 {
488 drive->special.b.set_geometry = 0;
489 drive->special.b.recalibrate = 0;
490 }
491}
492
493/**
494 * siimage_reset - reset a device on an siimage controller
495 * @drive: drive to reset
496 *
497 * Perform a controller level reset fo the device. For
498 * SATA we must also check the PHY.
499 */
500
501static void siimage_reset (ide_drive_t *drive)
502{
503 ide_hwif_t *hwif = HWIF(drive);
504 u8 reset = 0;
505 unsigned long addr = siimage_selreg(hwif, 0);
506
507 if (hwif->mmio) {
508 reset = hwif->INB(addr);
509 hwif->OUTB((reset|0x03), addr);
510 /* FIXME:posting */
511 udelay(25);
512 hwif->OUTB(reset, addr);
513 (void) hwif->INB(addr);
514 } else {
515 pci_read_config_byte(hwif->pci_dev, addr, &reset);
516 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
517 udelay(25);
518 pci_write_config_byte(hwif->pci_dev, addr, reset);
519 pci_read_config_byte(hwif->pci_dev, addr, &reset);
520 }
521
522 if (SATA_STATUS_REG) {
0ecdca26
BZ		 523 /* SATA_STATUS_REG is valid only when in MMIO mode */
524 u32 sata_stat = readl((void __iomem *)SATA_STATUS_REG);
1da177e4
LT		 525 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
526 hwif->name, sata_stat, __FUNCTION__);
527 if (!(sata_stat)) {
528 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
529 hwif->name, sata_stat);
530 drive->failures++;
531 }
532 }
533
534}
535
536/**
537 * proc_reports_siimage - add siimage controller to proc
538 * @dev: PCI device
539 * @clocking: SCSC value
540 * @name: controller name
541 *
542 * Report the clocking mode of the controller and add it to
543 * the /proc interface layer
544 */
545
546static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
547{
548 if (!pdev_is_sata(dev)) {
549 printk(KERN_INFO "%s: BASE CLOCK ", name);
550 clocking &= 0x03;
551 switch (clocking) {
552 case 0x03: printk("DISABLED!\n"); break;
553 case 0x02: printk("== 2X PCI\n"); break;
554 case 0x01: printk("== 133\n"); break;
555 case 0x00: printk("== 100\n"); break;
556 }
557 }
558}
559
560/**
561 * setup_mmio_siimage - switch an SI controller into MMIO
562 * @dev: PCI device we are configuring
563 * @name: device name
564 *
565 * Attempt to put the device into mmio mode. There are some slight
566 * complications here with certain systems where the mmio bar isnt
567 * mapped so we have to be sure we can fall back to I/O.
568 */
569
570static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
571{
572 unsigned long bar5 = pci_resource_start(dev, 5);
573 unsigned long barsize = pci_resource_len(dev, 5);
574 u8 tmpbyte = 0;
575 void __iomem *ioaddr;
d868dd19 576 u32 tmp, irq_mask;
1da177e4
LT		 577
578 /*
579 * Drop back to PIO if we can't map the mmio. Some
580 * systems seem to get terminally confused in the PCI
581 * spaces.
582 */
583
584 if(!request_mem_region(bar5, barsize, name))
585 {
586 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
587 return 0;
588 }
589
590 ioaddr = ioremap(bar5, barsize);
591
592 if (ioaddr == NULL)
593 {
594 release_mem_region(bar5, barsize);
595 return 0;
596 }
597
598 pci_set_master(dev);
599 pci_set_drvdata(dev, (void *) ioaddr);
600
601 if (pdev_is_sata(dev)) {
d868dd19
JL		 602 /* make sure IDE0/1 interrupts are not masked */
603 irq_mask = (1 << 22) | (1 << 23);
604 tmp = readl(ioaddr + 0x48);
605 if (tmp & irq_mask) {
606 tmp &= ~irq_mask;
607 writel(tmp, ioaddr + 0x48);
608 readl(ioaddr + 0x48); /* flush */
609 }
1da177e4
LT		 610 writel(0, ioaddr + 0x148);
611 writel(0, ioaddr + 0x1C8);
612 }
613
614 writeb(0, ioaddr + 0xB4);
615 writeb(0, ioaddr + 0xF4);
616 tmpbyte = readb(ioaddr + 0x4A);
617
618 switch(tmpbyte & 0x30) {
619 case 0x00:
620 /* In 100 MHz clocking, try and switch to 133 */
621 writeb(tmpbyte|0x10, ioaddr + 0x4A);
622 break;
623 case 0x10:
624 /* On 133Mhz clocking */
625 break;
626 case 0x20:
627 /* On PCIx2 clocking */
628 break;
629 case 0x30:
630 /* Clocking is disabled */
631 /* 133 clock attempt to force it on */
632 writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
633 break;
634 }
635
636 writeb( 0x72, ioaddr + 0xA1);
637 writew( 0x328A, ioaddr + 0xA2);
638 writel(0x62DD62DD, ioaddr + 0xA4);
639 writel(0x43924392, ioaddr + 0xA8);
640 writel(0x40094009, ioaddr + 0xAC);
641 writeb( 0x72, ioaddr + 0xE1);
642 writew( 0x328A, ioaddr + 0xE2);
643 writel(0x62DD62DD, ioaddr + 0xE4);
644 writel(0x43924392, ioaddr + 0xE8);
645 writel(0x40094009, ioaddr + 0xEC);
646
647 if (pdev_is_sata(dev)) {
648 writel(0xFFFF0000, ioaddr + 0x108);
649 writel(0xFFFF0000, ioaddr + 0x188);
650 writel(0x00680000, ioaddr + 0x148);
651 writel(0x00680000, ioaddr + 0x1C8);
652 }
653
654 tmpbyte = readb(ioaddr + 0x4A);
655
656 proc_reports_siimage(dev, (tmpbyte>>4), name);
657 return 1;
658}
659
660/**
661 * init_chipset_siimage - set up an SI device
662 * @dev: PCI device
663 * @name: device name
664 *
665 * Perform the initial PCI set up for this device. Attempt to switch
666 * to 133MHz clocking if the system isn't already set up to do it.
667 */
668
669static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
670{
671 u32 class_rev = 0;
672 u8 tmpbyte = 0;
673 u8 BA5_EN = 0;
674
675 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
676 class_rev &= 0xff;
677 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
678
679 pci_read_config_byte(dev, 0x8A, &BA5_EN);
680 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
681 if (setup_mmio_siimage(dev, name)) {
682 return 0;
683 }
684 }
685
686 pci_write_config_byte(dev, 0x80, 0x00);
687 pci_write_config_byte(dev, 0x84, 0x00);
688 pci_read_config_byte(dev, 0x8A, &tmpbyte);
689 switch(tmpbyte & 0x30) {
690 case 0x00:
691 /* 133 clock attempt to force it on */
692 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
693 case 0x30:
694 /* if clocking is disabled */
695 /* 133 clock attempt to force it on */
696 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
697 case 0x10:
698 /* 133 already */
699 break;
700 case 0x20:
701 /* BIOS set PCI x2 clocking */
702 break;
703 }
704
705 pci_read_config_byte(dev, 0x8A, &tmpbyte);
706
707 pci_write_config_byte(dev, 0xA1, 0x72);
708 pci_write_config_word(dev, 0xA2, 0x328A);
709 pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
710 pci_write_config_dword(dev, 0xA8, 0x43924392);
711 pci_write_config_dword(dev, 0xAC, 0x40094009);
712 pci_write_config_byte(dev, 0xB1, 0x72);
713 pci_write_config_word(dev, 0xB2, 0x328A);
714 pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
715 pci_write_config_dword(dev, 0xB8, 0x43924392);
716 pci_write_config_dword(dev, 0xBC, 0x40094009);
717
718 proc_reports_siimage(dev, (tmpbyte>>4), name);
719 return 0;
720}
721
722/**
723 * init_mmio_iops_siimage - set up the iops for MMIO
724 * @hwif: interface to set up
725 *
726 * The basic setup here is fairly simple, we can use standard MMIO
727 * operations. However we do have to set the taskfile register offsets
728 * by hand as there isnt a standard defined layout for them this
729 * time.
730 *
731 * The hardware supports buffered taskfiles and also some rather nice
19c1ef5f 732 * extended PRD tables. For better SI3112 support use the libata driver
1da177e4
LT		 733 */
734
735static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
736{
737 struct pci_dev *dev = hwif->pci_dev;
738 void *addr = pci_get_drvdata(dev);
739 u8 ch = hwif->channel;
740 hw_regs_t hw;
741 unsigned long base;
742
743 /*
744 * Fill in the basic HWIF bits
745 */
746
747 default_hwif_mmiops(hwif);
748 hwif->hwif_data = addr;
749
750 /*
751 * Now set up the hw. We have to do this ourselves as
59c51591 752 * the MMIO layout isnt the same as the standard port
1da177e4
LT		 753 * based I/O
754 */
755
756 memset(&hw, 0, sizeof(hw_regs_t));
757
758 base = (unsigned long)addr;
759 if (ch)
760 base += 0xC0;
761 else
762 base += 0x80;
763
764 /*
765 * The buffered task file doesn't have status/control
766 * so we can't currently use it sanely since we want to
767 * use LBA48 mode.
768 */
1da177e4
LT		 769 hw.io_ports[IDE_DATA_OFFSET] = base;
770 hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
771 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
772 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
773 hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
774 hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
775 hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
776 hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
777 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
778
779 hw.io_ports[IDE_IRQ_OFFSET] = 0;
780
781 if (pdev_is_sata(dev)) {
782 base = (unsigned long)addr;
783 if (ch)
784 base += 0x80;
785 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
786 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
787 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
788 hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140;
789 hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144;
790 hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148;
791 }
792
793 hw.irq = hwif->pci_dev->irq;
794
795 memcpy(&hwif->hw, &hw, sizeof(hw));
796 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
797
798 hwif->irq = hw.irq;
799
800 base = (unsigned long) addr;
801
1da177e4 802 hwif->dma_base = base + (ch ? 0x08 : 0x00);
2ad1e558
BZ		 803
804 hwif->mmio = 1;
1da177e4
LT		 805}
806
807static int is_dev_seagate_sata(ide_drive_t *drive)
808{
809 const char *s = &drive->id->model[0];
810 unsigned len;
811
812 if (!drive->present)
813 return 0;
814
815 len = strnlen(s, sizeof(drive->id->model));
816
817 if ((len > 4) && (!memcmp(s, "ST", 2))) {
818 if ((!memcmp(s + len - 2, "AS", 2)) ||
819 (!memcmp(s + len - 3, "ASL", 3))) {
820 printk(KERN_INFO "%s: applying pessimistic Seagate "
821 "errata fix\n", drive->name);
822 return 1;
823 }
824 }
825 return 0;
826}
827
828/**
829 * siimage_fixup - post probe fixups
830 * @hwif: interface to fix up
831 *
832 * Called after drive probe we use this to decide whether the
833 * Seagate fixup must be applied. This used to be in init_iops but
834 * that can occur before we know what drives are present.
835 */
836
837static void __devinit siimage_fixup(ide_hwif_t *hwif)
838{
839 /* Try and raise the rqsize */
840 if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0]))
841 hwif->rqsize = 128;
842}
843
844/**
845 * init_iops_siimage - set up iops
846 * @hwif: interface to set up
847 *
848 * Do the basic setup for the SIIMAGE hardware interface
849 * and then do the MMIO setup if we can. This is the first
850 * look in we get for setting up the hwif so that we
851 * can get the iops right before using them.
852 */
853
854static void __devinit init_iops_siimage(ide_hwif_t *hwif)
855{
856 struct pci_dev *dev = hwif->pci_dev;
857 u32 class_rev = 0;
858
859 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
860 class_rev &= 0xff;
861
862 hwif->hwif_data = NULL;
863
864 /* Pessimal until we finish probing */
865 hwif->rqsize = 15;
866
867 if (pci_get_drvdata(dev) == NULL)
868 return;
869 init_mmio_iops_siimage(hwif);
870}
871
872/**
873 * ata66_siimage - check for 80 pin cable
874 * @hwif: interface to check
875 *
876 * Check for the presence of an ATA66 capable cable on the
877 * interface.
878 */
879
49521f97 880static u8 __devinit ata66_siimage(ide_hwif_t *hwif)
1da177e4
LT		 881{
882 unsigned long addr = siimage_selreg(hwif, 0);
49521f97
BZ		 883 u8 ata66 = 0;
884
885 if (pci_get_drvdata(hwif->pci_dev) == NULL)
1da177e4 886 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
49521f97
BZ		 887 else
888 ata66 = hwif->INB(addr);
1da177e4 889
49521f97 890 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
1da177e4
LT		 891}
892
893/**
894 * init_hwif_siimage - set up hwif structs
895 * @hwif: interface to set up
896 *
897 * We do the basic set up of the interface structure. The SIIMAGE
898 * requires several custom handlers so we override the default
899 * ide DMA handlers appropriately
900 */
901
902static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
903{
904 hwif->autodma = 0;
905
906 hwif->resetproc = &siimage_reset;
907 hwif->speedproc = &siimage_tune_chipset;
26bcb879 908 hwif->set_pio_mode = &sil_set_pio_mode;
1da177e4
LT		 909 hwif->reset_poll = &siimage_reset_poll;
910 hwif->pre_reset = &siimage_pre_reset;
2d5eaa6d 911 hwif->udma_filter = &sil_udma_filter;
1da177e4 912
19c1ef5f
AC		 913 if(is_sata(hwif)) {
914 static int first = 1;
915
1da177e4
LT		 916 hwif->busproc = &siimage_busproc;
917
19c1ef5f
AC		 918 if (first) {
919 printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n");
920 first = 0;
921 }
922 }
328dcbb6
BZ		 923
924 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
925
926 if (hwif->dma_base == 0)
1da177e4 927 return;
1da177e4
LT		 928
929 hwif->ultra_mask = 0x7f;
930 hwif->mwdma_mask = 0x07;
1da177e4
LT		 931
932 if (!is_sata(hwif))
933 hwif->atapi_dma = 1;
934
935 hwif->ide_dma_check = &siimage_config_drive_for_dma;
49521f97
BZ		 936
937 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
938 hwif->cbl = ata66_siimage(hwif);
1da177e4
LT		 939
940 if (hwif->mmio) {
941 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
942 } else {
943 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
944 }
945
946 /*
947 * The BIOS often doesn't set up DMA on this controller
948 * so we always do it.
949 */
950
951 hwif->autodma = 1;
952 hwif->drives[0].autodma = hwif->autodma;
953 hwif->drives[1].autodma = hwif->autodma;
954}
955
956#define DECLARE_SII_DEV(name_str) \
957 { \
958 .name = name_str, \
959 .init_chipset = init_chipset_siimage, \
960 .init_iops = init_iops_siimage, \
961 .init_hwif = init_hwif_siimage, \
962 .fixup = siimage_fixup, \
1da177e4
LT		 963 .autodma = AUTODMA, \
964 .bootable = ON_BOARD, \
4099d143 965 .pio_mask = ATA_PIO4, \
1da177e4
LT		 966 }
967
968static ide_pci_device_t siimage_chipsets[] __devinitdata = {
969 /* 0 */ DECLARE_SII_DEV("SiI680"),
970 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
971 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
972};
973
974/**
975 * siimage_init_one - pci layer discovery entry
976 * @dev: PCI device
977 * @id: ident table entry
978 *
979 * Called by the PCI code when it finds an SI680 or SI3112 controller.
980 * We then use the IDE PCI generic helper to do most of the work.
981 */
982
983static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
984{
985 return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
986}
987
988static struct pci_device_id siimage_pci_tbl[] = {
28a2a3f5 989 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4 990#ifdef CONFIG_BLK_DEV_IDE_SATA
28a2a3f5
AC		 991 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
992 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1da177e4
LT		 993#endif
994 { 0, },
995};
996MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
997
998static struct pci_driver driver = {
999 .name = "SiI_IDE",
1000 .id_table = siimage_pci_tbl,
1001 .probe = siimage_init_one,
1002};
1003
82ab1eec 1004static int __init siimage_ide_init(void)
1da177e4
LT		 1005{
1006 return ide_pci_register_driver(&driver);
1007}
1008
1009module_init(siimage_ide_init);
1010
1011MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1012MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1013MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)