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cs5520: don't enable VDMA in ->speedproc
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / siimage.c
CommitLineData
1da177e4 1/*
328dcbb6 2 * linux/drivers/ide/pci/siimage.c Version 1.15 Jun 29 2007
1da177e4
LT		 3 *
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
075cb655 6 * Copyright (C) 2007 MontaVista Software, Inc.
328dcbb6 7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4
LT		 8 *
9 * May be copied or modified under the terms of the GNU General Public License
10 *
bf4c796d
JG		 11 * Documentation for CMD680:
12 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
13 *
14 * Documentation for SiI 3112:
15 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
16 *
17 * Errata and other documentation only available under NDA.
1da177e4
LT		 18 *
19 *
20 * FAQ Items:
21 * If you are using Marvell SATA-IDE adapters with Maxtor drives
22 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
23 *
24 * If you are using WD drives with SATA bridges you must set the
25 * drive to "Single". "Master" will hang
26 *
27 * If you have strange problems with nVidia chipset systems please
28 * see the SI support documentation and update your system BIOS
29 * if neccessary
8693d3e4
AC		 30 *
31 * The Dell DRAC4 has some interesting features including effectively hot
32 * unplugging/replugging the virtual CD interface when the DRAC is reset.
33 * This often causes drivers/ide/siimage to panic but is ok with the rather
34 * smarter code in libata.
328dcbb6
BZ		 35 *
36 * TODO:
37 * - IORDY fixes
38 * - VDMA support
1da177e4
LT		 39 */
40
1da177e4
LT		 41#include <linux/types.h>
42#include <linux/module.h>
43#include <linux/pci.h>
44#include <linux/delay.h>
45#include <linux/hdreg.h>
46#include <linux/ide.h>
47#include <linux/init.h>
48
49#include <asm/io.h>
50
1da177e4
LT		 51/**
52 * pdev_is_sata - check if device is SATA
53 * @pdev: PCI device to check
54 *
55 * Returns true if this is a SATA controller
56 */
57
58static int pdev_is_sata(struct pci_dev *pdev)
59{
60 switch(pdev->device)
61 {
62 case PCI_DEVICE_ID_SII_3112:
63 case PCI_DEVICE_ID_SII_1210SA:
64 return 1;
65 case PCI_DEVICE_ID_SII_680:
66 return 0;
67 }
68 BUG();
69 return 0;
70}
71
72/**
73 * is_sata - check if hwif is SATA
74 * @hwif: interface to check
75 *
76 * Returns true if this is a SATA controller
77 */
78
79static inline int is_sata(ide_hwif_t *hwif)
80{
81 return pdev_is_sata(hwif->pci_dev);
82}
83
84/**
85 * siimage_selreg - return register base
86 * @hwif: interface
87 * @r: config offset
88 *
89 * Turn a config register offset into the right address in either
90 * PCI space or MMIO space to access the control register in question
91 * Thankfully this is a configuration operation so isnt performance
92 * criticial.
93 */
94
95static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
96{
97 unsigned long base = (unsigned long)hwif->hwif_data;
98 base += 0xA0 + r;
99 if(hwif->mmio)
100 base += (hwif->channel << 6);
101 else
102 base += (hwif->channel << 4);
103 return base;
104}
105
106/**
107 * siimage_seldev - return register base
108 * @hwif: interface
109 * @r: config offset
110 *
111 * Turn a config register offset into the right address in either
112 * PCI space or MMIO space to access the control register in question
113 * including accounting for the unit shift.
114 */
115
116static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
117{
118 ide_hwif_t *hwif = HWIF(drive);
119 unsigned long base = (unsigned long)hwif->hwif_data;
120 base += 0xA0 + r;
121 if(hwif->mmio)
122 base += (hwif->channel << 6);
123 else
124 base += (hwif->channel << 4);
125 base |= drive->select.b.unit << drive->select.b.unit;
126 return base;
127}
128
129/**
2d5eaa6d
BZ		 130 * sil_udma_filter - compute UDMA mask
131 * @drive: IDE device
132 *
133 * Compute the available UDMA speeds for the device on the interface.
1da177e4 134 *
1da177e4 135 * For the CMD680 this depends on the clocking mode (scsc), for the
2d5eaa6d 136 * SI3112 SATA controller life is a bit simpler.
1da177e4 137 */
2d5eaa6d
BZ		 138
139static u8 sil_udma_filter(ide_drive_t *drive)
1da177e4 140{
2d5eaa6d 141 ide_hwif_t *hwif = drive->hwif;
1da177e4 142 unsigned long base = (unsigned long) hwif->hwif_data;
2d5eaa6d 143 u8 mask = 0, scsc = 0;
1da177e4
LT		 144
145 if (hwif->mmio)
146 scsc = hwif->INB(base + 0x4A);
147 else
148 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
149
2d5eaa6d
BZ		 150 if (is_sata(hwif)) {
151 mask = strstr(drive->id->model, "Maxtor") ? 0x3f : 0x7f;
152 goto out;
1da177e4 153 }
2d5eaa6d 154
1da177e4 155 if ((scsc & 0x30) == 0x10) /* 133 */
2d5eaa6d 156 mask = 0x7f;
1da177e4 157 else if ((scsc & 0x30) == 0x20) /* 2xPCI */
2d5eaa6d 158 mask = 0x7f;
1da177e4 159 else if ((scsc & 0x30) == 0x00) /* 100 */
2d5eaa6d 160 mask = 0x3f;
1da177e4
LT		 161 else /* Disabled ? */
162 BUG();
2d5eaa6d
BZ		 163out:
164 return mask;
1da177e4
LT		 165}
166
167/**
328dcbb6 168 * sil_tune_pio - tune a drive
1da177e4 169 * @drive: drive to tune
328dcbb6 170 * @pio: the desired PIO mode
1da177e4
LT		 171 *
172 * Load the timing settings for this device mode into the
173 * controller. If we are in PIO mode 3 or 4 turn on IORDY
174 * monitoring (bit 9). The TF timing is bits 31:16
175 */
328dcbb6
BZ		 176
177static void sil_tune_pio(ide_drive_t *drive, u8 pio)
1da177e4 178{
328dcbb6
BZ		 179 const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
180 const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
181
1da177e4 182 ide_hwif_t *hwif = HWIF(drive);
328dcbb6 183 ide_drive_t *pair = &hwif->drives[drive->dn ^ 1];
1da177e4
LT		 184 u32 speedt = 0;
185 u16 speedp = 0;
186 unsigned long addr = siimage_seldev(drive, 0x04);
187 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
328dcbb6
BZ		 188 u8 tf_pio = pio;
189
190 /* trim *taskfile* PIO to the slowest of the master/slave */
191 if (pair->present) {
2134758d 192 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
328dcbb6
BZ		 193
194 if (pair_pio < tf_pio)
195 tf_pio = pair_pio;
1da177e4 196 }
075cb655 197
328dcbb6
BZ		 198 /* cheat for now and use the docs */
199 speedp = data_speed[pio];
200 speedt = tf_speed[tf_pio];
201
075cb655
SS		 202 if (hwif->mmio) {
203 hwif->OUTW(speedp, addr);
204 hwif->OUTW(speedt, tfaddr);
1da177e4 205 /* Now set up IORDY */
328dcbb6 206 if (pio > 2)
1da177e4
LT		 207 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
208 else
209 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
075cb655 210 } else {
1da177e4
LT		 211 pci_write_config_word(hwif->pci_dev, addr, speedp);
212 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
213 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
214 speedp &= ~0x200;
215 /* Set IORDY for mode 3 or 4 */
328dcbb6 216 if (pio > 2)
1da177e4
LT		 217 speedp |= 0x200;
218 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
219 }
220}
221
26bcb879 222static void sil_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 223{
328dcbb6
BZ		 224 sil_tune_pio(drive, pio);
225 (void)ide_config_drive_speed(drive, XFER_PIO_0 + pio);
1da177e4
LT		 226}
227
1da177e4
LT		 228/**
229 * siimage_tune_chipset - set controller timings
230 * @drive: Drive to set up
f212ff28 231 * @speed: speed we want to achieve
1da177e4 232 *
f212ff28 233 * Tune the SII chipset for the desired mode.
1da177e4 234 */
f212ff28
BZ		 235
236static int siimage_tune_chipset(ide_drive_t *drive, const u8 speed)
1da177e4
LT		 237{
238 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
239 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
240 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
241
242 ide_hwif_t *hwif = HWIF(drive);
243 u16 ultra = 0, multi = 0;
244 u8 mode = 0, unit = drive->select.b.unit;
1da177e4
LT		 245 unsigned long base = (unsigned long)hwif->hwif_data;
246 u8 scsc = 0, addr_mask = ((hwif->channel) ?
247 ((hwif->mmio) ? 0xF4 : 0x84) :
248 ((hwif->mmio) ? 0xB4 : 0x80));
249
250 unsigned long ma = siimage_seldev(drive, 0x08);
251 unsigned long ua = siimage_seldev(drive, 0x0C);
252
253 if (hwif->mmio) {
254 scsc = hwif->INB(base + 0x4A);
255 mode = hwif->INB(base + addr_mask);
256 multi = hwif->INW(ma);
257 ultra = hwif->INW(ua);
258 } else {
259 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
260 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
261 pci_read_config_word(hwif->pci_dev, ma, &multi);
262 pci_read_config_word(hwif->pci_dev, ua, &ultra);
263 }
264
265 mode &= ~((unit) ? 0x30 : 0x03);
266 ultra &= ~0x3F;
267 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
268
269 scsc = is_sata(hwif) ? 1 : scsc;
270
271 switch(speed) {
272 case XFER_PIO_4:
273 case XFER_PIO_3:
274 case XFER_PIO_2:
275 case XFER_PIO_1:
276 case XFER_PIO_0:
328dcbb6 277 sil_tune_pio(drive, speed - XFER_PIO_0);
1da177e4
LT		 278 mode |= ((unit) ? 0x10 : 0x01);
279 break;
280 case XFER_MW_DMA_2:
281 case XFER_MW_DMA_1:
282 case XFER_MW_DMA_0:
283 multi = dma[speed - XFER_MW_DMA_0];
284 mode |= ((unit) ? 0x20 : 0x02);
1da177e4
LT		 285 break;
286 case XFER_UDMA_6:
287 case XFER_UDMA_5:
288 case XFER_UDMA_4:
289 case XFER_UDMA_3:
290 case XFER_UDMA_2:
291 case XFER_UDMA_1:
292 case XFER_UDMA_0:
293 multi = dma[2];
294 ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
295 (ultra5[speed - XFER_UDMA_0]));
296 mode |= ((unit) ? 0x30 : 0x03);
1da177e4
LT		 297 break;
298 default:
299 return 1;
300 }
301
302 if (hwif->mmio) {
303 hwif->OUTB(mode, base + addr_mask);
304 hwif->OUTW(multi, ma);
305 hwif->OUTW(ultra, ua);
306 } else {
307 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
308 pci_write_config_word(hwif->pci_dev, ma, multi);
309 pci_write_config_word(hwif->pci_dev, ua, ultra);
310 }
311 return (ide_config_drive_speed(drive, speed));
312}
313
1da177e4
LT		 314/**
315 * siimage_configure_drive_for_dma - set up for DMA transfers
316 * @drive: drive we are going to set up
317 *
318 * Set up the drive for DMA, tune the controller and drive as
319 * required. If the drive isn't suitable for DMA or we hit
320 * other problems then we will drop down to PIO and set up
321 * PIO appropriately
322 */
323
324static int siimage_config_drive_for_dma (ide_drive_t *drive)
325{
4728d546 326 if (ide_tune_dma(drive))
3608b5d7 327 return 0;
1da177e4 328
d8f4469d 329 if (ide_use_fast_pio(drive))
26bcb879 330 ide_set_max_pio(drive);
d8f4469d 331
3608b5d7 332 return -1;
1da177e4
LT		 333}
334
335/* returns 1 if dma irq issued, 0 otherwise */
336static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
337{
338 ide_hwif_t *hwif = HWIF(drive);
339 u8 dma_altstat = 0;
340 unsigned long addr = siimage_selreg(hwif, 1);
341
342 /* return 1 if INTR asserted */
343 if ((hwif->INB(hwif->dma_status) & 4) == 4)
344 return 1;
345
346 /* return 1 if Device INTR asserted */
347 pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
348 if (dma_altstat & 8)
349 return 0; //return 1;
350 return 0;
351}
352
1da177e4
LT		 353/**
354 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
355 * @drive: drive we are testing
356 *
357 * Check if we caused an IDE DMA interrupt. We may also have caused
358 * SATA status interrupts, if so we clean them up and continue.
359 */
360
361static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
362{
363 ide_hwif_t *hwif = HWIF(drive);
364 unsigned long base = (unsigned long)hwif->hwif_data;
365 unsigned long addr = siimage_selreg(hwif, 0x1);
366
367 if (SATA_ERROR_REG) {
0ecdca26 368 u32 ext_stat = readl((void __iomem *)(base + 0x10));
1da177e4
LT		 369 u8 watchdog = 0;
370 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
0ecdca26
BZ		 371 u32 sata_error = readl((void __iomem *)SATA_ERROR_REG);
372 writel(sata_error, (void __iomem *)SATA_ERROR_REG);
1da177e4 373 watchdog = (sata_error & 0x00680000) ? 1 : 0;
1da177e4
LT		 374 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
375 "watchdog = %d, %s\n",
376 drive->name, sata_error, watchdog,
377 __FUNCTION__);
1da177e4
LT		 378
379 } else {
380 watchdog = (ext_stat & 0x8000) ? 1 : 0;
381 }
382 ext_stat >>= 16;
383
384 if (!(ext_stat & 0x0404) && !watchdog)
385 return 0;
386 }
387
388 /* return 1 if INTR asserted */
0ecdca26 389 if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04)
1da177e4
LT		 390 return 1;
391
392 /* return 1 if Device INTR asserted */
0ecdca26 393 if ((readb((void __iomem *)addr) & 8) == 8)
1da177e4
LT		 394 return 0; //return 1;
395
396 return 0;
397}
398
399/**
400 * siimage_busproc - bus isolation ioctl
401 * @drive: drive to isolate/restore
402 * @state: bus state to set
403 *
404 * Used by the SII3112 to handle bus isolation. As this is a
405 * SATA controller the work required is quite limited, we
406 * just have to clean up the statistics
407 */
408
409static int siimage_busproc (ide_drive_t * drive, int state)
410{
411 ide_hwif_t *hwif = HWIF(drive);
412 u32 stat_config = 0;
413 unsigned long addr = siimage_selreg(hwif, 0);
414
0ecdca26
BZ		 415 if (hwif->mmio)
416 stat_config = readl((void __iomem *)addr);
417 else
1da177e4
LT		 418 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
419
420 switch (state) {
421 case BUSSTATE_ON:
422 hwif->drives[0].failures = 0;
423 hwif->drives[1].failures = 0;
424 break;
425 case BUSSTATE_OFF:
426 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
427 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
428 break;
429 case BUSSTATE_TRISTATE:
430 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
431 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
432 break;
433 default:
434 return -EINVAL;
435 }
436 hwif->bus_state = state;
437 return 0;
438}
439
440/**
441 * siimage_reset_poll - wait for sata reset
442 * @drive: drive we are resetting
443 *
444 * Poll the SATA phy and see whether it has come back from the dead
445 * yet.
446 */
447
448static int siimage_reset_poll (ide_drive_t *drive)
449{
450 if (SATA_STATUS_REG) {
451 ide_hwif_t *hwif = HWIF(drive);
452
0ecdca26
BZ		 453 /* SATA_STATUS_REG is valid only when in MMIO mode */
454 if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) {
1da177e4 455 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
0ecdca26 456 hwif->name, readl((void __iomem *)SATA_STATUS_REG));
1da177e4
LT		 457 HWGROUP(drive)->polling = 0;
458 return ide_started;
459 }
460 return 0;
461 } else {
462 return 0;
463 }
464}
465
466/**
467 * siimage_pre_reset - reset hook
468 * @drive: IDE device being reset
469 *
470 * For the SATA devices we need to handle recalibration/geometry
471 * differently
472 */
473
474static void siimage_pre_reset (ide_drive_t *drive)
475{
476 if (drive->media != ide_disk)
477 return;
478
479 if (is_sata(HWIF(drive)))
480 {
481 drive->special.b.set_geometry = 0;
482 drive->special.b.recalibrate = 0;
483 }
484}
485
486/**
487 * siimage_reset - reset a device on an siimage controller
488 * @drive: drive to reset
489 *
490 * Perform a controller level reset fo the device. For
491 * SATA we must also check the PHY.
492 */
493
494static void siimage_reset (ide_drive_t *drive)
495{
496 ide_hwif_t *hwif = HWIF(drive);
497 u8 reset = 0;
498 unsigned long addr = siimage_selreg(hwif, 0);
499
500 if (hwif->mmio) {
501 reset = hwif->INB(addr);
502 hwif->OUTB((reset|0x03), addr);
503 /* FIXME:posting */
504 udelay(25);
505 hwif->OUTB(reset, addr);
506 (void) hwif->INB(addr);
507 } else {
508 pci_read_config_byte(hwif->pci_dev, addr, &reset);
509 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
510 udelay(25);
511 pci_write_config_byte(hwif->pci_dev, addr, reset);
512 pci_read_config_byte(hwif->pci_dev, addr, &reset);
513 }
514
515 if (SATA_STATUS_REG) {
0ecdca26
BZ		 516 /* SATA_STATUS_REG is valid only when in MMIO mode */
517 u32 sata_stat = readl((void __iomem *)SATA_STATUS_REG);
1da177e4
LT		 518 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
519 hwif->name, sata_stat, __FUNCTION__);
520 if (!(sata_stat)) {
521 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
522 hwif->name, sata_stat);
523 drive->failures++;
524 }
525 }
526
527}
528
529/**
530 * proc_reports_siimage - add siimage controller to proc
531 * @dev: PCI device
532 * @clocking: SCSC value
533 * @name: controller name
534 *
535 * Report the clocking mode of the controller and add it to
536 * the /proc interface layer
537 */
538
539static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
540{
541 if (!pdev_is_sata(dev)) {
542 printk(KERN_INFO "%s: BASE CLOCK ", name);
543 clocking &= 0x03;
544 switch (clocking) {
545 case 0x03: printk("DISABLED!\n"); break;
546 case 0x02: printk("== 2X PCI\n"); break;
547 case 0x01: printk("== 133\n"); break;
548 case 0x00: printk("== 100\n"); break;
549 }
550 }
551}
552
553/**
554 * setup_mmio_siimage - switch an SI controller into MMIO
555 * @dev: PCI device we are configuring
556 * @name: device name
557 *
558 * Attempt to put the device into mmio mode. There are some slight
559 * complications here with certain systems where the mmio bar isnt
560 * mapped so we have to be sure we can fall back to I/O.
561 */
562
563static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
564{
565 unsigned long bar5 = pci_resource_start(dev, 5);
566 unsigned long barsize = pci_resource_len(dev, 5);
567 u8 tmpbyte = 0;
568 void __iomem *ioaddr;
d868dd19 569 u32 tmp, irq_mask;
1da177e4
LT		 570
571 /*
572 * Drop back to PIO if we can't map the mmio. Some
573 * systems seem to get terminally confused in the PCI
574 * spaces.
575 */
576
577 if(!request_mem_region(bar5, barsize, name))
578 {
579 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
580 return 0;
581 }
582
583 ioaddr = ioremap(bar5, barsize);
584
585 if (ioaddr == NULL)
586 {
587 release_mem_region(bar5, barsize);
588 return 0;
589 }
590
591 pci_set_master(dev);
592 pci_set_drvdata(dev, (void *) ioaddr);
593
594 if (pdev_is_sata(dev)) {
d868dd19
JL		 595 /* make sure IDE0/1 interrupts are not masked */
596 irq_mask = (1 << 22) | (1 << 23);
597 tmp = readl(ioaddr + 0x48);
598 if (tmp & irq_mask) {
599 tmp &= ~irq_mask;
600 writel(tmp, ioaddr + 0x48);
601 readl(ioaddr + 0x48); /* flush */
602 }
1da177e4
LT		 603 writel(0, ioaddr + 0x148);
604 writel(0, ioaddr + 0x1C8);
605 }
606
607 writeb(0, ioaddr + 0xB4);
608 writeb(0, ioaddr + 0xF4);
609 tmpbyte = readb(ioaddr + 0x4A);
610
611 switch(tmpbyte & 0x30) {
612 case 0x00:
613 /* In 100 MHz clocking, try and switch to 133 */
614 writeb(tmpbyte|0x10, ioaddr + 0x4A);
615 break;
616 case 0x10:
617 /* On 133Mhz clocking */
618 break;
619 case 0x20:
620 /* On PCIx2 clocking */
621 break;
622 case 0x30:
623 /* Clocking is disabled */
624 /* 133 clock attempt to force it on */
625 writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
626 break;
627 }
628
629 writeb( 0x72, ioaddr + 0xA1);
630 writew( 0x328A, ioaddr + 0xA2);
631 writel(0x62DD62DD, ioaddr + 0xA4);
632 writel(0x43924392, ioaddr + 0xA8);
633 writel(0x40094009, ioaddr + 0xAC);
634 writeb( 0x72, ioaddr + 0xE1);
635 writew( 0x328A, ioaddr + 0xE2);
636 writel(0x62DD62DD, ioaddr + 0xE4);
637 writel(0x43924392, ioaddr + 0xE8);
638 writel(0x40094009, ioaddr + 0xEC);
639
640 if (pdev_is_sata(dev)) {
641 writel(0xFFFF0000, ioaddr + 0x108);
642 writel(0xFFFF0000, ioaddr + 0x188);
643 writel(0x00680000, ioaddr + 0x148);
644 writel(0x00680000, ioaddr + 0x1C8);
645 }
646
647 tmpbyte = readb(ioaddr + 0x4A);
648
649 proc_reports_siimage(dev, (tmpbyte>>4), name);
650 return 1;
651}
652
653/**
654 * init_chipset_siimage - set up an SI device
655 * @dev: PCI device
656 * @name: device name
657 *
658 * Perform the initial PCI set up for this device. Attempt to switch
659 * to 133MHz clocking if the system isn't already set up to do it.
660 */
661
662static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
663{
664 u32 class_rev = 0;
665 u8 tmpbyte = 0;
666 u8 BA5_EN = 0;
667
668 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
669 class_rev &= 0xff;
670 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
671
672 pci_read_config_byte(dev, 0x8A, &BA5_EN);
673 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
674 if (setup_mmio_siimage(dev, name)) {
675 return 0;
676 }
677 }
678
679 pci_write_config_byte(dev, 0x80, 0x00);
680 pci_write_config_byte(dev, 0x84, 0x00);
681 pci_read_config_byte(dev, 0x8A, &tmpbyte);
682 switch(tmpbyte & 0x30) {
683 case 0x00:
684 /* 133 clock attempt to force it on */
685 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
686 case 0x30:
687 /* if clocking is disabled */
688 /* 133 clock attempt to force it on */
689 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
690 case 0x10:
691 /* 133 already */
692 break;
693 case 0x20:
694 /* BIOS set PCI x2 clocking */
695 break;
696 }
697
698 pci_read_config_byte(dev, 0x8A, &tmpbyte);
699
700 pci_write_config_byte(dev, 0xA1, 0x72);
701 pci_write_config_word(dev, 0xA2, 0x328A);
702 pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
703 pci_write_config_dword(dev, 0xA8, 0x43924392);
704 pci_write_config_dword(dev, 0xAC, 0x40094009);
705 pci_write_config_byte(dev, 0xB1, 0x72);
706 pci_write_config_word(dev, 0xB2, 0x328A);
707 pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
708 pci_write_config_dword(dev, 0xB8, 0x43924392);
709 pci_write_config_dword(dev, 0xBC, 0x40094009);
710
711 proc_reports_siimage(dev, (tmpbyte>>4), name);
712 return 0;
713}
714
715/**
716 * init_mmio_iops_siimage - set up the iops for MMIO
717 * @hwif: interface to set up
718 *
719 * The basic setup here is fairly simple, we can use standard MMIO
720 * operations. However we do have to set the taskfile register offsets
721 * by hand as there isnt a standard defined layout for them this
722 * time.
723 *
724 * The hardware supports buffered taskfiles and also some rather nice
19c1ef5f 725 * extended PRD tables. For better SI3112 support use the libata driver
1da177e4
LT		 726 */
727
728static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
729{
730 struct pci_dev *dev = hwif->pci_dev;
731 void *addr = pci_get_drvdata(dev);
732 u8 ch = hwif->channel;
733 hw_regs_t hw;
734 unsigned long base;
735
736 /*
737 * Fill in the basic HWIF bits
738 */
739
740 default_hwif_mmiops(hwif);
741 hwif->hwif_data = addr;
742
743 /*
744 * Now set up the hw. We have to do this ourselves as
59c51591 745 * the MMIO layout isnt the same as the standard port
1da177e4
LT		 746 * based I/O
747 */
748
749 memset(&hw, 0, sizeof(hw_regs_t));
750
751 base = (unsigned long)addr;
752 if (ch)
753 base += 0xC0;
754 else
755 base += 0x80;
756
757 /*
758 * The buffered task file doesn't have status/control
759 * so we can't currently use it sanely since we want to
760 * use LBA48 mode.
761 */
1da177e4
LT		 762 hw.io_ports[IDE_DATA_OFFSET] = base;
763 hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
764 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
765 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
766 hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
767 hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
768 hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
769 hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
770 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
771
772 hw.io_ports[IDE_IRQ_OFFSET] = 0;
773
774 if (pdev_is_sata(dev)) {
775 base = (unsigned long)addr;
776 if (ch)
777 base += 0x80;
778 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
779 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
780 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
781 hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140;
782 hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144;
783 hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148;
784 }
785
786 hw.irq = hwif->pci_dev->irq;
787
788 memcpy(&hwif->hw, &hw, sizeof(hw));
789 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
790
791 hwif->irq = hw.irq;
792
793 base = (unsigned long) addr;
794
1da177e4 795 hwif->dma_base = base + (ch ? 0x08 : 0x00);
2ad1e558
BZ		 796
797 hwif->mmio = 1;
1da177e4
LT		 798}
799
800static int is_dev_seagate_sata(ide_drive_t *drive)
801{
802 const char *s = &drive->id->model[0];
803 unsigned len;
804
805 if (!drive->present)
806 return 0;
807
808 len = strnlen(s, sizeof(drive->id->model));
809
810 if ((len > 4) && (!memcmp(s, "ST", 2))) {
811 if ((!memcmp(s + len - 2, "AS", 2)) ||
812 (!memcmp(s + len - 3, "ASL", 3))) {
813 printk(KERN_INFO "%s: applying pessimistic Seagate "
814 "errata fix\n", drive->name);
815 return 1;
816 }
817 }
818 return 0;
819}
820
821/**
822 * siimage_fixup - post probe fixups
823 * @hwif: interface to fix up
824 *
825 * Called after drive probe we use this to decide whether the
826 * Seagate fixup must be applied. This used to be in init_iops but
827 * that can occur before we know what drives are present.
828 */
829
830static void __devinit siimage_fixup(ide_hwif_t *hwif)
831{
832 /* Try and raise the rqsize */
833 if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0]))
834 hwif->rqsize = 128;
835}
836
837/**
838 * init_iops_siimage - set up iops
839 * @hwif: interface to set up
840 *
841 * Do the basic setup for the SIIMAGE hardware interface
842 * and then do the MMIO setup if we can. This is the first
843 * look in we get for setting up the hwif so that we
844 * can get the iops right before using them.
845 */
846
847static void __devinit init_iops_siimage(ide_hwif_t *hwif)
848{
849 struct pci_dev *dev = hwif->pci_dev;
850 u32 class_rev = 0;
851
852 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
853 class_rev &= 0xff;
854
855 hwif->hwif_data = NULL;
856
857 /* Pessimal until we finish probing */
858 hwif->rqsize = 15;
859
860 if (pci_get_drvdata(dev) == NULL)
861 return;
862 init_mmio_iops_siimage(hwif);
863}
864
865/**
866 * ata66_siimage - check for 80 pin cable
867 * @hwif: interface to check
868 *
869 * Check for the presence of an ATA66 capable cable on the
870 * interface.
871 */
872
49521f97 873static u8 __devinit ata66_siimage(ide_hwif_t *hwif)
1da177e4
LT		 874{
875 unsigned long addr = siimage_selreg(hwif, 0);
49521f97
BZ		 876 u8 ata66 = 0;
877
878 if (pci_get_drvdata(hwif->pci_dev) == NULL)
1da177e4 879 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
49521f97
BZ		 880 else
881 ata66 = hwif->INB(addr);
1da177e4 882
49521f97 883 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
1da177e4
LT		 884}
885
886/**
887 * init_hwif_siimage - set up hwif structs
888 * @hwif: interface to set up
889 *
890 * We do the basic set up of the interface structure. The SIIMAGE
891 * requires several custom handlers so we override the default
892 * ide DMA handlers appropriately
893 */
894
895static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
896{
897 hwif->autodma = 0;
898
899 hwif->resetproc = &siimage_reset;
900 hwif->speedproc = &siimage_tune_chipset;
26bcb879 901 hwif->set_pio_mode = &sil_set_pio_mode;
1da177e4
LT		 902 hwif->reset_poll = &siimage_reset_poll;
903 hwif->pre_reset = &siimage_pre_reset;
2d5eaa6d 904 hwif->udma_filter = &sil_udma_filter;
1da177e4 905
19c1ef5f
AC		 906 if(is_sata(hwif)) {
907 static int first = 1;
908
1da177e4
LT		 909 hwif->busproc = &siimage_busproc;
910
19c1ef5f
AC		 911 if (first) {
912 printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n");
913 first = 0;
914 }
915 }
328dcbb6
BZ		 916
917 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
918
919 if (hwif->dma_base == 0)
1da177e4 920 return;
1da177e4
LT		 921
922 hwif->ultra_mask = 0x7f;
923 hwif->mwdma_mask = 0x07;
1da177e4
LT		 924
925 if (!is_sata(hwif))
926 hwif->atapi_dma = 1;
927
928 hwif->ide_dma_check = &siimage_config_drive_for_dma;
49521f97
BZ		 929
930 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
931 hwif->cbl = ata66_siimage(hwif);
1da177e4
LT		 932
933 if (hwif->mmio) {
934 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
935 } else {
936 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
937 }
938
939 /*
940 * The BIOS often doesn't set up DMA on this controller
941 * so we always do it.
942 */
943
944 hwif->autodma = 1;
945 hwif->drives[0].autodma = hwif->autodma;
946 hwif->drives[1].autodma = hwif->autodma;
947}
948
949#define DECLARE_SII_DEV(name_str) \
950 { \
951 .name = name_str, \
952 .init_chipset = init_chipset_siimage, \
953 .init_iops = init_iops_siimage, \
954 .init_hwif = init_hwif_siimage, \
955 .fixup = siimage_fixup, \
1da177e4
LT		 956 .autodma = AUTODMA, \
957 .bootable = ON_BOARD, \
4099d143 958 .pio_mask = ATA_PIO4, \
1da177e4
LT		 959 }
960
961static ide_pci_device_t siimage_chipsets[] __devinitdata = {
962 /* 0 */ DECLARE_SII_DEV("SiI680"),
963 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
964 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
965};
966
967/**
968 * siimage_init_one - pci layer discovery entry
969 * @dev: PCI device
970 * @id: ident table entry
971 *
972 * Called by the PCI code when it finds an SI680 or SI3112 controller.
973 * We then use the IDE PCI generic helper to do most of the work.
974 */
975
976static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
977{
978 return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
979}
980
981static struct pci_device_id siimage_pci_tbl[] = {
28a2a3f5 982 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1da177e4 983#ifdef CONFIG_BLK_DEV_IDE_SATA
28a2a3f5
AC		 984 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
985 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1da177e4
LT		 986#endif
987 { 0, },
988};
989MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
990
991static struct pci_driver driver = {
992 .name = "SiI_IDE",
993 .id_table = siimage_pci_tbl,
994 .probe = siimage_init_one,
995};
996
82ab1eec 997static int __init siimage_ide_init(void)
1da177e4
LT		 998{
999 return ide_pci_register_driver(&driver);
1000}
1001
1002module_init(siimage_ide_init);
1003
1004MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1005MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1006MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)