Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> |
3 | * Copyright (C) 2003 Red Hat <alan@redhat.com> | |
075cb655 | 4 | * Copyright (C) 2007 MontaVista Software, Inc. |
328dcbb6 | 5 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
6 | * |
7 | * May be copied or modified under the terms of the GNU General Public License | |
8 | * | |
bf4c796d JG |
9 | * Documentation for CMD680: |
10 | * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 | |
11 | * | |
12 | * Documentation for SiI 3112: | |
13 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
14 | * | |
15 | * Errata and other documentation only available under NDA. | |
1da177e4 LT |
16 | * |
17 | * | |
18 | * FAQ Items: | |
19 | * If you are using Marvell SATA-IDE adapters with Maxtor drives | |
20 | * ensure the system is set up for ATA100/UDMA5 not UDMA6. | |
21 | * | |
22 | * If you are using WD drives with SATA bridges you must set the | |
23 | * drive to "Single". "Master" will hang | |
24 | * | |
25 | * If you have strange problems with nVidia chipset systems please | |
26 | * see the SI support documentation and update your system BIOS | |
3a4fa0a2 | 27 | * if necessary |
8693d3e4 AC |
28 | * |
29 | * The Dell DRAC4 has some interesting features including effectively hot | |
30 | * unplugging/replugging the virtual CD interface when the DRAC is reset. | |
31 | * This often causes drivers/ide/siimage to panic but is ok with the rather | |
32 | * smarter code in libata. | |
328dcbb6 BZ |
33 | * |
34 | * TODO: | |
35 | * - IORDY fixes | |
36 | * - VDMA support | |
1da177e4 LT |
37 | */ |
38 | ||
1da177e4 LT |
39 | #include <linux/types.h> |
40 | #include <linux/module.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/hdreg.h> | |
44 | #include <linux/ide.h> | |
45 | #include <linux/init.h> | |
46 | ||
47 | #include <asm/io.h> | |
48 | ||
1da177e4 LT |
49 | /** |
50 | * pdev_is_sata - check if device is SATA | |
51 | * @pdev: PCI device to check | |
52 | * | |
53 | * Returns true if this is a SATA controller | |
54 | */ | |
55 | ||
56 | static int pdev_is_sata(struct pci_dev *pdev) | |
57 | { | |
438c4702 BZ |
58 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
59 | switch(pdev->device) { | |
1da177e4 LT |
60 | case PCI_DEVICE_ID_SII_3112: |
61 | case PCI_DEVICE_ID_SII_1210SA: | |
62 | return 1; | |
63 | case PCI_DEVICE_ID_SII_680: | |
64 | return 0; | |
65 | } | |
66 | BUG(); | |
438c4702 | 67 | #endif |
1da177e4 LT |
68 | return 0; |
69 | } | |
438c4702 | 70 | |
1da177e4 LT |
71 | /** |
72 | * is_sata - check if hwif is SATA | |
73 | * @hwif: interface to check | |
74 | * | |
75 | * Returns true if this is a SATA controller | |
76 | */ | |
77 | ||
78 | static inline int is_sata(ide_hwif_t *hwif) | |
79 | { | |
36501650 | 80 | return pdev_is_sata(to_pci_dev(hwif->dev)); |
1da177e4 LT |
81 | } |
82 | ||
83 | /** | |
84 | * siimage_selreg - return register base | |
85 | * @hwif: interface | |
86 | * @r: config offset | |
87 | * | |
88 | * Turn a config register offset into the right address in either | |
89 | * PCI space or MMIO space to access the control register in question | |
90 | * Thankfully this is a configuration operation so isnt performance | |
91 | * criticial. | |
92 | */ | |
93 | ||
94 | static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) | |
95 | { | |
96 | unsigned long base = (unsigned long)hwif->hwif_data; | |
97 | base += 0xA0 + r; | |
98 | if(hwif->mmio) | |
99 | base += (hwif->channel << 6); | |
100 | else | |
101 | base += (hwif->channel << 4); | |
102 | return base; | |
103 | } | |
104 | ||
105 | /** | |
106 | * siimage_seldev - return register base | |
107 | * @hwif: interface | |
108 | * @r: config offset | |
109 | * | |
110 | * Turn a config register offset into the right address in either | |
111 | * PCI space or MMIO space to access the control register in question | |
112 | * including accounting for the unit shift. | |
113 | */ | |
114 | ||
115 | static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) | |
116 | { | |
117 | ide_hwif_t *hwif = HWIF(drive); | |
118 | unsigned long base = (unsigned long)hwif->hwif_data; | |
119 | base += 0xA0 + r; | |
120 | if(hwif->mmio) | |
121 | base += (hwif->channel << 6); | |
122 | else | |
123 | base += (hwif->channel << 4); | |
124 | base |= drive->select.b.unit << drive->select.b.unit; | |
125 | return base; | |
126 | } | |
127 | ||
128 | /** | |
2d5eaa6d BZ |
129 | * sil_udma_filter - compute UDMA mask |
130 | * @drive: IDE device | |
131 | * | |
132 | * Compute the available UDMA speeds for the device on the interface. | |
1da177e4 | 133 | * |
1da177e4 | 134 | * For the CMD680 this depends on the clocking mode (scsc), for the |
2d5eaa6d | 135 | * SI3112 SATA controller life is a bit simpler. |
1da177e4 | 136 | */ |
2d5eaa6d | 137 | |
438c4702 | 138 | static u8 sil_pata_udma_filter(ide_drive_t *drive) |
1da177e4 | 139 | { |
2d5eaa6d | 140 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 141 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 142 | unsigned long base = (unsigned long) hwif->hwif_data; |
2d5eaa6d | 143 | u8 mask = 0, scsc = 0; |
1da177e4 LT |
144 | |
145 | if (hwif->mmio) | |
146 | scsc = hwif->INB(base + 0x4A); | |
147 | else | |
36501650 | 148 | pci_read_config_byte(dev, 0x8A, &scsc); |
1da177e4 | 149 | |
1da177e4 | 150 | if ((scsc & 0x30) == 0x10) /* 133 */ |
438c4702 | 151 | mask = ATA_UDMA6; |
1da177e4 | 152 | else if ((scsc & 0x30) == 0x20) /* 2xPCI */ |
438c4702 | 153 | mask = ATA_UDMA6; |
1da177e4 | 154 | else if ((scsc & 0x30) == 0x00) /* 100 */ |
438c4702 | 155 | mask = ATA_UDMA5; |
1da177e4 LT |
156 | else /* Disabled ? */ |
157 | BUG(); | |
438c4702 | 158 | |
2d5eaa6d | 159 | return mask; |
1da177e4 LT |
160 | } |
161 | ||
438c4702 BZ |
162 | static u8 sil_sata_udma_filter(ide_drive_t *drive) |
163 | { | |
164 | return strstr(drive->id->model, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6; | |
165 | } | |
166 | ||
1da177e4 | 167 | /** |
88b2b32b BZ |
168 | * sil_set_pio_mode - set host controller for PIO mode |
169 | * @drive: drive | |
170 | * @pio: PIO mode number | |
1da177e4 LT |
171 | * |
172 | * Load the timing settings for this device mode into the | |
173 | * controller. If we are in PIO mode 3 or 4 turn on IORDY | |
174 | * monitoring (bit 9). The TF timing is bits 31:16 | |
175 | */ | |
328dcbb6 | 176 | |
88b2b32b | 177 | static void sil_set_pio_mode(ide_drive_t *drive, u8 pio) |
1da177e4 | 178 | { |
328dcbb6 BZ |
179 | const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; |
180 | const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; | |
181 | ||
1da177e4 | 182 | ide_hwif_t *hwif = HWIF(drive); |
a87a87cc | 183 | ide_drive_t *pair = ide_get_paired_drive(drive); |
1da177e4 LT |
184 | u32 speedt = 0; |
185 | u16 speedp = 0; | |
186 | unsigned long addr = siimage_seldev(drive, 0x04); | |
187 | unsigned long tfaddr = siimage_selreg(hwif, 0x02); | |
ffe5415c | 188 | unsigned long base = (unsigned long)hwif->hwif_data; |
328dcbb6 | 189 | u8 tf_pio = pio; |
ffe5415c BZ |
190 | u8 addr_mask = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84) |
191 | : (hwif->mmio ? 0xB4 : 0x80); | |
192 | u8 mode = 0; | |
193 | u8 unit = drive->select.b.unit; | |
328dcbb6 BZ |
194 | |
195 | /* trim *taskfile* PIO to the slowest of the master/slave */ | |
196 | if (pair->present) { | |
2134758d | 197 | u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4); |
328dcbb6 BZ |
198 | |
199 | if (pair_pio < tf_pio) | |
200 | tf_pio = pair_pio; | |
1da177e4 | 201 | } |
075cb655 | 202 | |
328dcbb6 BZ |
203 | /* cheat for now and use the docs */ |
204 | speedp = data_speed[pio]; | |
205 | speedt = tf_speed[tf_pio]; | |
206 | ||
075cb655 SS |
207 | if (hwif->mmio) { |
208 | hwif->OUTW(speedp, addr); | |
209 | hwif->OUTW(speedt, tfaddr); | |
1da177e4 | 210 | /* Now set up IORDY */ |
328dcbb6 | 211 | if (pio > 2) |
1da177e4 LT |
212 | hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2); |
213 | else | |
214 | hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2); | |
ffe5415c BZ |
215 | |
216 | mode = hwif->INB(base + addr_mask); | |
217 | mode &= ~(unit ? 0x30 : 0x03); | |
218 | mode |= (unit ? 0x10 : 0x01); | |
219 | hwif->OUTB(mode, base + addr_mask); | |
075cb655 | 220 | } else { |
36501650 BZ |
221 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
222 | ||
223 | pci_write_config_word(dev, addr, speedp); | |
224 | pci_write_config_word(dev, tfaddr, speedt); | |
225 | pci_read_config_word(dev, tfaddr - 2, &speedp); | |
1da177e4 LT |
226 | speedp &= ~0x200; |
227 | /* Set IORDY for mode 3 or 4 */ | |
328dcbb6 | 228 | if (pio > 2) |
1da177e4 | 229 | speedp |= 0x200; |
36501650 | 230 | pci_write_config_word(dev, tfaddr - 2, speedp); |
ffe5415c | 231 | |
36501650 | 232 | pci_read_config_byte(dev, addr_mask, &mode); |
ffe5415c BZ |
233 | mode &= ~(unit ? 0x30 : 0x03); |
234 | mode |= (unit ? 0x10 : 0x01); | |
36501650 | 235 | pci_write_config_byte(dev, addr_mask, mode); |
1da177e4 LT |
236 | } |
237 | } | |
238 | ||
1da177e4 | 239 | /** |
88b2b32b BZ |
240 | * sil_set_dma_mode - set host controller for DMA mode |
241 | * @drive: drive | |
242 | * @speed: DMA mode | |
1da177e4 | 243 | * |
88b2b32b | 244 | * Tune the SiI chipset for the desired DMA mode. |
1da177e4 | 245 | */ |
f212ff28 | 246 | |
88b2b32b | 247 | static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 LT |
248 | { |
249 | u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; | |
250 | u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; | |
251 | u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; | |
252 | ||
253 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 254 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
255 | u16 ultra = 0, multi = 0; |
256 | u8 mode = 0, unit = drive->select.b.unit; | |
1da177e4 LT |
257 | unsigned long base = (unsigned long)hwif->hwif_data; |
258 | u8 scsc = 0, addr_mask = ((hwif->channel) ? | |
259 | ((hwif->mmio) ? 0xF4 : 0x84) : | |
260 | ((hwif->mmio) ? 0xB4 : 0x80)); | |
261 | ||
262 | unsigned long ma = siimage_seldev(drive, 0x08); | |
263 | unsigned long ua = siimage_seldev(drive, 0x0C); | |
264 | ||
265 | if (hwif->mmio) { | |
266 | scsc = hwif->INB(base + 0x4A); | |
267 | mode = hwif->INB(base + addr_mask); | |
268 | multi = hwif->INW(ma); | |
269 | ultra = hwif->INW(ua); | |
270 | } else { | |
36501650 BZ |
271 | pci_read_config_byte(dev, 0x8A, &scsc); |
272 | pci_read_config_byte(dev, addr_mask, &mode); | |
273 | pci_read_config_word(dev, ma, &multi); | |
274 | pci_read_config_word(dev, ua, &ultra); | |
1da177e4 LT |
275 | } |
276 | ||
277 | mode &= ~((unit) ? 0x30 : 0x03); | |
278 | ultra &= ~0x3F; | |
279 | scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; | |
280 | ||
281 | scsc = is_sata(hwif) ? 1 : scsc; | |
282 | ||
4db90a14 BZ |
283 | if (speed >= XFER_UDMA_0) { |
284 | multi = dma[2]; | |
285 | ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] : | |
286 | ultra5[speed - XFER_UDMA_0]); | |
287 | mode |= (unit ? 0x30 : 0x03); | |
288 | } else { | |
289 | multi = dma[speed - XFER_MW_DMA_0]; | |
290 | mode |= (unit ? 0x20 : 0x02); | |
1da177e4 LT |
291 | } |
292 | ||
293 | if (hwif->mmio) { | |
294 | hwif->OUTB(mode, base + addr_mask); | |
295 | hwif->OUTW(multi, ma); | |
296 | hwif->OUTW(ultra, ua); | |
297 | } else { | |
36501650 BZ |
298 | pci_write_config_byte(dev, addr_mask, mode); |
299 | pci_write_config_word(dev, ma, multi); | |
300 | pci_write_config_word(dev, ua, ultra); | |
1da177e4 | 301 | } |
1da177e4 LT |
302 | } |
303 | ||
1da177e4 LT |
304 | /* returns 1 if dma irq issued, 0 otherwise */ |
305 | static int siimage_io_ide_dma_test_irq (ide_drive_t *drive) | |
306 | { | |
307 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 308 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
309 | u8 dma_altstat = 0; |
310 | unsigned long addr = siimage_selreg(hwif, 1); | |
311 | ||
312 | /* return 1 if INTR asserted */ | |
313 | if ((hwif->INB(hwif->dma_status) & 4) == 4) | |
314 | return 1; | |
315 | ||
316 | /* return 1 if Device INTR asserted */ | |
36501650 | 317 | pci_read_config_byte(dev, addr, &dma_altstat); |
1da177e4 LT |
318 | if (dma_altstat & 8) |
319 | return 0; //return 1; | |
320 | return 0; | |
321 | } | |
322 | ||
1da177e4 LT |
323 | /** |
324 | * siimage_mmio_ide_dma_test_irq - check we caused an IRQ | |
325 | * @drive: drive we are testing | |
326 | * | |
327 | * Check if we caused an IDE DMA interrupt. We may also have caused | |
328 | * SATA status interrupts, if so we clean them up and continue. | |
329 | */ | |
330 | ||
331 | static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive) | |
332 | { | |
333 | ide_hwif_t *hwif = HWIF(drive); | |
1da177e4 LT |
334 | unsigned long addr = siimage_selreg(hwif, 0x1); |
335 | ||
336 | if (SATA_ERROR_REG) { | |
438c4702 BZ |
337 | unsigned long base = (unsigned long)hwif->hwif_data; |
338 | ||
0ecdca26 | 339 | u32 ext_stat = readl((void __iomem *)(base + 0x10)); |
1da177e4 LT |
340 | u8 watchdog = 0; |
341 | if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { | |
0ecdca26 BZ |
342 | u32 sata_error = readl((void __iomem *)SATA_ERROR_REG); |
343 | writel(sata_error, (void __iomem *)SATA_ERROR_REG); | |
1da177e4 | 344 | watchdog = (sata_error & 0x00680000) ? 1 : 0; |
1da177e4 LT |
345 | printk(KERN_WARNING "%s: sata_error = 0x%08x, " |
346 | "watchdog = %d, %s\n", | |
347 | drive->name, sata_error, watchdog, | |
348 | __FUNCTION__); | |
1da177e4 LT |
349 | |
350 | } else { | |
351 | watchdog = (ext_stat & 0x8000) ? 1 : 0; | |
352 | } | |
353 | ext_stat >>= 16; | |
354 | ||
355 | if (!(ext_stat & 0x0404) && !watchdog) | |
356 | return 0; | |
357 | } | |
358 | ||
359 | /* return 1 if INTR asserted */ | |
0ecdca26 | 360 | if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04) |
1da177e4 LT |
361 | return 1; |
362 | ||
363 | /* return 1 if Device INTR asserted */ | |
0ecdca26 | 364 | if ((readb((void __iomem *)addr) & 8) == 8) |
1da177e4 LT |
365 | return 0; //return 1; |
366 | ||
367 | return 0; | |
368 | } | |
369 | ||
370 | /** | |
438c4702 | 371 | * sil_sata_busproc - bus isolation IOCTL |
1da177e4 LT |
372 | * @drive: drive to isolate/restore |
373 | * @state: bus state to set | |
374 | * | |
375 | * Used by the SII3112 to handle bus isolation. As this is a | |
376 | * SATA controller the work required is quite limited, we | |
377 | * just have to clean up the statistics | |
378 | */ | |
438c4702 BZ |
379 | |
380 | static int sil_sata_busproc(ide_drive_t * drive, int state) | |
1da177e4 LT |
381 | { |
382 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 383 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
384 | u32 stat_config = 0; |
385 | unsigned long addr = siimage_selreg(hwif, 0); | |
386 | ||
0ecdca26 BZ |
387 | if (hwif->mmio) |
388 | stat_config = readl((void __iomem *)addr); | |
389 | else | |
36501650 | 390 | pci_read_config_dword(dev, addr, &stat_config); |
1da177e4 LT |
391 | |
392 | switch (state) { | |
393 | case BUSSTATE_ON: | |
394 | hwif->drives[0].failures = 0; | |
395 | hwif->drives[1].failures = 0; | |
396 | break; | |
397 | case BUSSTATE_OFF: | |
398 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | |
399 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
400 | break; | |
401 | case BUSSTATE_TRISTATE: | |
402 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | |
403 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
404 | break; | |
405 | default: | |
406 | return -EINVAL; | |
407 | } | |
408 | hwif->bus_state = state; | |
409 | return 0; | |
410 | } | |
411 | ||
412 | /** | |
438c4702 | 413 | * sil_sata_reset_poll - wait for SATA reset |
1da177e4 LT |
414 | * @drive: drive we are resetting |
415 | * | |
416 | * Poll the SATA phy and see whether it has come back from the dead | |
417 | * yet. | |
418 | */ | |
438c4702 BZ |
419 | |
420 | static int sil_sata_reset_poll(ide_drive_t *drive) | |
1da177e4 LT |
421 | { |
422 | if (SATA_STATUS_REG) { | |
423 | ide_hwif_t *hwif = HWIF(drive); | |
424 | ||
0ecdca26 BZ |
425 | /* SATA_STATUS_REG is valid only when in MMIO mode */ |
426 | if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) { | |
1da177e4 | 427 | printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", |
0ecdca26 | 428 | hwif->name, readl((void __iomem *)SATA_STATUS_REG)); |
1da177e4 LT |
429 | HWGROUP(drive)->polling = 0; |
430 | return ide_started; | |
431 | } | |
1da177e4 | 432 | } |
438c4702 BZ |
433 | |
434 | return 0; | |
1da177e4 LT |
435 | } |
436 | ||
437 | /** | |
438c4702 | 438 | * sil_sata_pre_reset - reset hook |
1da177e4 LT |
439 | * @drive: IDE device being reset |
440 | * | |
441 | * For the SATA devices we need to handle recalibration/geometry | |
442 | * differently | |
443 | */ | |
1da177e4 | 444 | |
438c4702 BZ |
445 | static void sil_sata_pre_reset(ide_drive_t *drive) |
446 | { | |
447 | if (drive->media == ide_disk) { | |
1da177e4 LT |
448 | drive->special.b.set_geometry = 0; |
449 | drive->special.b.recalibrate = 0; | |
450 | } | |
451 | } | |
452 | ||
1da177e4 LT |
453 | /** |
454 | * proc_reports_siimage - add siimage controller to proc | |
455 | * @dev: PCI device | |
456 | * @clocking: SCSC value | |
457 | * @name: controller name | |
458 | * | |
459 | * Report the clocking mode of the controller and add it to | |
460 | * the /proc interface layer | |
461 | */ | |
462 | ||
463 | static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name) | |
464 | { | |
465 | if (!pdev_is_sata(dev)) { | |
466 | printk(KERN_INFO "%s: BASE CLOCK ", name); | |
467 | clocking &= 0x03; | |
468 | switch (clocking) { | |
469 | case 0x03: printk("DISABLED!\n"); break; | |
470 | case 0x02: printk("== 2X PCI\n"); break; | |
471 | case 0x01: printk("== 133\n"); break; | |
472 | case 0x00: printk("== 100\n"); break; | |
473 | } | |
474 | } | |
475 | } | |
476 | ||
477 | /** | |
478 | * setup_mmio_siimage - switch an SI controller into MMIO | |
479 | * @dev: PCI device we are configuring | |
480 | * @name: device name | |
481 | * | |
482 | * Attempt to put the device into mmio mode. There are some slight | |
483 | * complications here with certain systems where the mmio bar isnt | |
484 | * mapped so we have to be sure we can fall back to I/O. | |
485 | */ | |
486 | ||
487 | static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name) | |
488 | { | |
489 | unsigned long bar5 = pci_resource_start(dev, 5); | |
490 | unsigned long barsize = pci_resource_len(dev, 5); | |
491 | u8 tmpbyte = 0; | |
492 | void __iomem *ioaddr; | |
d868dd19 | 493 | u32 tmp, irq_mask; |
1da177e4 LT |
494 | |
495 | /* | |
496 | * Drop back to PIO if we can't map the mmio. Some | |
497 | * systems seem to get terminally confused in the PCI | |
498 | * spaces. | |
499 | */ | |
500 | ||
501 | if(!request_mem_region(bar5, barsize, name)) | |
502 | { | |
503 | printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n"); | |
504 | return 0; | |
505 | } | |
506 | ||
507 | ioaddr = ioremap(bar5, barsize); | |
508 | ||
509 | if (ioaddr == NULL) | |
510 | { | |
511 | release_mem_region(bar5, barsize); | |
512 | return 0; | |
513 | } | |
514 | ||
515 | pci_set_master(dev); | |
516 | pci_set_drvdata(dev, (void *) ioaddr); | |
517 | ||
518 | if (pdev_is_sata(dev)) { | |
d868dd19 JL |
519 | /* make sure IDE0/1 interrupts are not masked */ |
520 | irq_mask = (1 << 22) | (1 << 23); | |
521 | tmp = readl(ioaddr + 0x48); | |
522 | if (tmp & irq_mask) { | |
523 | tmp &= ~irq_mask; | |
524 | writel(tmp, ioaddr + 0x48); | |
525 | readl(ioaddr + 0x48); /* flush */ | |
526 | } | |
1da177e4 LT |
527 | writel(0, ioaddr + 0x148); |
528 | writel(0, ioaddr + 0x1C8); | |
529 | } | |
530 | ||
531 | writeb(0, ioaddr + 0xB4); | |
532 | writeb(0, ioaddr + 0xF4); | |
533 | tmpbyte = readb(ioaddr + 0x4A); | |
534 | ||
535 | switch(tmpbyte & 0x30) { | |
536 | case 0x00: | |
537 | /* In 100 MHz clocking, try and switch to 133 */ | |
538 | writeb(tmpbyte|0x10, ioaddr + 0x4A); | |
539 | break; | |
540 | case 0x10: | |
541 | /* On 133Mhz clocking */ | |
542 | break; | |
543 | case 0x20: | |
544 | /* On PCIx2 clocking */ | |
545 | break; | |
546 | case 0x30: | |
547 | /* Clocking is disabled */ | |
548 | /* 133 clock attempt to force it on */ | |
549 | writeb(tmpbyte & ~0x20, ioaddr + 0x4A); | |
550 | break; | |
551 | } | |
552 | ||
553 | writeb( 0x72, ioaddr + 0xA1); | |
554 | writew( 0x328A, ioaddr + 0xA2); | |
555 | writel(0x62DD62DD, ioaddr + 0xA4); | |
556 | writel(0x43924392, ioaddr + 0xA8); | |
557 | writel(0x40094009, ioaddr + 0xAC); | |
558 | writeb( 0x72, ioaddr + 0xE1); | |
559 | writew( 0x328A, ioaddr + 0xE2); | |
560 | writel(0x62DD62DD, ioaddr + 0xE4); | |
561 | writel(0x43924392, ioaddr + 0xE8); | |
562 | writel(0x40094009, ioaddr + 0xEC); | |
563 | ||
564 | if (pdev_is_sata(dev)) { | |
565 | writel(0xFFFF0000, ioaddr + 0x108); | |
566 | writel(0xFFFF0000, ioaddr + 0x188); | |
567 | writel(0x00680000, ioaddr + 0x148); | |
568 | writel(0x00680000, ioaddr + 0x1C8); | |
569 | } | |
570 | ||
571 | tmpbyte = readb(ioaddr + 0x4A); | |
572 | ||
573 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
574 | return 1; | |
575 | } | |
576 | ||
577 | /** | |
578 | * init_chipset_siimage - set up an SI device | |
579 | * @dev: PCI device | |
580 | * @name: device name | |
581 | * | |
582 | * Perform the initial PCI set up for this device. Attempt to switch | |
583 | * to 133MHz clocking if the system isn't already set up to do it. | |
584 | */ | |
585 | ||
586 | static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name) | |
587 | { | |
fc212bb1 | 588 | u8 rev = dev->revision, tmpbyte = 0, BA5_EN = 0; |
1da177e4 | 589 | |
fc212bb1 | 590 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255); |
1da177e4 LT |
591 | |
592 | pci_read_config_byte(dev, 0x8A, &BA5_EN); | |
593 | if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) { | |
594 | if (setup_mmio_siimage(dev, name)) { | |
595 | return 0; | |
596 | } | |
597 | } | |
598 | ||
599 | pci_write_config_byte(dev, 0x80, 0x00); | |
600 | pci_write_config_byte(dev, 0x84, 0x00); | |
601 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
602 | switch(tmpbyte & 0x30) { | |
603 | case 0x00: | |
604 | /* 133 clock attempt to force it on */ | |
605 | pci_write_config_byte(dev, 0x8A, tmpbyte|0x10); | |
606 | case 0x30: | |
607 | /* if clocking is disabled */ | |
608 | /* 133 clock attempt to force it on */ | |
609 | pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20); | |
610 | case 0x10: | |
611 | /* 133 already */ | |
612 | break; | |
613 | case 0x20: | |
614 | /* BIOS set PCI x2 clocking */ | |
615 | break; | |
616 | } | |
617 | ||
618 | pci_read_config_byte(dev, 0x8A, &tmpbyte); | |
619 | ||
620 | pci_write_config_byte(dev, 0xA1, 0x72); | |
621 | pci_write_config_word(dev, 0xA2, 0x328A); | |
622 | pci_write_config_dword(dev, 0xA4, 0x62DD62DD); | |
623 | pci_write_config_dword(dev, 0xA8, 0x43924392); | |
624 | pci_write_config_dword(dev, 0xAC, 0x40094009); | |
625 | pci_write_config_byte(dev, 0xB1, 0x72); | |
626 | pci_write_config_word(dev, 0xB2, 0x328A); | |
627 | pci_write_config_dword(dev, 0xB4, 0x62DD62DD); | |
628 | pci_write_config_dword(dev, 0xB8, 0x43924392); | |
629 | pci_write_config_dword(dev, 0xBC, 0x40094009); | |
630 | ||
631 | proc_reports_siimage(dev, (tmpbyte>>4), name); | |
632 | return 0; | |
633 | } | |
634 | ||
635 | /** | |
636 | * init_mmio_iops_siimage - set up the iops for MMIO | |
637 | * @hwif: interface to set up | |
638 | * | |
639 | * The basic setup here is fairly simple, we can use standard MMIO | |
640 | * operations. However we do have to set the taskfile register offsets | |
641 | * by hand as there isnt a standard defined layout for them this | |
642 | * time. | |
643 | * | |
644 | * The hardware supports buffered taskfiles and also some rather nice | |
19c1ef5f | 645 | * extended PRD tables. For better SI3112 support use the libata driver |
1da177e4 LT |
646 | */ |
647 | ||
648 | static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif) | |
649 | { | |
36501650 | 650 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
651 | void *addr = pci_get_drvdata(dev); |
652 | u8 ch = hwif->channel; | |
653 | hw_regs_t hw; | |
654 | unsigned long base; | |
655 | ||
656 | /* | |
657 | * Fill in the basic HWIF bits | |
658 | */ | |
659 | ||
660 | default_hwif_mmiops(hwif); | |
661 | hwif->hwif_data = addr; | |
662 | ||
663 | /* | |
664 | * Now set up the hw. We have to do this ourselves as | |
59c51591 | 665 | * the MMIO layout isnt the same as the standard port |
1da177e4 LT |
666 | * based I/O |
667 | */ | |
668 | ||
669 | memset(&hw, 0, sizeof(hw_regs_t)); | |
670 | ||
671 | base = (unsigned long)addr; | |
672 | if (ch) | |
673 | base += 0xC0; | |
674 | else | |
675 | base += 0x80; | |
676 | ||
677 | /* | |
678 | * The buffered task file doesn't have status/control | |
679 | * so we can't currently use it sanely since we want to | |
680 | * use LBA48 mode. | |
681 | */ | |
1da177e4 LT |
682 | hw.io_ports[IDE_DATA_OFFSET] = base; |
683 | hw.io_ports[IDE_ERROR_OFFSET] = base + 1; | |
684 | hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2; | |
685 | hw.io_ports[IDE_SECTOR_OFFSET] = base + 3; | |
686 | hw.io_ports[IDE_LCYL_OFFSET] = base + 4; | |
687 | hw.io_ports[IDE_HCYL_OFFSET] = base + 5; | |
688 | hw.io_ports[IDE_SELECT_OFFSET] = base + 6; | |
689 | hw.io_ports[IDE_STATUS_OFFSET] = base + 7; | |
690 | hw.io_ports[IDE_CONTROL_OFFSET] = base + 10; | |
691 | ||
692 | hw.io_ports[IDE_IRQ_OFFSET] = 0; | |
693 | ||
694 | if (pdev_is_sata(dev)) { | |
695 | base = (unsigned long)addr; | |
696 | if (ch) | |
697 | base += 0x80; | |
698 | hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; | |
699 | hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; | |
700 | hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; | |
701 | hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140; | |
702 | hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144; | |
703 | hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148; | |
704 | } | |
705 | ||
9239b333 | 706 | memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports)); |
1da177e4 | 707 | |
9239b333 | 708 | hwif->irq = dev->irq; |
1da177e4 | 709 | |
9239b333 | 710 | hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00); |
2ad1e558 BZ |
711 | |
712 | hwif->mmio = 1; | |
1da177e4 LT |
713 | } |
714 | ||
715 | static int is_dev_seagate_sata(ide_drive_t *drive) | |
716 | { | |
717 | const char *s = &drive->id->model[0]; | |
718 | unsigned len; | |
719 | ||
1da177e4 LT |
720 | len = strnlen(s, sizeof(drive->id->model)); |
721 | ||
722 | if ((len > 4) && (!memcmp(s, "ST", 2))) { | |
723 | if ((!memcmp(s + len - 2, "AS", 2)) || | |
724 | (!memcmp(s + len - 3, "ASL", 3))) { | |
725 | printk(KERN_INFO "%s: applying pessimistic Seagate " | |
726 | "errata fix\n", drive->name); | |
727 | return 1; | |
728 | } | |
729 | } | |
730 | return 0; | |
731 | } | |
732 | ||
733 | /** | |
f01393e4 BZ |
734 | * sil_quirkproc - post probe fixups |
735 | * @drive: drive | |
1da177e4 LT |
736 | * |
737 | * Called after drive probe we use this to decide whether the | |
738 | * Seagate fixup must be applied. This used to be in init_iops but | |
739 | * that can occur before we know what drives are present. | |
740 | */ | |
741 | ||
f01393e4 | 742 | static void __devinit sil_quirkproc(ide_drive_t *drive) |
1da177e4 | 743 | { |
f01393e4 BZ |
744 | ide_hwif_t *hwif = drive->hwif; |
745 | ||
1da177e4 | 746 | /* Try and raise the rqsize */ |
f01393e4 | 747 | if (!is_sata(hwif) || !is_dev_seagate_sata(drive)) |
1da177e4 LT |
748 | hwif->rqsize = 128; |
749 | } | |
750 | ||
751 | /** | |
752 | * init_iops_siimage - set up iops | |
753 | * @hwif: interface to set up | |
754 | * | |
755 | * Do the basic setup for the SIIMAGE hardware interface | |
756 | * and then do the MMIO setup if we can. This is the first | |
757 | * look in we get for setting up the hwif so that we | |
758 | * can get the iops right before using them. | |
759 | */ | |
760 | ||
761 | static void __devinit init_iops_siimage(ide_hwif_t *hwif) | |
762 | { | |
36501650 BZ |
763 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
764 | ||
1da177e4 LT |
765 | hwif->hwif_data = NULL; |
766 | ||
767 | /* Pessimal until we finish probing */ | |
768 | hwif->rqsize = 15; | |
769 | ||
36501650 | 770 | if (pci_get_drvdata(dev) == NULL) |
1da177e4 | 771 | return; |
fc212bb1 | 772 | |
1da177e4 LT |
773 | init_mmio_iops_siimage(hwif); |
774 | } | |
775 | ||
776 | /** | |
777 | * ata66_siimage - check for 80 pin cable | |
778 | * @hwif: interface to check | |
779 | * | |
780 | * Check for the presence of an ATA66 capable cable on the | |
781 | * interface. | |
782 | */ | |
783 | ||
49521f97 | 784 | static u8 __devinit ata66_siimage(ide_hwif_t *hwif) |
1da177e4 | 785 | { |
36501650 | 786 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 787 | unsigned long addr = siimage_selreg(hwif, 0); |
49521f97 BZ |
788 | u8 ata66 = 0; |
789 | ||
36501650 BZ |
790 | if (pci_get_drvdata(dev) == NULL) |
791 | pci_read_config_byte(dev, addr, &ata66); | |
49521f97 BZ |
792 | else |
793 | ata66 = hwif->INB(addr); | |
1da177e4 | 794 | |
49521f97 | 795 | return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
1da177e4 LT |
796 | } |
797 | ||
798 | /** | |
799 | * init_hwif_siimage - set up hwif structs | |
800 | * @hwif: interface to set up | |
801 | * | |
802 | * We do the basic set up of the interface structure. The SIIMAGE | |
803 | * requires several custom handlers so we override the default | |
804 | * ide DMA handlers appropriately | |
805 | */ | |
806 | ||
807 | static void __devinit init_hwif_siimage(ide_hwif_t *hwif) | |
808 | { | |
438c4702 BZ |
809 | u8 sata = is_sata(hwif); |
810 | ||
26bcb879 | 811 | hwif->set_pio_mode = &sil_set_pio_mode; |
88b2b32b | 812 | hwif->set_dma_mode = &sil_set_dma_mode; |
f01393e4 | 813 | hwif->quirkproc = &sil_quirkproc; |
1da177e4 | 814 | |
438c4702 | 815 | if (sata) { |
19c1ef5f AC |
816 | static int first = 1; |
817 | ||
438c4702 BZ |
818 | hwif->busproc = &sil_sata_busproc; |
819 | hwif->reset_poll = &sil_sata_reset_poll; | |
820 | hwif->pre_reset = &sil_sata_pre_reset; | |
821 | hwif->udma_filter = &sil_sata_udma_filter; | |
1da177e4 | 822 | |
19c1ef5f AC |
823 | if (first) { |
824 | printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n"); | |
825 | first = 0; | |
826 | } | |
438c4702 BZ |
827 | } else |
828 | hwif->udma_filter = &sil_pata_udma_filter; | |
328dcbb6 | 829 | |
328dcbb6 | 830 | if (hwif->dma_base == 0) |
1da177e4 | 831 | return; |
1da177e4 | 832 | |
438c4702 | 833 | if (sata) |
33c1002e | 834 | hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
1da177e4 | 835 | |
49521f97 BZ |
836 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
837 | hwif->cbl = ata66_siimage(hwif); | |
1da177e4 LT |
838 | |
839 | if (hwif->mmio) { | |
840 | hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq; | |
841 | } else { | |
842 | hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq; | |
843 | } | |
1da177e4 LT |
844 | } |
845 | ||
846 | #define DECLARE_SII_DEV(name_str) \ | |
847 | { \ | |
848 | .name = name_str, \ | |
849 | .init_chipset = init_chipset_siimage, \ | |
850 | .init_iops = init_iops_siimage, \ | |
851 | .init_hwif = init_hwif_siimage, \ | |
7cab14a7 | 852 | .host_flags = IDE_HFLAG_BOOTABLE, \ |
4099d143 | 853 | .pio_mask = ATA_PIO4, \ |
5f8b6c34 BZ |
854 | .mwdma_mask = ATA_MWDMA2, \ |
855 | .udma_mask = ATA_UDMA6, \ | |
1da177e4 LT |
856 | } |
857 | ||
85620436 | 858 | static const struct ide_port_info siimage_chipsets[] __devinitdata = { |
1da177e4 LT |
859 | /* 0 */ DECLARE_SII_DEV("SiI680"), |
860 | /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"), | |
861 | /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA") | |
862 | }; | |
863 | ||
864 | /** | |
865 | * siimage_init_one - pci layer discovery entry | |
866 | * @dev: PCI device | |
867 | * @id: ident table entry | |
868 | * | |
869 | * Called by the PCI code when it finds an SI680 or SI3112 controller. | |
870 | * We then use the IDE PCI generic helper to do most of the work. | |
871 | */ | |
872 | ||
873 | static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
874 | { | |
875 | return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]); | |
876 | } | |
877 | ||
9cbcc5e3 BZ |
878 | static const struct pci_device_id siimage_pci_tbl[] = { |
879 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 }, | |
1da177e4 | 880 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
9cbcc5e3 BZ |
881 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 }, |
882 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 2 }, | |
1da177e4 LT |
883 | #endif |
884 | { 0, }, | |
885 | }; | |
886 | MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); | |
887 | ||
888 | static struct pci_driver driver = { | |
889 | .name = "SiI_IDE", | |
890 | .id_table = siimage_pci_tbl, | |
891 | .probe = siimage_init_one, | |
892 | }; | |
893 | ||
82ab1eec | 894 | static int __init siimage_ide_init(void) |
1da177e4 LT |
895 | { |
896 | return ide_pci_register_driver(&driver); | |
897 | } | |
898 | ||
899 | module_init(siimage_ide_init); | |
900 | ||
901 | MODULE_AUTHOR("Andre Hedrick, Alan Cox"); | |
902 | MODULE_DESCRIPTION("PCI driver module for SiI IDE"); | |
903 | MODULE_LICENSE("GPL"); |