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ide: make ide_hwif_t.ide_dma_{host_off,off_quietly} void (v2)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / sgiioc4.c
CommitLineData
1da177e4 1/*
0271fc2d 2 * Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
1da177e4
LT		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
11 *
12 * You should have received a copy of the GNU General Public
13 * License along with this program; if not, write the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
15 *
1da177e4
LT		 16 * For further information regarding this notice, see:
17 *
18 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
19 */
20
21#include <linux/module.h>
22#include <linux/types.h>
23#include <linux/pci.h>
24#include <linux/delay.h>
25#include <linux/hdreg.h>
26#include <linux/init.h>
27#include <linux/kernel.h>
28#include <linux/timer.h>
29#include <linux/mm.h>
30#include <linux/ioport.h>
31#include <linux/blkdev.h>
22329b51 32#include <linux/ioc4.h>
1da177e4
LT		 33#include <asm/io.h>
34
35#include <linux/ide.h>
36
37/* IOC4 Specific Definitions */
38#define IOC4_CMD_OFFSET 0x100
39#define IOC4_CTRL_OFFSET 0x120
40#define IOC4_DMA_OFFSET 0x140
41#define IOC4_INTR_OFFSET 0x0
42
43#define IOC4_TIMING 0x00
44#define IOC4_DMA_PTR_L 0x01
45#define IOC4_DMA_PTR_H 0x02
46#define IOC4_DMA_ADDR_L 0x03
47#define IOC4_DMA_ADDR_H 0x04
48#define IOC4_BC_DEV 0x05
49#define IOC4_BC_MEM 0x06
50#define IOC4_DMA_CTRL 0x07
51#define IOC4_DMA_END_ADDR 0x08
52
53/* Bits in the IOC4 Control/Status Register */
54#define IOC4_S_DMA_START 0x01
55#define IOC4_S_DMA_STOP 0x02
56#define IOC4_S_DMA_DIR 0x04
57#define IOC4_S_DMA_ACTIVE 0x08
58#define IOC4_S_DMA_ERROR 0x10
59#define IOC4_ATA_MEMERR 0x02
60
61/* Read/Write Directions */
62#define IOC4_DMA_WRITE 0x04
63#define IOC4_DMA_READ 0x00
64
65/* Interrupt Register Offsets */
66#define IOC4_INTR_REG 0x03
67#define IOC4_INTR_SET 0x05
68#define IOC4_INTR_CLEAR 0x07
69
70#define IOC4_IDE_CACHELINE_SIZE 128
71#define IOC4_CMD_CTL_BLK_SIZE 0x20
72#define IOC4_SUPPORTED_FIRMWARE_REV 46
73
74typedef struct {
75 u32 timing_reg0;
76 u32 timing_reg1;
77 u32 low_mem_ptr;
78 u32 high_mem_ptr;
79 u32 low_mem_addr;
80 u32 high_mem_addr;
81 u32 dev_byte_count;
82 u32 mem_byte_count;
83 u32 status;
84} ioc4_dma_regs_t;
85
86/* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
87/* IOC4 has only 1 IDE channel */
88#define IOC4_PRD_BYTES 16
89#define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
90
91
92static void
93sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
94 unsigned long ctrl_port, unsigned long irq_port)
95{
96 unsigned long reg = data_port;
97 int i;
98
99 /* Registers are word (32 bit) aligned */
100 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
101 hw->io_ports[i] = reg + i * 4;
102
103 if (ctrl_port)
104 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
105
106 if (irq_port)
107 hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
108}
109
110static void
111sgiioc4_maskproc(ide_drive_t * drive, int mask)
112{
0ecdca26
BZ		 113 writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
114 (void __iomem *)IDE_CONTROL_REG);
1da177e4
LT		 115}
116
117
118static int
119sgiioc4_checkirq(ide_hwif_t * hwif)
120{
0ecdca26
BZ		 121 unsigned long intr_addr =
122 hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4;
1da177e4 123
0ecdca26 124 if ((u8)readl((void __iomem *)intr_addr) & 0x03)
1da177e4
LT		 125 return 1;
126
127 return 0;
128}
129
0ecdca26 130static u8 sgiioc4_INB(unsigned long);
1da177e4
LT		 131
132static int
133sgiioc4_clearirq(ide_drive_t * drive)
134{
135 u32 intr_reg;
136 ide_hwif_t *hwif = HWIF(drive);
137 unsigned long other_ir =
138 hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
139
140 /* Code to check for PCI error conditions */
0ecdca26 141 intr_reg = readl((void __iomem *)other_ir);
1da177e4
LT		 142 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
143 /*
0ecdca26 144 * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect
1da177e4
LT		 145 * of clearing the interrupt. The first read should clear it
146 * if it is set. The second read should return a "clear" status
147 * if it got cleared. If not, then spin for a bit trying to
148 * clear it.
149 */
0ecdca26 150 u8 stat = sgiioc4_INB(IDE_STATUS_REG);
1da177e4 151 int count = 0;
0ecdca26 152 stat = sgiioc4_INB(IDE_STATUS_REG);
1da177e4
LT		 153 while ((stat & 0x80) && (count++ < 100)) {
154 udelay(1);
0ecdca26 155 stat = sgiioc4_INB(IDE_STATUS_REG);
1da177e4
LT		 156 }
157
158 if (intr_reg & 0x02) {
159 /* Error when transferring DMA data on PCI bus */
160 u32 pci_err_addr_low, pci_err_addr_high,
161 pci_stat_cmd_reg;
162
163 pci_err_addr_low =
0ecdca26 164 readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]);
1da177e4 165 pci_err_addr_high =
0ecdca26 166 readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4));
1da177e4
LT		 167 pci_read_config_dword(hwif->pci_dev, PCI_COMMAND,
168 &pci_stat_cmd_reg);
169 printk(KERN_ERR
170 "%s(%s) : PCI Bus Error when doing DMA:"
171 " status-cmd reg is 0x%x\n",
172 __FUNCTION__, drive->name, pci_stat_cmd_reg);
173 printk(KERN_ERR
174 "%s(%s) : PCI Error Address is 0x%x%x\n",
175 __FUNCTION__, drive->name,
176 pci_err_addr_high, pci_err_addr_low);
177 /* Clear the PCI Error indicator */
178 pci_write_config_dword(hwif->pci_dev, PCI_COMMAND,
179 0x00000146);
180 }
181
182 /* Clear the Interrupt, Error bits on the IOC4 */
0ecdca26 183 writel(0x03, (void __iomem *)other_ir);
1da177e4 184
0ecdca26 185 intr_reg = readl((void __iomem *)other_ir);
1da177e4
LT		 186 }
187
188 return intr_reg & 3;
189}
190
191static void sgiioc4_ide_dma_start(ide_drive_t * drive)
192{
193 ide_hwif_t *hwif = HWIF(drive);
0ecdca26
BZ		 194 unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
195 unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
1da177e4
LT		 196 unsigned int temp_reg = reg | IOC4_S_DMA_START;
197
0ecdca26 198 writel(temp_reg, (void __iomem *)ioc4_dma_addr);
1da177e4
LT		 199}
200
201static u32
202sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
203{
0ecdca26 204 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
1da177e4
LT		 205 u32 ioc4_dma;
206 int count;
207
208 count = 0;
0ecdca26 209 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
1da177e4
LT		 210 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
211 udelay(1);
0ecdca26 212 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
1da177e4
LT		 213 }
214 return ioc4_dma;
215}
216
217/* Stops the IOC4 DMA Engine */
218static int
219sgiioc4_ide_dma_end(ide_drive_t * drive)
220{
221 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
222 ide_hwif_t *hwif = HWIF(drive);
0ecdca26 223 unsigned long dma_base = hwif->dma_base;
1da177e4 224 int dma_stat = 0;
3f63c5e8 225 unsigned long *ending_dma = ide_get_hwifdata(hwif);
1da177e4 226
0ecdca26 227 writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
1da177e4
LT		 228
229 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
230
231 if (ioc4_dma & IOC4_S_DMA_STOP) {
232 printk(KERN_ERR
233 "%s(%s): IOC4 DMA STOP bit is still 1 :"
234 "ioc4_dma_reg 0x%x\n",
235 __FUNCTION__, drive->name, ioc4_dma);
236 dma_stat = 1;
237 }
238
239 /*
240 * The IOC4 will DMA 1's to the ending dma area to indicate that
241 * previous data DMA is complete. This is necessary because of relaxed
242 * ordering between register reads and DMA writes on the Altix.
243 */
244 while ((cnt++ < 200) && (!valid)) {
245 for (num = 0; num < 16; num++) {
246 if (ending_dma[num]) {
247 valid = 1;
248 break;
249 }
250 }
251 udelay(1);
252 }
253 if (!valid) {
254 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__,
255 drive->name);
256 dma_stat = 1;
257 }
258
0ecdca26
BZ		 259 bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
260 bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
1da177e4
LT		 261
262 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
263 if (bc_dev > bc_mem + 8) {
264 printk(KERN_ERR
265 "%s(%s): WARNING!! byte_count_dev %d "
266 "!= byte_count_mem %d\n",
267 __FUNCTION__, drive->name, bc_dev, bc_mem);
268 }
269 }
270
271 drive->waiting_for_dma = 0;
272 ide_destroy_dmatable(drive);
273
274 return dma_stat;
275}
276
1da177e4
LT		 277static int
278sgiioc4_ide_dma_on(ide_drive_t * drive)
279{
280 drive->using_dma = 1;
281
282 return HWIF(drive)->ide_dma_host_on(drive);
283}
284
7469aaf6 285static void sgiioc4_dma_off_quietly(ide_drive_t *drive)
1da177e4
LT		 286{
287 drive->using_dma = 0;
288
7469aaf6 289 drive->hwif->dma_host_off(drive);
1da177e4
LT		 290}
291
9ef5791e
BZ		 292static int sgiioc4_ide_dma_check(ide_drive_t *drive)
293{
294 /* FIXME: check for available DMA modes */
295 if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0) {
296 printk(KERN_WARNING "%s: couldn't set MWDMA2 mode, "
297 "using PIO instead\n", drive->name);
3608b5d7 298 return -1;
9ef5791e 299 } else
3608b5d7 300 return 0;
9ef5791e
BZ		 301}
302
1da177e4
LT		 303/* returns 1 if dma irq issued, 0 otherwise */
304static int
305sgiioc4_ide_dma_test_irq(ide_drive_t * drive)
306{
307 return sgiioc4_checkirq(HWIF(drive));
308}
309
310static int
311sgiioc4_ide_dma_host_on(ide_drive_t * drive)
312{
313 if (drive->using_dma)
314 return 0;
315
316 return 1;
317}
318
7469aaf6 319static void sgiioc4_dma_host_off(ide_drive_t * drive)
1da177e4
LT		 320{
321 sgiioc4_clearirq(drive);
1da177e4
LT		 322}
323
324static int
325sgiioc4_ide_dma_lostirq(ide_drive_t * drive)
326{
327 HWIF(drive)->resetproc(drive);
328
329 return __ide_dma_lostirq(drive);
330}
331
332static void
333sgiioc4_resetproc(ide_drive_t * drive)
334{
335 sgiioc4_ide_dma_end(drive);
336 sgiioc4_clearirq(drive);
337}
338
339static u8
340sgiioc4_INB(unsigned long port)
341{
a835fa79 342 u8 reg = (u8) readb((void __iomem *) port);
1da177e4
LT		 343
344 if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */
345 if (reg & 0x51) { /* Not busy...check for interrupt */
346 unsigned long other_ir = port - 0x110;
a835fa79 347 unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
1da177e4
LT		 348
349 /* Clear the Interrupt, Error bits on the IOC4 */
350 if (intr_reg & 0x03) {
a835fa79
JH		 351 writel(0x03, (void __iomem *) other_ir);
352 intr_reg = (u32) readl((void __iomem *) other_ir);
1da177e4
LT		 353 }
354 }
355 }
356
357 return reg;
358}
359
360/* Creates a dma map for the scatter-gather list entries */
361static void __devinit
362ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base)
363{
1678df37 364 void __iomem *virt_dma_base;
1da177e4 365 int num_ports = sizeof (ioc4_dma_regs_t);
3f63c5e8 366 void *pad;
1da177e4
LT		 367
368 printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
369 dma_base, dma_base + num_ports - 1);
370
1678df37 371 if (!request_mem_region(dma_base, num_ports, hwif->name)) {
1da177e4
LT		 372 printk(KERN_ERR
373 "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
374 "ALREADY in use\n",
375 __FUNCTION__, hwif->name, (void *) dma_base,
376 (void *) dma_base + num_ports - 1);
377 goto dma_alloc_failure;
378 }
379
1678df37
JK		 380 virt_dma_base = ioremap(dma_base, num_ports);
381 if (virt_dma_base == NULL) {
382 printk(KERN_ERR
383 "%s(%s) -- ERROR, Unable to map addresses 0x%lx to 0x%lx\n",
384 __FUNCTION__, hwif->name, dma_base, dma_base + num_ports - 1);
385 goto dma_remap_failure;
386 }
387 hwif->dma_base = (unsigned long) virt_dma_base;
388
1da177e4
LT		 389 hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
390 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
391 &hwif->dmatable_dma);
392
393 if (!hwif->dmatable_cpu)
1678df37 394 goto dma_pci_alloc_failure;
1da177e4
LT		 395
396 hwif->sg_max_nents = IOC4_PRD_ENTRIES;
397
3f63c5e8
SS		 398 pad = pci_alloc_consistent(hwif->pci_dev, IOC4_IDE_CACHELINE_SIZE,
399 (dma_addr_t *) &(hwif->dma_status));
1da177e4 400
3f63c5e8
SS		 401 if (pad) {
402 ide_set_hwifdata(hwif, pad);
403 return;
404 }
1da177e4 405
1da177e4
LT		 406 pci_free_consistent(hwif->pci_dev,
407 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
408 hwif->dmatable_cpu, hwif->dmatable_dma);
409 printk(KERN_INFO
410 "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
411 __FUNCTION__, hwif->name);
412 printk(KERN_INFO
413 "Changing from DMA to PIO mode for Drive %s\n", hwif->name);
414
1678df37
JK		 415dma_pci_alloc_failure:
416 iounmap(virt_dma_base);
417
418dma_remap_failure:
419 release_mem_region(dma_base, num_ports);
420
1da177e4
LT		 421dma_alloc_failure:
422 /* Disable DMA because we couldnot allocate any DMA maps */
423 hwif->autodma = 0;
424 hwif->atapi_dma = 0;
425}
426
427/* Initializes the IOC4 DMA Engine */
428static void
429sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
430{
431 u32 ioc4_dma;
432 ide_hwif_t *hwif = HWIF(drive);
0ecdca26
BZ		 433 unsigned long dma_base = hwif->dma_base;
434 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
1da177e4
LT		 435 u32 dma_addr, ending_dma_addr;
436
0ecdca26 437 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
1da177e4
LT		 438
439 if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
440 printk(KERN_WARNING
441 "%s(%s):Warning!! DMA from previous transfer was still active\n",
442 __FUNCTION__, drive->name);
0ecdca26 443 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
1da177e4
LT		 444 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
445
446 if (ioc4_dma & IOC4_S_DMA_STOP)
447 printk(KERN_ERR
448 "%s(%s) : IOC4 Dma STOP bit is still 1\n",
449 __FUNCTION__, drive->name);
450 }
451
0ecdca26 452 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
1da177e4
LT		 453 if (ioc4_dma & IOC4_S_DMA_ERROR) {
454 printk(KERN_WARNING
455 "%s(%s) : Warning!! - DMA Error during Previous"
456 " transfer | status 0x%x\n",
457 __FUNCTION__, drive->name, ioc4_dma);
0ecdca26 458 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
1da177e4
LT		 459 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
460
461 if (ioc4_dma & IOC4_S_DMA_STOP)
462 printk(KERN_ERR
463 "%s(%s) : IOC4 DMA STOP bit is still 1\n",
464 __FUNCTION__, drive->name);
465 }
466
467 /* Address of the Scatter Gather List */
468 dma_addr = cpu_to_le32(hwif->dmatable_dma);
0ecdca26 469 writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
1da177e4
LT		 470
471 /* Address of the Ending DMA */
3f63c5e8 472 memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
1da177e4 473 ending_dma_addr = cpu_to_le32(hwif->dma_status);
0ecdca26 474 writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
1da177e4 475
0ecdca26 476 writel(dma_direction, (void __iomem *)ioc4_dma_addr);
1da177e4
LT		 477 drive->waiting_for_dma = 1;
478}
479
480/* IOC4 Scatter Gather list Format */
481/* 128 Bit entries to support 64 bit addresses in the future */
482/* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
483/* --------------------------------------------------------------------- */
484/* | Upper 32 bits - Zero | Lower 32 bits- address | */
485/* --------------------------------------------------------------------- */
486/* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
487/* --------------------------------------------------------------------- */
488/* Creates the scatter gather list, DMA Table */
489static unsigned int
490sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
491{
492 ide_hwif_t *hwif = HWIF(drive);
493 unsigned int *table = hwif->dmatable_cpu;
494 unsigned int count = 0, i = 1;
495 struct scatterlist *sg;
496
497 hwif->sg_nents = i = ide_build_sglist(drive, rq);
498
499 if (!i)
500 return 0; /* sglist of length Zero */
501
502 sg = hwif->sg_table;
503 while (i && sg_dma_len(sg)) {
504 dma_addr_t cur_addr;
505 int cur_len;
506 cur_addr = sg_dma_address(sg);
507 cur_len = sg_dma_len(sg);
508
509 while (cur_len) {
510 if (count++ >= IOC4_PRD_ENTRIES) {
511 printk(KERN_WARNING
512 "%s: DMA table too small\n",
513 drive->name);
514 goto use_pio_instead;
515 } else {
0271fc2d 516 u32 bcount =
1da177e4
LT		 517 0x10000 - (cur_addr & 0xffff);
518
519 if (bcount > cur_len)
520 bcount = cur_len;
521
522 /* put the addr, length in
523 * the IOC4 dma-table format */
524 *table = 0x0;
525 table++;
526 *table = cpu_to_be32(cur_addr);
527 table++;
528 *table = 0x0;
529 table++;
530
0271fc2d 531 *table = cpu_to_be32(bcount);
1da177e4
LT		 532 table++;
533
534 cur_addr += bcount;
535 cur_len -= bcount;
536 }
537 }
538
539 sg++;
540 i--;
541 }
542
543 if (count) {
544 table--;
545 *table |= cpu_to_be32(0x80000000);
546 return count;
547 }
548
549use_pio_instead:
550 pci_unmap_sg(hwif->pci_dev, hwif->sg_table, hwif->sg_nents,
551 hwif->sg_dma_direction);
552
553 return 0; /* revert to PIO for this request */
554}
555
556static int sgiioc4_ide_dma_setup(ide_drive_t *drive)
557{
558 struct request *rq = HWGROUP(drive)->rq;
559 unsigned int count = 0;
560 int ddir;
561
562 if (rq_data_dir(rq))
563 ddir = PCI_DMA_TODEVICE;
564 else
565 ddir = PCI_DMA_FROMDEVICE;
566
567 if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
568 /* try PIO instead of DMA */
569 ide_map_sg(drive, rq);
570 return 1;
571 }
572
573 if (rq_data_dir(rq))
574 /* Writes TO the IOC4 FROM Main Memory */
575 ddir = IOC4_DMA_READ;
576 else
577 /* Writes FROM the IOC4 TO Main Memory */
578 ddir = IOC4_DMA_WRITE;
579
580 sgiioc4_configure_for_dma(ddir, drive);
581
582 return 0;
583}
584
585static void __devinit
586ide_init_sgiioc4(ide_hwif_t * hwif)
587{
2ad1e558 588 hwif->mmio = 1;
1da177e4
LT		 589 hwif->autodma = 1;
590 hwif->atapi_dma = 1;
591 hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
592 hwif->mwdma_mask = 0x2; /* Multimode-2 DMA */
593 hwif->swdma_mask = 0x2;
594 hwif->tuneproc = NULL; /* Sets timing for PIO mode */
595 hwif->speedproc = NULL; /* Sets timing for DMA &/or PIO modes */
596 hwif->selectproc = NULL;/* Use the default routine to select drive */
597 hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */
598 hwif->pre_reset = NULL; /* No HBA specific pre_set needed */
599 hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine,
600 clear interrupts */
601 hwif->intrproc = NULL; /* Enable or Disable interrupt from drive */
602 hwif->maskproc = &sgiioc4_maskproc; /* Mask on/off NIEN register */
603 hwif->quirkproc = NULL;
604 hwif->busproc = NULL;
605
606 hwif->dma_setup = &sgiioc4_ide_dma_setup;
607 hwif->dma_start = &sgiioc4_ide_dma_start;
608 hwif->ide_dma_end = &sgiioc4_ide_dma_end;
609 hwif->ide_dma_check = &sgiioc4_ide_dma_check;
610 hwif->ide_dma_on = &sgiioc4_ide_dma_on;
7469aaf6 611 hwif->dma_off_quietly = &sgiioc4_dma_off_quietly;
1da177e4
LT		 612 hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq;
613 hwif->ide_dma_host_on = &sgiioc4_ide_dma_host_on;
7469aaf6 614 hwif->dma_host_off = &sgiioc4_dma_host_off;
1da177e4
LT		 615 hwif->ide_dma_lostirq = &sgiioc4_ide_dma_lostirq;
616 hwif->ide_dma_timeout = &__ide_dma_timeout;
a835fa79 617
1da177e4
LT		 618 hwif->INB = &sgiioc4_INB;
619}
620
621static int __devinit
622sgiioc4_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t * d)
623{
1678df37
JK		 624 unsigned long cmd_base, dma_base, irqport;
625 unsigned long bar0, cmd_phys_base, ctl;
626 void __iomem *virt_base;
1da177e4
LT		 627 ide_hwif_t *hwif;
628 int h;
629
deb5e5c0
JH		 630 /*
631 * Find an empty HWIF; if none available, return -ENOMEM.
632 */
1da177e4
LT		 633 for (h = 0; h < MAX_HWIFS; ++h) {
634 hwif = &ide_hwifs[h];
1da177e4
LT		 635 if (hwif->chipset == ide_unknown)
636 break;
637 }
deb5e5c0
JH		 638 if (h == MAX_HWIFS) {
639 printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", d->name);
640 return -ENOMEM;
641 }
1da177e4
LT		 642
643 /* Get the CmdBlk and CtrlBlk Base Registers */
1678df37
JK		 644 bar0 = pci_resource_start(dev, 0);
645 virt_base = ioremap(bar0, pci_resource_len(dev, 0));
646 if (virt_base == NULL) {
647 printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
648 d->name, bar0);
649 return -ENOMEM;
650 }
651 cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
652 ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
653 irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
1da177e4
LT		 654 dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
655
1678df37
JK		 656 cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
657 if (!request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
658 hwif->name)) {
1da177e4 659 printk(KERN_ERR
1678df37 660 "%s : %s -- ERROR, Addresses "
1da177e4 661 "0x%p to 0x%p ALREADY in use\n",
1678df37
JK		 662 __FUNCTION__, hwif->name, (void *) cmd_phys_base,
663 (void *) cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
1da177e4
LT		 664 return -ENOMEM;
665 }
666
1678df37 667 if (hwif->io_ports[IDE_DATA_OFFSET] != cmd_base) {
1da177e4 668 /* Initialize the IO registers */
1678df37 669 sgiioc4_init_hwif_ports(&hwif->hw, cmd_base, ctl, irqport);
1da177e4
LT		 670 memcpy(hwif->io_ports, hwif->hw.io_ports,
671 sizeof (hwif->io_ports));
672 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
673 }
674
675 hwif->irq = dev->irq;
676 hwif->chipset = ide_pci;
677 hwif->pci_dev = dev;
678 hwif->channel = 0; /* Single Channel chip */
679 hwif->cds = (struct ide_pci_device_s *) d;
680 hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */
681
1678df37
JK		 682 /* The IOC4 uses MMIO rather than Port IO. */
683 default_hwif_mmiops(hwif);
684
1da177e4 685 /* Initializing chipset IRQ Registers */
0ecdca26 686 writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
1da177e4
LT		 687
688 ide_init_sgiioc4(hwif);
689
690 if (dma_base)
691 ide_dma_sgiioc4(hwif, dma_base);
692 else
693 printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
694 hwif->name, d->name);
695
696 if (probe_hwif_init(hwif))
697 return -EIO;
698
699 /* Create /proc/ide entries */
0271fc2d 700 create_proc_ide_interfaces();
1da177e4
LT		 701
702 return 0;
703}
704
705static unsigned int __devinit
706pci_init_sgiioc4(struct pci_dev *dev, ide_pci_device_t * d)
707{
708 unsigned int class_rev;
709 int ret;
710
711 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
712 class_rev &= 0xff;
713 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
714 d->name, pci_name(dev), class_rev);
715 if (class_rev < IOC4_SUPPORTED_FIRMWARE_REV) {
716 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
717 "firmware is obsolete - please upgrade to revision"
718 "46 or higher\n", d->name, pci_name(dev));
719 ret = -EAGAIN;
720 goto out;
721 }
722 ret = sgiioc4_ide_setup_pci_device(dev, d);
723out:
724 return ret;
725}
726
7b77d864 727static ide_pci_device_t sgiioc4_chipset __devinitdata = {
1da177e4
LT		 728 /* Channel 0 */
729 .name = "SGIIOC4",
730 .init_hwif = ide_init_sgiioc4,
731 .init_dma = ide_dma_sgiioc4,
732 .channels = 1,
733 .autodma = AUTODMA,
734 /* SGI IOC4 doesn't have enablebits. */
735 .bootable = ON_BOARD,
1da177e4
LT		 736};
737
738int
22329b51 739ioc4_ide_attach_one(struct ioc4_driver_data *idd)
1da177e4 740{
f5befceb
BC		 741 /* PCI-RT does not bring out IDE connection.
742 * Do not attach to this particular IOC4.
743 */
744 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
745 return 0;
746
7b77d864 747 return pci_init_sgiioc4(idd->idd_pdev, &sgiioc4_chipset);
1da177e4
LT		 748}
749
22329b51
BC		 750static struct ioc4_submodule ioc4_ide_submodule = {
751 .is_name = "IOC4_ide",
752 .is_owner = THIS_MODULE,
753 .is_probe = ioc4_ide_attach_one,
754/* .is_remove = ioc4_ide_remove_one, */
755};
756
82ab1eec 757static int __init ioc4_ide_init(void)
22329b51
BC		 758{
759 return ioc4_register_submodule(&ioc4_ide_submodule);
760}
761
59f14800 762late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
1da177e4 763
a835fa79 764MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
1da177e4
LT		 765MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
766MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)