Commit | Line | Data |
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1da177e4 | 1 | /* |
0271fc2d | 2 | * Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved. |
1da177e4 LT |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of version 2 of the GNU General Public License | |
6 | * as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it would be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public | |
13 | * License along with this program; if not, write the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
15 | * | |
1da177e4 LT |
16 | * For further information regarding this notice, see: |
17 | * | |
18 | * http://oss.sgi.com/projects/GenInfo/NoticeExplan | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/hdreg.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/kernel.h> | |
1da177e4 LT |
28 | #include <linux/ioport.h> |
29 | #include <linux/blkdev.h> | |
55c16a70 | 30 | #include <linux/scatterlist.h> |
22329b51 | 31 | #include <linux/ioc4.h> |
1da177e4 LT |
32 | #include <asm/io.h> |
33 | ||
34 | #include <linux/ide.h> | |
35 | ||
ca1997c1 BZ |
36 | #define DRV_NAME "SGIIOC4" |
37 | ||
1da177e4 LT |
38 | /* IOC4 Specific Definitions */ |
39 | #define IOC4_CMD_OFFSET 0x100 | |
40 | #define IOC4_CTRL_OFFSET 0x120 | |
41 | #define IOC4_DMA_OFFSET 0x140 | |
42 | #define IOC4_INTR_OFFSET 0x0 | |
43 | ||
44 | #define IOC4_TIMING 0x00 | |
45 | #define IOC4_DMA_PTR_L 0x01 | |
46 | #define IOC4_DMA_PTR_H 0x02 | |
47 | #define IOC4_DMA_ADDR_L 0x03 | |
48 | #define IOC4_DMA_ADDR_H 0x04 | |
49 | #define IOC4_BC_DEV 0x05 | |
50 | #define IOC4_BC_MEM 0x06 | |
51 | #define IOC4_DMA_CTRL 0x07 | |
52 | #define IOC4_DMA_END_ADDR 0x08 | |
53 | ||
54 | /* Bits in the IOC4 Control/Status Register */ | |
55 | #define IOC4_S_DMA_START 0x01 | |
56 | #define IOC4_S_DMA_STOP 0x02 | |
57 | #define IOC4_S_DMA_DIR 0x04 | |
58 | #define IOC4_S_DMA_ACTIVE 0x08 | |
59 | #define IOC4_S_DMA_ERROR 0x10 | |
60 | #define IOC4_ATA_MEMERR 0x02 | |
61 | ||
62 | /* Read/Write Directions */ | |
63 | #define IOC4_DMA_WRITE 0x04 | |
64 | #define IOC4_DMA_READ 0x00 | |
65 | ||
66 | /* Interrupt Register Offsets */ | |
67 | #define IOC4_INTR_REG 0x03 | |
68 | #define IOC4_INTR_SET 0x05 | |
69 | #define IOC4_INTR_CLEAR 0x07 | |
70 | ||
71 | #define IOC4_IDE_CACHELINE_SIZE 128 | |
72 | #define IOC4_CMD_CTL_BLK_SIZE 0x20 | |
73 | #define IOC4_SUPPORTED_FIRMWARE_REV 46 | |
74 | ||
75 | typedef struct { | |
76 | u32 timing_reg0; | |
77 | u32 timing_reg1; | |
78 | u32 low_mem_ptr; | |
79 | u32 high_mem_ptr; | |
80 | u32 low_mem_addr; | |
81 | u32 high_mem_addr; | |
82 | u32 dev_byte_count; | |
83 | u32 mem_byte_count; | |
84 | u32 status; | |
85 | } ioc4_dma_regs_t; | |
86 | ||
87 | /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */ | |
88 | /* IOC4 has only 1 IDE channel */ | |
89 | #define IOC4_PRD_BYTES 16 | |
90 | #define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES)) | |
91 | ||
92 | ||
93 | static void | |
94 | sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port, | |
95 | unsigned long ctrl_port, unsigned long irq_port) | |
96 | { | |
97 | unsigned long reg = data_port; | |
98 | int i; | |
99 | ||
100 | /* Registers are word (32 bit) aligned */ | |
101 | for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) | |
102 | hw->io_ports[i] = reg + i * 4; | |
103 | ||
104 | if (ctrl_port) | |
105 | hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; | |
106 | ||
107 | if (irq_port) | |
108 | hw->io_ports[IDE_IRQ_OFFSET] = irq_port; | |
109 | } | |
110 | ||
111 | static void | |
112 | sgiioc4_maskproc(ide_drive_t * drive, int mask) | |
113 | { | |
0ecdca26 BZ |
114 | writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2), |
115 | (void __iomem *)IDE_CONTROL_REG); | |
1da177e4 LT |
116 | } |
117 | ||
118 | ||
119 | static int | |
120 | sgiioc4_checkirq(ide_hwif_t * hwif) | |
121 | { | |
0ecdca26 BZ |
122 | unsigned long intr_addr = |
123 | hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4; | |
1da177e4 | 124 | |
0ecdca26 | 125 | if ((u8)readl((void __iomem *)intr_addr) & 0x03) |
1da177e4 LT |
126 | return 1; |
127 | ||
128 | return 0; | |
129 | } | |
130 | ||
0ecdca26 | 131 | static u8 sgiioc4_INB(unsigned long); |
1da177e4 LT |
132 | |
133 | static int | |
134 | sgiioc4_clearirq(ide_drive_t * drive) | |
135 | { | |
136 | u32 intr_reg; | |
137 | ide_hwif_t *hwif = HWIF(drive); | |
138 | unsigned long other_ir = | |
139 | hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2); | |
140 | ||
141 | /* Code to check for PCI error conditions */ | |
0ecdca26 | 142 | intr_reg = readl((void __iomem *)other_ir); |
1da177e4 LT |
143 | if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */ |
144 | /* | |
0ecdca26 | 145 | * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect |
1da177e4 LT |
146 | * of clearing the interrupt. The first read should clear it |
147 | * if it is set. The second read should return a "clear" status | |
148 | * if it got cleared. If not, then spin for a bit trying to | |
149 | * clear it. | |
150 | */ | |
0ecdca26 | 151 | u8 stat = sgiioc4_INB(IDE_STATUS_REG); |
1da177e4 | 152 | int count = 0; |
0ecdca26 | 153 | stat = sgiioc4_INB(IDE_STATUS_REG); |
1da177e4 LT |
154 | while ((stat & 0x80) && (count++ < 100)) { |
155 | udelay(1); | |
0ecdca26 | 156 | stat = sgiioc4_INB(IDE_STATUS_REG); |
1da177e4 LT |
157 | } |
158 | ||
159 | if (intr_reg & 0x02) { | |
36501650 | 160 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 LT |
161 | /* Error when transferring DMA data on PCI bus */ |
162 | u32 pci_err_addr_low, pci_err_addr_high, | |
163 | pci_stat_cmd_reg; | |
164 | ||
165 | pci_err_addr_low = | |
0ecdca26 | 166 | readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]); |
1da177e4 | 167 | pci_err_addr_high = |
0ecdca26 | 168 | readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4)); |
36501650 | 169 | pci_read_config_dword(dev, PCI_COMMAND, |
1da177e4 LT |
170 | &pci_stat_cmd_reg); |
171 | printk(KERN_ERR | |
172 | "%s(%s) : PCI Bus Error when doing DMA:" | |
173 | " status-cmd reg is 0x%x\n", | |
174 | __FUNCTION__, drive->name, pci_stat_cmd_reg); | |
175 | printk(KERN_ERR | |
176 | "%s(%s) : PCI Error Address is 0x%x%x\n", | |
177 | __FUNCTION__, drive->name, | |
178 | pci_err_addr_high, pci_err_addr_low); | |
179 | /* Clear the PCI Error indicator */ | |
36501650 | 180 | pci_write_config_dword(dev, PCI_COMMAND, 0x00000146); |
1da177e4 LT |
181 | } |
182 | ||
183 | /* Clear the Interrupt, Error bits on the IOC4 */ | |
0ecdca26 | 184 | writel(0x03, (void __iomem *)other_ir); |
1da177e4 | 185 | |
0ecdca26 | 186 | intr_reg = readl((void __iomem *)other_ir); |
1da177e4 LT |
187 | } |
188 | ||
189 | return intr_reg & 3; | |
190 | } | |
191 | ||
192 | static void sgiioc4_ide_dma_start(ide_drive_t * drive) | |
193 | { | |
194 | ide_hwif_t *hwif = HWIF(drive); | |
0ecdca26 BZ |
195 | unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4; |
196 | unsigned int reg = readl((void __iomem *)ioc4_dma_addr); | |
1da177e4 LT |
197 | unsigned int temp_reg = reg | IOC4_S_DMA_START; |
198 | ||
0ecdca26 | 199 | writel(temp_reg, (void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
200 | } |
201 | ||
202 | static u32 | |
203 | sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base) | |
204 | { | |
0ecdca26 | 205 | unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4; |
1da177e4 LT |
206 | u32 ioc4_dma; |
207 | int count; | |
208 | ||
209 | count = 0; | |
0ecdca26 | 210 | ioc4_dma = readl((void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
211 | while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) { |
212 | udelay(1); | |
0ecdca26 | 213 | ioc4_dma = readl((void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
214 | } |
215 | return ioc4_dma; | |
216 | } | |
217 | ||
218 | /* Stops the IOC4 DMA Engine */ | |
219 | static int | |
220 | sgiioc4_ide_dma_end(ide_drive_t * drive) | |
221 | { | |
222 | u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0; | |
223 | ide_hwif_t *hwif = HWIF(drive); | |
0ecdca26 | 224 | unsigned long dma_base = hwif->dma_base; |
1da177e4 | 225 | int dma_stat = 0; |
3f63c5e8 | 226 | unsigned long *ending_dma = ide_get_hwifdata(hwif); |
1da177e4 | 227 | |
0ecdca26 | 228 | writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4)); |
1da177e4 LT |
229 | |
230 | ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); | |
231 | ||
232 | if (ioc4_dma & IOC4_S_DMA_STOP) { | |
233 | printk(KERN_ERR | |
234 | "%s(%s): IOC4 DMA STOP bit is still 1 :" | |
235 | "ioc4_dma_reg 0x%x\n", | |
236 | __FUNCTION__, drive->name, ioc4_dma); | |
237 | dma_stat = 1; | |
238 | } | |
239 | ||
240 | /* | |
241 | * The IOC4 will DMA 1's to the ending dma area to indicate that | |
242 | * previous data DMA is complete. This is necessary because of relaxed | |
243 | * ordering between register reads and DMA writes on the Altix. | |
244 | */ | |
245 | while ((cnt++ < 200) && (!valid)) { | |
246 | for (num = 0; num < 16; num++) { | |
247 | if (ending_dma[num]) { | |
248 | valid = 1; | |
249 | break; | |
250 | } | |
251 | } | |
252 | udelay(1); | |
253 | } | |
254 | if (!valid) { | |
255 | printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__, | |
256 | drive->name); | |
257 | dma_stat = 1; | |
258 | } | |
259 | ||
0ecdca26 BZ |
260 | bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4)); |
261 | bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4)); | |
1da177e4 LT |
262 | |
263 | if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) { | |
264 | if (bc_dev > bc_mem + 8) { | |
265 | printk(KERN_ERR | |
266 | "%s(%s): WARNING!! byte_count_dev %d " | |
267 | "!= byte_count_mem %d\n", | |
268 | __FUNCTION__, drive->name, bc_dev, bc_mem); | |
269 | } | |
270 | } | |
271 | ||
272 | drive->waiting_for_dma = 0; | |
273 | ide_destroy_dmatable(drive); | |
274 | ||
275 | return dma_stat; | |
276 | } | |
277 | ||
88b2b32b | 278 | static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed) |
ca1997c1 | 279 | { |
ca1997c1 BZ |
280 | } |
281 | ||
1da177e4 LT |
282 | /* returns 1 if dma irq issued, 0 otherwise */ |
283 | static int | |
284 | sgiioc4_ide_dma_test_irq(ide_drive_t * drive) | |
285 | { | |
286 | return sgiioc4_checkirq(HWIF(drive)); | |
287 | } | |
288 | ||
15ce926a | 289 | static void sgiioc4_dma_host_set(ide_drive_t *drive, int on) |
1da177e4 | 290 | { |
15ce926a BZ |
291 | if (!on) |
292 | sgiioc4_clearirq(drive); | |
1da177e4 LT |
293 | } |
294 | ||
1da177e4 LT |
295 | static void |
296 | sgiioc4_resetproc(ide_drive_t * drive) | |
297 | { | |
298 | sgiioc4_ide_dma_end(drive); | |
299 | sgiioc4_clearirq(drive); | |
300 | } | |
301 | ||
841d2a9b SS |
302 | static void |
303 | sgiioc4_dma_lost_irq(ide_drive_t * drive) | |
304 | { | |
305 | sgiioc4_resetproc(drive); | |
306 | ||
307 | ide_dma_lost_irq(drive); | |
308 | } | |
309 | ||
1da177e4 LT |
310 | static u8 |
311 | sgiioc4_INB(unsigned long port) | |
312 | { | |
a835fa79 | 313 | u8 reg = (u8) readb((void __iomem *) port); |
1da177e4 LT |
314 | |
315 | if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */ | |
316 | if (reg & 0x51) { /* Not busy...check for interrupt */ | |
317 | unsigned long other_ir = port - 0x110; | |
a835fa79 | 318 | unsigned int intr_reg = (u32) readl((void __iomem *) other_ir); |
1da177e4 LT |
319 | |
320 | /* Clear the Interrupt, Error bits on the IOC4 */ | |
321 | if (intr_reg & 0x03) { | |
a835fa79 JH |
322 | writel(0x03, (void __iomem *) other_ir); |
323 | intr_reg = (u32) readl((void __iomem *) other_ir); | |
1da177e4 LT |
324 | } |
325 | } | |
326 | } | |
327 | ||
328 | return reg; | |
329 | } | |
330 | ||
331 | /* Creates a dma map for the scatter-gather list entries */ | |
ca1997c1 | 332 | static int __devinit |
1da177e4 LT |
333 | ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base) |
334 | { | |
36501650 | 335 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1678df37 | 336 | void __iomem *virt_dma_base; |
1da177e4 | 337 | int num_ports = sizeof (ioc4_dma_regs_t); |
3f63c5e8 | 338 | void *pad; |
1da177e4 LT |
339 | |
340 | printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name, | |
341 | dma_base, dma_base + num_ports - 1); | |
342 | ||
1678df37 | 343 | if (!request_mem_region(dma_base, num_ports, hwif->name)) { |
1da177e4 LT |
344 | printk(KERN_ERR |
345 | "%s(%s) -- ERROR, Addresses 0x%p to 0x%p " | |
346 | "ALREADY in use\n", | |
347 | __FUNCTION__, hwif->name, (void *) dma_base, | |
348 | (void *) dma_base + num_ports - 1); | |
ca1997c1 | 349 | return -1; |
1da177e4 LT |
350 | } |
351 | ||
1678df37 JK |
352 | virt_dma_base = ioremap(dma_base, num_ports); |
353 | if (virt_dma_base == NULL) { | |
354 | printk(KERN_ERR | |
355 | "%s(%s) -- ERROR, Unable to map addresses 0x%lx to 0x%lx\n", | |
356 | __FUNCTION__, hwif->name, dma_base, dma_base + num_ports - 1); | |
357 | goto dma_remap_failure; | |
358 | } | |
359 | hwif->dma_base = (unsigned long) virt_dma_base; | |
360 | ||
36501650 | 361 | hwif->dmatable_cpu = pci_alloc_consistent(dev, |
1da177e4 LT |
362 | IOC4_PRD_ENTRIES * IOC4_PRD_BYTES, |
363 | &hwif->dmatable_dma); | |
364 | ||
365 | if (!hwif->dmatable_cpu) | |
1678df37 | 366 | goto dma_pci_alloc_failure; |
1da177e4 LT |
367 | |
368 | hwif->sg_max_nents = IOC4_PRD_ENTRIES; | |
369 | ||
36501650 | 370 | pad = pci_alloc_consistent(dev, IOC4_IDE_CACHELINE_SIZE, |
3f63c5e8 | 371 | (dma_addr_t *) &(hwif->dma_status)); |
1da177e4 | 372 | |
3f63c5e8 SS |
373 | if (pad) { |
374 | ide_set_hwifdata(hwif, pad); | |
ca1997c1 | 375 | return 0; |
3f63c5e8 | 376 | } |
1da177e4 | 377 | |
36501650 | 378 | pci_free_consistent(dev, IOC4_PRD_ENTRIES * IOC4_PRD_BYTES, |
1da177e4 LT |
379 | hwif->dmatable_cpu, hwif->dmatable_dma); |
380 | printk(KERN_INFO | |
381 | "%s() -- Error! Unable to allocate DMA Maps for drive %s\n", | |
382 | __FUNCTION__, hwif->name); | |
383 | printk(KERN_INFO | |
384 | "Changing from DMA to PIO mode for Drive %s\n", hwif->name); | |
385 | ||
1678df37 JK |
386 | dma_pci_alloc_failure: |
387 | iounmap(virt_dma_base); | |
388 | ||
389 | dma_remap_failure: | |
390 | release_mem_region(dma_base, num_ports); | |
391 | ||
ca1997c1 | 392 | return -1; |
1da177e4 LT |
393 | } |
394 | ||
395 | /* Initializes the IOC4 DMA Engine */ | |
396 | static void | |
397 | sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive) | |
398 | { | |
399 | u32 ioc4_dma; | |
400 | ide_hwif_t *hwif = HWIF(drive); | |
0ecdca26 BZ |
401 | unsigned long dma_base = hwif->dma_base; |
402 | unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4; | |
1da177e4 LT |
403 | u32 dma_addr, ending_dma_addr; |
404 | ||
0ecdca26 | 405 | ioc4_dma = readl((void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
406 | |
407 | if (ioc4_dma & IOC4_S_DMA_ACTIVE) { | |
408 | printk(KERN_WARNING | |
409 | "%s(%s):Warning!! DMA from previous transfer was still active\n", | |
410 | __FUNCTION__, drive->name); | |
0ecdca26 | 411 | writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
412 | ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); |
413 | ||
414 | if (ioc4_dma & IOC4_S_DMA_STOP) | |
415 | printk(KERN_ERR | |
416 | "%s(%s) : IOC4 Dma STOP bit is still 1\n", | |
417 | __FUNCTION__, drive->name); | |
418 | } | |
419 | ||
0ecdca26 | 420 | ioc4_dma = readl((void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
421 | if (ioc4_dma & IOC4_S_DMA_ERROR) { |
422 | printk(KERN_WARNING | |
423 | "%s(%s) : Warning!! - DMA Error during Previous" | |
424 | " transfer | status 0x%x\n", | |
425 | __FUNCTION__, drive->name, ioc4_dma); | |
0ecdca26 | 426 | writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
427 | ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base); |
428 | ||
429 | if (ioc4_dma & IOC4_S_DMA_STOP) | |
430 | printk(KERN_ERR | |
431 | "%s(%s) : IOC4 DMA STOP bit is still 1\n", | |
432 | __FUNCTION__, drive->name); | |
433 | } | |
434 | ||
435 | /* Address of the Scatter Gather List */ | |
436 | dma_addr = cpu_to_le32(hwif->dmatable_dma); | |
0ecdca26 | 437 | writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4)); |
1da177e4 LT |
438 | |
439 | /* Address of the Ending DMA */ | |
3f63c5e8 | 440 | memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE); |
1da177e4 | 441 | ending_dma_addr = cpu_to_le32(hwif->dma_status); |
0ecdca26 | 442 | writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4)); |
1da177e4 | 443 | |
0ecdca26 | 444 | writel(dma_direction, (void __iomem *)ioc4_dma_addr); |
1da177e4 LT |
445 | drive->waiting_for_dma = 1; |
446 | } | |
447 | ||
448 | /* IOC4 Scatter Gather list Format */ | |
449 | /* 128 Bit entries to support 64 bit addresses in the future */ | |
450 | /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */ | |
451 | /* --------------------------------------------------------------------- */ | |
452 | /* | Upper 32 bits - Zero | Lower 32 bits- address | */ | |
453 | /* --------------------------------------------------------------------- */ | |
454 | /* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */ | |
455 | /* --------------------------------------------------------------------- */ | |
456 | /* Creates the scatter gather list, DMA Table */ | |
457 | static unsigned int | |
458 | sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir) | |
459 | { | |
460 | ide_hwif_t *hwif = HWIF(drive); | |
461 | unsigned int *table = hwif->dmatable_cpu; | |
462 | unsigned int count = 0, i = 1; | |
463 | struct scatterlist *sg; | |
464 | ||
465 | hwif->sg_nents = i = ide_build_sglist(drive, rq); | |
466 | ||
467 | if (!i) | |
468 | return 0; /* sglist of length Zero */ | |
469 | ||
470 | sg = hwif->sg_table; | |
471 | while (i && sg_dma_len(sg)) { | |
472 | dma_addr_t cur_addr; | |
473 | int cur_len; | |
474 | cur_addr = sg_dma_address(sg); | |
475 | cur_len = sg_dma_len(sg); | |
476 | ||
477 | while (cur_len) { | |
478 | if (count++ >= IOC4_PRD_ENTRIES) { | |
479 | printk(KERN_WARNING | |
480 | "%s: DMA table too small\n", | |
481 | drive->name); | |
482 | goto use_pio_instead; | |
483 | } else { | |
0271fc2d | 484 | u32 bcount = |
1da177e4 LT |
485 | 0x10000 - (cur_addr & 0xffff); |
486 | ||
487 | if (bcount > cur_len) | |
488 | bcount = cur_len; | |
489 | ||
490 | /* put the addr, length in | |
491 | * the IOC4 dma-table format */ | |
492 | *table = 0x0; | |
493 | table++; | |
494 | *table = cpu_to_be32(cur_addr); | |
495 | table++; | |
496 | *table = 0x0; | |
497 | table++; | |
498 | ||
0271fc2d | 499 | *table = cpu_to_be32(bcount); |
1da177e4 LT |
500 | table++; |
501 | ||
502 | cur_addr += bcount; | |
503 | cur_len -= bcount; | |
504 | } | |
505 | } | |
506 | ||
55c16a70 | 507 | sg = sg_next(sg); |
1da177e4 LT |
508 | i--; |
509 | } | |
510 | ||
511 | if (count) { | |
512 | table--; | |
513 | *table |= cpu_to_be32(0x80000000); | |
514 | return count; | |
515 | } | |
516 | ||
517 | use_pio_instead: | |
f6fb786d | 518 | ide_destroy_dmatable(drive); |
1da177e4 LT |
519 | |
520 | return 0; /* revert to PIO for this request */ | |
521 | } | |
522 | ||
523 | static int sgiioc4_ide_dma_setup(ide_drive_t *drive) | |
524 | { | |
525 | struct request *rq = HWGROUP(drive)->rq; | |
526 | unsigned int count = 0; | |
527 | int ddir; | |
528 | ||
529 | if (rq_data_dir(rq)) | |
530 | ddir = PCI_DMA_TODEVICE; | |
531 | else | |
532 | ddir = PCI_DMA_FROMDEVICE; | |
533 | ||
534 | if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) { | |
535 | /* try PIO instead of DMA */ | |
536 | ide_map_sg(drive, rq); | |
537 | return 1; | |
538 | } | |
539 | ||
540 | if (rq_data_dir(rq)) | |
541 | /* Writes TO the IOC4 FROM Main Memory */ | |
542 | ddir = IOC4_DMA_READ; | |
543 | else | |
544 | /* Writes FROM the IOC4 TO Main Memory */ | |
545 | ddir = IOC4_DMA_WRITE; | |
546 | ||
547 | sgiioc4_configure_for_dma(ddir, drive); | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | static void __devinit | |
553 | ide_init_sgiioc4(ide_hwif_t * hwif) | |
554 | { | |
2ad1e558 | 555 | hwif->mmio = 1; |
26bcb879 | 556 | hwif->set_pio_mode = NULL; /* Sets timing for PIO mode */ |
88b2b32b | 557 | hwif->set_dma_mode = &sgiioc4_set_dma_mode; |
1da177e4 LT |
558 | hwif->selectproc = NULL;/* Use the default routine to select drive */ |
559 | hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */ | |
560 | hwif->pre_reset = NULL; /* No HBA specific pre_set needed */ | |
561 | hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine, | |
562 | clear interrupts */ | |
1da177e4 LT |
563 | hwif->maskproc = &sgiioc4_maskproc; /* Mask on/off NIEN register */ |
564 | hwif->quirkproc = NULL; | |
565 | hwif->busproc = NULL; | |
566 | ||
b9d9e61a BZ |
567 | hwif->INB = &sgiioc4_INB; |
568 | ||
569 | if (hwif->dma_base == 0) | |
570 | return; | |
571 | ||
15ce926a | 572 | hwif->dma_host_set = &sgiioc4_dma_host_set; |
1da177e4 LT |
573 | hwif->dma_setup = &sgiioc4_ide_dma_setup; |
574 | hwif->dma_start = &sgiioc4_ide_dma_start; | |
575 | hwif->ide_dma_end = &sgiioc4_ide_dma_end; | |
1da177e4 | 576 | hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq; |
841d2a9b | 577 | hwif->dma_lost_irq = &sgiioc4_dma_lost_irq; |
c283f5db | 578 | hwif->dma_timeout = &ide_dma_timeout; |
1da177e4 LT |
579 | } |
580 | ||
c413b9b9 BZ |
581 | static const struct ide_port_info sgiioc4_port_info __devinitdata = { |
582 | .chipset = ide_pci, | |
583 | .host_flags = IDE_HFLAG_NO_DMA | /* no SFF-style DMA */ | |
584 | IDE_HFLAG_NO_AUTOTUNE, | |
585 | .mwdma_mask = ATA_MWDMA2_ONLY, | |
586 | }; | |
587 | ||
1da177e4 | 588 | static int __devinit |
ca1997c1 | 589 | sgiioc4_ide_setup_pci_device(struct pci_dev *dev) |
1da177e4 | 590 | { |
1678df37 JK |
591 | unsigned long cmd_base, dma_base, irqport; |
592 | unsigned long bar0, cmd_phys_base, ctl; | |
593 | void __iomem *virt_base; | |
1da177e4 LT |
594 | ide_hwif_t *hwif; |
595 | int h; | |
8447d9d5 | 596 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
8f8e8483 | 597 | hw_regs_t hw; |
c413b9b9 | 598 | struct ide_port_info d = sgiioc4_port_info; |
1da177e4 | 599 | |
deb5e5c0 JH |
600 | /* |
601 | * Find an empty HWIF; if none available, return -ENOMEM. | |
602 | */ | |
1da177e4 LT |
603 | for (h = 0; h < MAX_HWIFS; ++h) { |
604 | hwif = &ide_hwifs[h]; | |
1da177e4 LT |
605 | if (hwif->chipset == ide_unknown) |
606 | break; | |
607 | } | |
deb5e5c0 | 608 | if (h == MAX_HWIFS) { |
ca1997c1 BZ |
609 | printk(KERN_ERR "%s: too many IDE interfaces, no room in table\n", |
610 | DRV_NAME); | |
deb5e5c0 JH |
611 | return -ENOMEM; |
612 | } | |
1da177e4 LT |
613 | |
614 | /* Get the CmdBlk and CtrlBlk Base Registers */ | |
1678df37 JK |
615 | bar0 = pci_resource_start(dev, 0); |
616 | virt_base = ioremap(bar0, pci_resource_len(dev, 0)); | |
617 | if (virt_base == NULL) { | |
618 | printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n", | |
ca1997c1 | 619 | DRV_NAME, bar0); |
1678df37 JK |
620 | return -ENOMEM; |
621 | } | |
622 | cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET; | |
623 | ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET; | |
624 | irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET; | |
1da177e4 LT |
625 | dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET; |
626 | ||
1678df37 JK |
627 | cmd_phys_base = bar0 + IOC4_CMD_OFFSET; |
628 | if (!request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE, | |
629 | hwif->name)) { | |
1da177e4 | 630 | printk(KERN_ERR |
1678df37 | 631 | "%s : %s -- ERROR, Addresses " |
1da177e4 | 632 | "0x%p to 0x%p ALREADY in use\n", |
1678df37 JK |
633 | __FUNCTION__, hwif->name, (void *) cmd_phys_base, |
634 | (void *) cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE); | |
1da177e4 LT |
635 | return -ENOMEM; |
636 | } | |
637 | ||
8f8e8483 BZ |
638 | /* Initialize the IO registers */ |
639 | memset(&hw, 0, sizeof(hw)); | |
640 | sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport); | |
57c802e8 BZ |
641 | hw.irq = dev->irq; |
642 | hw.chipset = ide_pci; | |
643 | hw.dev = &dev->dev; | |
644 | ide_init_port_hw(hwif, &hw); | |
1da177e4 | 645 | |
36501650 | 646 | hwif->dev = &dev->dev; |
1da177e4 | 647 | |
1678df37 JK |
648 | /* The IOC4 uses MMIO rather than Port IO. */ |
649 | default_hwif_mmiops(hwif); | |
650 | ||
1da177e4 | 651 | /* Initializing chipset IRQ Registers */ |
0ecdca26 | 652 | writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4)); |
1da177e4 | 653 | |
c413b9b9 | 654 | if (dma_base == 0 || ide_dma_sgiioc4(hwif, dma_base)) { |
1da177e4 | 655 | printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n", |
ca1997c1 | 656 | hwif->name, DRV_NAME); |
c413b9b9 BZ |
657 | d.mwdma_mask = 0; |
658 | } | |
1da177e4 | 659 | |
b9d9e61a BZ |
660 | ide_init_sgiioc4(hwif); |
661 | ||
8447d9d5 | 662 | idx[0] = hwif->index; |
1da177e4 | 663 | |
c413b9b9 | 664 | if (ide_device_add(idx, &d)) |
8447d9d5 | 665 | return -EIO; |
1da177e4 LT |
666 | |
667 | return 0; | |
668 | } | |
669 | ||
670 | static unsigned int __devinit | |
ca1997c1 | 671 | pci_init_sgiioc4(struct pci_dev *dev) |
1da177e4 | 672 | { |
1da177e4 LT |
673 | int ret; |
674 | ||
1da177e4 | 675 | printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n", |
fc212bb1 BZ |
676 | DRV_NAME, pci_name(dev), dev->revision); |
677 | ||
678 | if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) { | |
1da177e4 | 679 | printk(KERN_ERR "Skipping %s IDE controller in slot %s: " |
ca1997c1 BZ |
680 | "firmware is obsolete - please upgrade to " |
681 | "revision46 or higher\n", | |
682 | DRV_NAME, pci_name(dev)); | |
1da177e4 LT |
683 | ret = -EAGAIN; |
684 | goto out; | |
685 | } | |
ca1997c1 | 686 | ret = sgiioc4_ide_setup_pci_device(dev); |
1da177e4 LT |
687 | out: |
688 | return ret; | |
689 | } | |
690 | ||
1da177e4 | 691 | int |
22329b51 | 692 | ioc4_ide_attach_one(struct ioc4_driver_data *idd) |
1da177e4 | 693 | { |
f5befceb BC |
694 | /* PCI-RT does not bring out IDE connection. |
695 | * Do not attach to this particular IOC4. | |
696 | */ | |
697 | if (idd->idd_variant == IOC4_VARIANT_PCI_RT) | |
698 | return 0; | |
699 | ||
ca1997c1 | 700 | return pci_init_sgiioc4(idd->idd_pdev); |
1da177e4 LT |
701 | } |
702 | ||
22329b51 BC |
703 | static struct ioc4_submodule ioc4_ide_submodule = { |
704 | .is_name = "IOC4_ide", | |
705 | .is_owner = THIS_MODULE, | |
706 | .is_probe = ioc4_ide_attach_one, | |
707 | /* .is_remove = ioc4_ide_remove_one, */ | |
708 | }; | |
709 | ||
82ab1eec | 710 | static int __init ioc4_ide_init(void) |
22329b51 BC |
711 | { |
712 | return ioc4_register_submodule(&ioc4_ide_submodule); | |
713 | } | |
714 | ||
59f14800 | 715 | late_initcall(ioc4_ide_init); /* Call only after IDE init is done */ |
1da177e4 | 716 | |
a835fa79 | 717 | MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon"); |
1da177e4 LT |
718 | MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card"); |
719 | MODULE_LICENSE("GPL"); |