[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / sc1200.c

/*
 * Copyright (C) 2000-2002		Mark Lord <mlord@pobox.com>
 * Copyright (C)      2007		Bartlomiej Zolnierkiewicz
 *
 * May be copied or modified under the terms of the GNU General Public License
 *
 * Development of this chipset driver was funded
 * by the nice folks at National Semiconductor.
 *
 * Documentation:
 *	Available from National Semiconductor
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <linux/pm.h>
#include <asm/io.h>
#include <asm/irq.h>

#define SC1200_REV_A	0x00
#define SC1200_REV_B1	0x01
#define SC1200_REV_B3	0x02
#define SC1200_REV_C1	0x03
#define SC1200_REV_D1	0x04

#define PCI_CLK_33	0x00
#define PCI_CLK_48	0x01
#define PCI_CLK_66	0x02
#define PCI_CLK_33A	0x03

static unsigned short sc1200_get_pci_clock (void)
{
	unsigned char chip_id, silicon_revision;
	unsigned int pci_clock;
	/*
	 * Check the silicon revision, as not all versions of the chip
	 * have the register with the fast PCI bus timings.
	 */
	chip_id = inb (0x903c);
	silicon_revision = inb (0x903d);

	// Read the fast pci clock frequency
	if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
		pci_clock = PCI_CLK_33;
	} else {
		// check clock generator configuration (cfcc)
		// the clock is in bits 8 and 9 of this word

		pci_clock = inw (0x901e);
		pci_clock >>= 8;
		pci_clock &= 0x03;
		if (pci_clock == PCI_CLK_33A)
			pci_clock = PCI_CLK_33;
	}
	return pci_clock;
}

/*
 * Here are the standard PIO mode 0-4 timings for each "format".
 * Format-0 uses fast data reg timings, with slower command reg timings.
 * Format-1 uses fast timings for all registers, but won't work with all drives.
 */
static const unsigned int sc1200_pio_timings[4][5] =
	{{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},	// format0  33Mhz
	 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010},	// format1, 33Mhz
	 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021},	// format1, 48Mhz
	 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}};	// format1, 66Mhz

/*
 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
 */
//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)

static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;

	pci_read_config_dword(pdev, basereg + 4, &format);
	format = (format >> 31) & 1;
	if (format)
		format += sc1200_get_pci_clock();
	pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
			       sc1200_pio_timings[format][pio]);
}

/*
 *	The SC1200 specifies that two drives sharing a cable cannot mix
 *	UDMA/MDMA.  It has to be one or the other, for the pair, though
 *	different timings can still be chosen for each drive.  We could
 *	set the appropriate timing bits on the fly, but that might be
 *	a bit confusing.  So, for now we statically handle this requirement
 *	by looking at our mate drive to see what it is capable of, before
 *	choosing a mode for our own drive.
 */
static u8 sc1200_udma_filter(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
	struct hd_driveid *mateid = mate->id;
	u8 mask = hwif->ultra_mask;

	if (mate->present == 0)
		goto out;

	if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
		if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
			goto out;
		if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
			mask = 0;
	}
out:
	return mask;
}

static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
{
	ide_hwif_t		*hwif = HWIF(drive);
	struct pci_dev		*dev = to_pci_dev(hwif->dev);
	int			unit = drive->select.b.unit;
	unsigned int		reg, timings;
	unsigned short		pci_clock;
	unsigned int		basereg = hwif->channel ? 0x50 : 0x40;

	static const u32 udma_timing[3][3] = {
		{ 0x00921250, 0x00911140, 0x00911030 },
		{ 0x00932470, 0x00922260, 0x00922140 },
		{ 0x009436a1, 0x00933481, 0x00923261 },
	};

	static const u32 mwdma_timing[3][3] = {
		{ 0x00077771, 0x00012121, 0x00002020 },
		{ 0x000bbbb2, 0x00024241, 0x00013131 },
		{ 0x000ffff3, 0x00035352, 0x00015151 },
	};

	pci_clock = sc1200_get_pci_clock();

	/*
	 * Note that each DMA mode has several timings associated with it.
	 * The correct timing depends on the fast PCI clock freq.
	 */

	if (mode >= XFER_UDMA_0)
		timings =  udma_timing[pci_clock][mode - XFER_UDMA_0];
	else
		timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];

	if (unit == 0) {			/* are we configuring drive0? */
		pci_read_config_dword(dev, basereg + 4, &reg);
		timings |= reg & 0x80000000;	/* preserve PIO format bit */
		pci_write_config_dword(dev, basereg + 4, timings);
	} else
		pci_write_config_dword(dev, basereg + 12, timings);
}

/*  Replacement for the standard ide_dma_end action in
 *  dma_proc.
 *
 *  returns 1 on error, 0 otherwise
 */
static int sc1200_ide_dma_end (ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	unsigned long dma_base = hwif->dma_base;
	byte dma_stat;

	dma_stat = inb(dma_base+2);		/* get DMA status */

	if (!(dma_stat & 4))
		printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
		  dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));

	outb(dma_stat|0x1b, dma_base+2);	/* clear the INTR & ERROR bits */
	outb(inb(dma_base)&~1, dma_base);	/* !! DO THIS HERE !! stop DMA */

	drive->waiting_for_dma = 0;
	ide_destroy_dmatable(drive);		/* purge DMA mappings */

	return (dma_stat & 7) != 4;		/* verify good DMA status */
}

/*
 * sc1200_set_pio_mode() handles setting of PIO modes
 * for both the chipset and drive.
 *
 * All existing BIOSs for this chipset guarantee that all drives
 * will have valid default PIO timings set up before we get here.
 */

static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t	*hwif = HWIF(drive);
	int		mode = -1;

	/*
	 * bad abuse of ->set_pio_mode interface
	 */
	switch (pio) {
		case 200: mode = XFER_UDMA_0;	break;
		case 201: mode = XFER_UDMA_1;	break;
		case 202: mode = XFER_UDMA_2;	break;
		case 100: mode = XFER_MW_DMA_0;	break;
		case 101: mode = XFER_MW_DMA_1;	break;
		case 102: mode = XFER_MW_DMA_2;	break;
	}
	if (mode != -1) {
		printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
		ide_dma_off_quietly(drive);
		if (ide_set_dma_mode(drive, mode) == 0 && drive->using_dma)
			hwif->dma_host_set(drive, 1);
		return;
	}

	sc1200_tunepio(drive, pio);
}

#ifdef CONFIG_PM
struct sc1200_saved_state {
	u32 regs[8];
};

static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
{
	printk("SC1200: suspend(%u)\n", state.event);

	/*
	 * we only save state when going from full power to less
	 */
	if (state.event == PM_EVENT_ON) {
		struct sc1200_saved_state *ss;
		unsigned int r;

		/*
		 * allocate a permanent save area, if not already allocated
		 */
		ss = (struct sc1200_saved_state *)pci_get_drvdata(dev);
		if (ss == NULL) {
			ss = kmalloc(sizeof(*ss), GFP_KERNEL);
			if (ss == NULL)
				return -ENOMEM;
			pci_set_drvdata(dev, ss);
		}

		/*
		 * save timing registers
		 * (this may be unnecessary if BIOS also does it)
		 */
		for (r = 0; r < 8; r++)
			pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
	}

	pci_disable_device(dev);
	pci_set_power_state(dev, pci_choose_state(dev, state));
	return 0;
}

static int sc1200_resume (struct pci_dev *dev)
{
	struct sc1200_saved_state *ss;
	unsigned int r;
	int i;

	i = pci_enable_device(dev);
	if (i)
		return i;

	ss = (struct sc1200_saved_state *)pci_get_drvdata(dev);

	/*
	 * restore timing registers
	 * (this may be unnecessary if BIOS also does it)
	 */
	if (ss) {
		for (r = 0; r < 8; r++)
			pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);
	}

	return 0;
}
#endif

/*
 * This gets invoked by the IDE driver once for each channel,
 * and performs channel-specific pre-initialization before drive probing.
 */
static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &sc1200_set_pio_mode;
	hwif->set_dma_mode = &sc1200_set_dma_mode;

	if (hwif->dma_base == 0)
		return;

	hwif->udma_filter = sc1200_udma_filter;
	hwif->ide_dma_end   = &sc1200_ide_dma_end;
}

static const struct ide_port_info sc1200_chipset __devinitdata = {
	.name		= "SC1200",
	.init_hwif	= init_hwif_sc1200,
	.host_flags	= IDE_HFLAG_SERIALIZE |
			  IDE_HFLAG_POST_SET_MODE |
			  IDE_HFLAG_ABUSE_DMA_MODES |
			  IDE_HFLAG_BOOTABLE,
	.pio_mask	= ATA_PIO4,
	.mwdma_mask	= ATA_MWDMA2,
	.udma_mask	= ATA_UDMA2,
};

static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &sc1200_chipset);
}

static const struct pci_device_id sc1200_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);

static struct pci_driver driver = {
	.name		= "SC1200_IDE",
	.id_table	= sc1200_pci_tbl,
	.probe		= sc1200_init_one,
#ifdef CONFIG_PM
	.suspend	= sc1200_suspend,
	.resume		= sc1200_resume,
#endif
};

static int __init sc1200_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(sc1200_ide_init);

MODULE_AUTHOR("Mark Lord");
MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
5fd216bb BZ	3	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5fd216bb BZ	4	*
1da177e4 LT	5	* May be copied or modified under the terms of the GNU General Public License
	6	*
	7	* Development of this chipset driver was funded
	8	* by the nice folks at National Semiconductor.
	9	*
	10	* Documentation:
	11	* Available from National Semiconductor
	12	*/
	13
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/types.h>
	16	#include <linux/kernel.h>
	17	#include <linux/delay.h>
	18	#include <linux/timer.h>
	19	#include <linux/mm.h>
	20	#include <linux/ioport.h>
	21	#include <linux/blkdev.h>
	22	#include <linux/hdreg.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/pci.h>
	25	#include <linux/init.h>
	26	#include <linux/ide.h>
	27	#include <linux/pm.h>
	28	#include <asm/io.h>
	29	#include <asm/irq.h>
	30
	31	#define SC1200_REV_A 0x00
	32	#define SC1200_REV_B1 0x01
	33	#define SC1200_REV_B3 0x02
	34	#define SC1200_REV_C1 0x03
	35	#define SC1200_REV_D1 0x04
	36
	37	#define PCI_CLK_33 0x00
	38	#define PCI_CLK_48 0x01
	39	#define PCI_CLK_66 0x02
	40	#define PCI_CLK_33A 0x03
	41
	42	static unsigned short sc1200_get_pci_clock (void)
	43	{
	44	unsigned char chip_id, silicon_revision;
	45	unsigned int pci_clock;
	46	/*
	47	* Check the silicon revision, as not all versions of the chip
	48	* have the register with the fast PCI bus timings.
	49	*/
	50	chip_id = inb (0x903c);
	51	silicon_revision = inb (0x903d);
	52
	53	// Read the fast pci clock frequency
	54	if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
	55	pci_clock = PCI_CLK_33;
	56	} else {
	57	// check clock generator configuration (cfcc)
	58	// the clock is in bits 8 and 9 of this word
	59
	60	pci_clock = inw (0x901e);
	61	pci_clock >>= 8;
	62	pci_clock &= 0x03;
	63	if (pci_clock == PCI_CLK_33A)
	64	pci_clock = PCI_CLK_33;
	65	}
	66	return pci_clock;
	67	}
	68
1da177e4 LT	69	/*
	70	* Here are the standard PIO mode 0-4 timings for each "format".
	71	* Format-0 uses fast data reg timings, with slower command reg timings.
	72	* Format-1 uses fast timings for all registers, but won't work with all drives.
	73	*/
	74	static const unsigned int sc1200_pio_timings[4][5] =
	75	{{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
	76	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
	77	{0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
	78	{0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
	79
	80	/*
	81	* After chip reset, the PIO timings are set to 0x00009172, which is not valid.
	82	*/
	83	//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
	84
3c3f5d2c BZ	85	static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
	86	{
	87	ide_hwif_t *hwif = drive->hwif;
36501650	88	struct pci_dev *pdev = to_pci_dev(hwif->dev);
3c3f5d2c BZ	89	unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
	90
	91	pci_read_config_dword(pdev, basereg + 4, &format);
	92	format = (format >> 31) & 1;
	93	if (format)
	94	format += sc1200_get_pci_clock();
	95	pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
	96	sc1200_pio_timings[format][pio]);
	97	}
	98
5fd216bb BZ	99	/*
	100	* The SC1200 specifies that two drives sharing a cable cannot mix
	101	* UDMA/MDMA. It has to be one or the other, for the pair, though
	102	* different timings can still be chosen for each drive. We could
	103	* set the appropriate timing bits on the fly, but that might be
	104	* a bit confusing. So, for now we statically handle this requirement
	105	* by looking at our mate drive to see what it is capable of, before
	106	* choosing a mode for our own drive.
	107	*/
	108	static u8 sc1200_udma_filter(ide_drive_t *drive)
1da177e4	109	{
5fd216bb BZ	110	ide_hwif_t *hwif = drive->hwif;
	111	ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
	112	struct hd_driveid *mateid = mate->id;
	113	u8 mask = hwif->ultra_mask;
	114
	115	if (mate->present == 0)
	116	goto out;
	117
	118	if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
	119	if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
	120	goto out;
	121	if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
	122	mask = 0;
1da177e4	123	}
5fd216bb BZ	124	out:
5fd216bb BZ	125	return mask;
1da177e4 LT	126	}
1da177e4 LT	127
88b2b32b	128	static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
1da177e4 LT	129	{
1da177e4 LT	130	ide_hwif_t *hwif = HWIF(drive);
36501650	131	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 LT	132	int unit = drive->select.b.unit;
	133	unsigned int reg, timings;
	134	unsigned short pci_clock;
	135	unsigned int basereg = hwif->channel ? 0x50 : 0x40;
	136
4eed504d BZ	137	static const u32 udma_timing[3][3] = {
	138	{ 0x00921250, 0x00911140, 0x00911030 },
	139	{ 0x00932470, 0x00922260, 0x00922140 },
	140	{ 0x009436a1, 0x00933481, 0x00923261 },
	141	};
	142
	143	static const u32 mwdma_timing[3][3] = {
	144	{ 0x00077771, 0x00012121, 0x00002020 },
	145	{ 0x000bbbb2, 0x00024241, 0x00013131 },
	146	{ 0x000ffff3, 0x00035352, 0x00015151 },
	147	};
	148
1da177e4 LT	149	pci_clock = sc1200_get_pci_clock();
	150
	151	/*
1da177e4 LT	152	* Note that each DMA mode has several timings associated with it.
	153	* The correct timing depends on the fast PCI clock freq.
	154	*/
4eed504d BZ	155
	156	if (mode >= XFER_UDMA_0)
	157	timings = udma_timing[pci_clock][mode - XFER_UDMA_0];
	158	else
	159	timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];
1da177e4 LT	160
1da177e4 LT	161	if (unit == 0) { /* are we configuring drive0? */
36501650	162	pci_read_config_dword(dev, basereg + 4, &reg);
1da177e4	163	timings \|= reg & 0x80000000; /* preserve PIO format bit */
36501650 BZ	164	pci_write_config_dword(dev, basereg + 4, timings);
	165	} else
	166	pci_write_config_dword(dev, basereg + 12, timings);
1da177e4 LT	167	}
1da177e4 LT	168
1da177e4 LT	169	/* Replacement for the standard ide_dma_end action in
	170	* dma_proc.
	171	*
	172	* returns 1 on error, 0 otherwise
	173	*/
	174	static int sc1200_ide_dma_end (ide_drive_t *drive)
	175	{
	176	ide_hwif_t *hwif = HWIF(drive);
	177	unsigned long dma_base = hwif->dma_base;
	178	byte dma_stat;
	179
	180	dma_stat = inb(dma_base+2); /* get DMA status */
	181
	182	if (!(dma_stat & 4))
	183	printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
	184	dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
	185
	186	outb(dma_stat\|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
	187	outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
	188
	189	drive->waiting_for_dma = 0;
	190	ide_destroy_dmatable(drive); /* purge DMA mappings */
	191
	192	return (dma_stat & 7) != 4; /* verify good DMA status */
	193	}
	194
	195	/*
26bcb879	196	* sc1200_set_pio_mode() handles setting of PIO modes
1da177e4 LT	197	* for both the chipset and drive.
	198	*
	199	* All existing BIOSs for this chipset guarantee that all drives
	200	* will have valid default PIO timings set up before we get here.
	201	*/
26bcb879 BZ	202
26bcb879 BZ	203	static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	204	{
1da177e4 LT	205	ide_hwif_t *hwif = HWIF(drive);
1da177e4 LT	206	int mode = -1;
1da177e4 LT	207
a01ba401	208	/*
26bcb879	209	* bad abuse of ->set_pio_mode interface
a01ba401	210	*/
1da177e4 LT	211	switch (pio) {
	212	case 200: mode = XFER_UDMA_0; break;
	213	case 201: mode = XFER_UDMA_1; break;
	214	case 202: mode = XFER_UDMA_2; break;
	215	case 100: mode = XFER_MW_DMA_0; break;
	216	case 101: mode = XFER_MW_DMA_1; break;
	217	case 102: mode = XFER_MW_DMA_2; break;
	218	}
	219	if (mode != -1) {
	220	printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
4a546e04	221	ide_dma_off_quietly(drive);
f37aaf9e	222	if (ide_set_dma_mode(drive, mode) == 0 && drive->using_dma)
15ce926a	223	hwif->dma_host_set(drive, 1);
1da177e4 LT	224	return;
	225	}
	226
88b2b32b	227	sc1200_tunepio(drive, pio);
1da177e4 LT	228	}
1da177e4 LT	229
b86cc29d	230	#ifdef CONFIG_PM
7c0e2666 BZ	231	struct sc1200_saved_state {
	232	u32 regs[8];
	233	};
1da177e4	234
3bfffd97	235	static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
1da177e4	236	{
ca078bae	237	printk("SC1200: suspend(%u)\n", state.event);
1da177e4	238
7c0e2666 BZ	239	/*
	240	* we only save state when going from full power to less
	241	*/
ca078bae	242	if (state.event == PM_EVENT_ON) {
7c0e2666 BZ	243	struct sc1200_saved_state *ss;
	244	unsigned int r;
	245
	246	/*
	247	* allocate a permanent save area, if not already allocated
	248	*/
	249	ss = (struct sc1200_saved_state *)pci_get_drvdata(dev);
	250	if (ss == NULL) {
	251	ss = kmalloc(sizeof(*ss), GFP_KERNEL);
	252	if (ss == NULL)
	253	return -ENOMEM;
	254	pci_set_drvdata(dev, ss);
1da177e4	255	}
1da177e4	256
7c0e2666 BZ	257	/*
	258	* save timing registers
	259	* (this may be unnecessary if BIOS also does it)
	260	*/
	261	for (r = 0; r < 8; r++)
	262	pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
	263	}
1da177e4 LT	264
1da177e4 LT	265	pci_disable_device(dev);
ca078bae	266	pci_set_power_state(dev, pci_choose_state(dev, state));
1da177e4 LT	267	return 0;
	268	}
	269
	270	static int sc1200_resume (struct pci_dev *dev)
	271	{
7c0e2666 BZ	272	struct sc1200_saved_state *ss;
	273	unsigned int r;
	274	int i;
9d434813 JG	275
	276	i = pci_enable_device(dev);
	277	if (i)
	278	return i;
1da177e4	279
7c0e2666 BZ	280	ss = (struct sc1200_saved_state *)pci_get_drvdata(dev);
	281
	282	/*
	283	* restore timing registers
	284	* (this may be unnecessary if BIOS also does it)
	285	*/
	286	if (ss) {
	287	for (r = 0; r < 8; r++)
	288	pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);
1da177e4	289	}
7c0e2666	290
1da177e4 LT	291	return 0;
1da177e4 LT	292	}
b86cc29d	293	#endif
1da177e4 LT	294
	295	/*
	296	* This gets invoked by the IDE driver once for each channel,
	297	* and performs channel-specific pre-initialization before drive probing.
	298	*/
6a6e1b1c	299	static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif)
1da177e4	300	{
88ae4d8c BZ	301	hwif->set_pio_mode = &sc1200_set_pio_mode;
	302	hwif->set_dma_mode = &sc1200_set_dma_mode;
	303
	304	if (hwif->dma_base == 0)
	305	return;
	306
	307	hwif->udma_filter = sc1200_udma_filter;
88ae4d8c	308	hwif->ide_dma_end = &sc1200_ide_dma_end;
1da177e4 LT	309	}
1da177e4 LT	310
85620436	311	static const struct ide_port_info sc1200_chipset __devinitdata = {
1da177e4 LT	312	.name = "SC1200",
1da177e4 LT	313	.init_hwif = init_hwif_sc1200,
1c51361a BZ	314	.host_flags = IDE_HFLAG_SERIALIZE \|
	315	IDE_HFLAG_POST_SET_MODE \|
	316	IDE_HFLAG_ABUSE_DMA_MODES \|
7cab14a7	317	IDE_HFLAG_BOOTABLE,
4099d143	318	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	319	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	320	.udma_mask = ATA_UDMA2,
1da177e4 LT	321	};
	322
	323	static int __devinit sc1200_init_one(struct pci_dev dev, const struct pci_device_id id)
	324	{
	325	return ide_setup_pci_device(dev, &sc1200_chipset);
	326	}
	327
9cbcc5e3 BZ	328	static const struct pci_device_id sc1200_pci_tbl[] = {
9cbcc5e3 BZ	329	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
1da177e4 LT	330	{ 0, },
	331	};
	332	MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
	333
	334	static struct pci_driver driver = {
	335	.name = "SC1200_IDE",
	336	.id_table = sc1200_pci_tbl,
	337	.probe = sc1200_init_one,
b86cc29d	338	#ifdef CONFIG_PM
1da177e4 LT	339	.suspend = sc1200_suspend,
1da177e4 LT	340	.resume = sc1200_resume,
b86cc29d	341	#endif
1da177e4 LT	342	};
1da177e4 LT	343
82ab1eec	344	static int __init sc1200_ide_init(void)
1da177e4 LT	345	{
	346	return ide_pci_register_driver(&driver);
	347	}
	348
	349	module_init(sc1200_ide_init);
	350
	351	MODULE_AUTHOR("Mark Lord");
	352	MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
	353	MODULE_LICENSE("GPL");