projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| 44854add | 2 | * linux/drivers/ide/pci/piix.c Version 0.45 May 12, 2006 |
| 1da177e4 LT |
3 | * |
| 4 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
| 5 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
| 6 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
| 44854add | 7 | * Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com> |
| 1da177e4 LT |
8 | * |
| 9 | * May be copied or modified under the terms of the GNU General Public License | |
| 10 | * | |
| 44854add | 11 | * PIO mode setting function for Intel chipsets. |
| 1da177e4 LT |
12 | * For use instead of BIOS settings. |
| 13 | * | |
| 14 | * 40-41 | |
| 15 | * 42-43 | |
| 16 | * | |
| 17 | * 41 | |
| 18 | * 43 | |
| 19 | * | |
| 20 | * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0); | |
| 21 | * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2); | |
| 22 | * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3); | |
| 23 | * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4); | |
| 24 | * | |
| 25 | * sitre = word40 & 0x4000; primary | |
| 26 | * sitre = word42 & 0x4000; secondary | |
| 27 | * | |
| 28 | * 44 8421|8421 hdd|hdb | |
| 44854add | 29 | * |
| 1da177e4 LT |
30 | * 48 8421 hdd|hdc|hdb|hda udma enabled |
| 31 | * | |
| 32 | * 0001 hda | |
| 33 | * 0010 hdb | |
| 34 | * 0100 hdc | |
| 35 | * 1000 hdd | |
| 36 | * | |
| 37 | * 4a 84|21 hdb|hda | |
| 38 | * 4b 84|21 hdd|hdc | |
| 39 | * | |
| 40 | * ata-33/82371AB | |
| 41 | * ata-33/82371EB | |
| 42 | * ata-33/82801AB ata-66/82801AA | |
| 43 | * 00|00 udma 0 00|00 reserved | |
| 44 | * 01|01 udma 1 01|01 udma 3 | |
| 45 | * 10|10 udma 2 10|10 udma 4 | |
| 46 | * 11|11 reserved 11|11 reserved | |
| 47 | * | |
| 48 | * 54 8421|8421 ata66 drive|ata66 enable | |
| 49 | * | |
| 50 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40); | |
| 51 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42); | |
| 52 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44); | |
| 53 | * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48); | |
| 54 | * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a); | |
| 55 | * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54); | |
| 56 | * | |
| 57 | * Documentation | |
| 58 | * Publically available from Intel web site. Errata documentation | |
| 59 | * is also publically available. As an aide to anyone hacking on this | |
| 60 | * driver the list of errata that are relevant is below.going back to | |
| 61 | * PIIX4. Older device documentation is now a bit tricky to find. | |
| 62 | * | |
| 63 | * Errata of note: | |
| 64 | * | |
| 65 | * Unfixable | |
| 66 | * PIIX4 errata #9 - Only on ultra obscure hw | |
| 67 | * ICH3 errata #13 - Not observed to affect real hw | |
| 68 | * by Intel | |
| 69 | * | |
| 70 | * Things we must deal with | |
| 71 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
| 72 | * (must stop/start dma to recover) | |
| 73 | * 440MX errata #15 - As PIIX4 errata #10 | |
| 74 | * PIIX4 errata #15 - Must not read control registers | |
| 75 | * during a PIO transfer | |
| 76 | * 440MX errata #13 - As PIIX4 errata #15 | |
| 77 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
| 78 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
| 79 | * ICH2 spec c #9 - Extra operations needed to handle | |
| 80 | * drive hotswap [NOT YET SUPPORTED] | |
| 81 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
| 82 | * and must be dword aligned | |
| 83 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
| 84 | * | |
| 85 | * Should have been BIOS fixed: | |
| 86 | * 450NX: errata #19 - DMA hangs on old 450NX | |
| 87 | * 450NX: errata #20 - DMA hangs on old 450NX | |
| 88 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
| 89 | * ICH3 errata #15 - IDE deadlock under high load | |
| 90 | * (BIOS must set dev 31 fn 0 bit 23) | |
| 91 | * ICH3 errata #18 - Don't use native mode | |
| 92 | */ | |
| 93 | ||
| 1da177e4 LT |
94 | #include <linux/types.h> |
| 95 | #include <linux/module.h> | |
| 96 | #include <linux/kernel.h> | |
| 97 | #include <linux/ioport.h> | |
| 98 | #include <linux/pci.h> | |
| 99 | #include <linux/hdreg.h> | |
| 100 | #include <linux/ide.h> | |
| 101 | #include <linux/delay.h> | |
| 102 | #include <linux/init.h> | |
| 103 | ||
| 104 | #include <asm/io.h> | |
| 105 | ||
| 106 | static int no_piix_dma; | |
| 107 | ||
| 108 | /** | |
| 109 | * piix_ratemask - compute rate mask for PIIX IDE | |
| 110 | * @drive: IDE drive to compute for | |
| 111 | * | |
| 112 | * Returns the available modes for the PIIX IDE controller. | |
| 113 | */ | |
| 114 | ||
| 115 | static u8 piix_ratemask (ide_drive_t *drive) | |
| 116 | { | |
| 117 | struct pci_dev *dev = HWIF(drive)->pci_dev; | |
| 118 | u8 mode; | |
| 119 | ||
| 120 | switch(dev->device) { | |
| 121 | case PCI_DEVICE_ID_INTEL_82801EB_1: | |
| 122 | mode = 3; | |
| 123 | break; | |
| 124 | /* UDMA 100 capable */ | |
| 125 | case PCI_DEVICE_ID_INTEL_82801BA_8: | |
| 126 | case PCI_DEVICE_ID_INTEL_82801BA_9: | |
| 127 | case PCI_DEVICE_ID_INTEL_82801CA_10: | |
| 128 | case PCI_DEVICE_ID_INTEL_82801CA_11: | |
| 129 | case PCI_DEVICE_ID_INTEL_82801E_11: | |
| 130 | case PCI_DEVICE_ID_INTEL_82801DB_1: | |
| 131 | case PCI_DEVICE_ID_INTEL_82801DB_10: | |
| 132 | case PCI_DEVICE_ID_INTEL_82801DB_11: | |
| 133 | case PCI_DEVICE_ID_INTEL_82801EB_11: | |
| 134 | case PCI_DEVICE_ID_INTEL_ESB_2: | |
| 135 | case PCI_DEVICE_ID_INTEL_ICH6_19: | |
| 136 | case PCI_DEVICE_ID_INTEL_ICH7_21: | |
| d69332b8 | 137 | case PCI_DEVICE_ID_INTEL_ESB2_18: |
| b7bed9ec | 138 | case PCI_DEVICE_ID_INTEL_ICH8_6: |
| 1da177e4 LT |
139 | mode = 3; |
| 140 | break; | |
| 141 | /* UDMA 66 capable */ | |
| 142 | case PCI_DEVICE_ID_INTEL_82801AA_1: | |
| 143 | case PCI_DEVICE_ID_INTEL_82372FB_1: | |
| 144 | mode = 2; | |
| 145 | break; | |
| 146 | /* UDMA 33 capable */ | |
| 147 | case PCI_DEVICE_ID_INTEL_82371AB: | |
| 148 | case PCI_DEVICE_ID_INTEL_82443MX_1: | |
| 149 | case PCI_DEVICE_ID_INTEL_82451NX: | |
| 150 | case PCI_DEVICE_ID_INTEL_82801AB_1: | |
| 151 | return 1; | |
| 152 | /* Non UDMA capable (MWDMA2) */ | |
| 153 | case PCI_DEVICE_ID_INTEL_82371SB_1: | |
| 154 | case PCI_DEVICE_ID_INTEL_82371FB_1: | |
| 155 | case PCI_DEVICE_ID_INTEL_82371FB_0: | |
| 156 | case PCI_DEVICE_ID_INTEL_82371MX: | |
| 157 | default: | |
| 158 | return 0; | |
| 159 | } | |
| 160 | ||
| 161 | /* | |
| 162 | * If we are UDMA66 capable fall back to UDMA33 | |
| 163 | * if the drive cannot see an 80pin cable. | |
| 164 | */ | |
| 165 | if (!eighty_ninty_three(drive)) | |
| 166 | mode = min(mode, (u8)1); | |
| 167 | return mode; | |
| 168 | } | |
| 169 | ||
| 170 | /** | |
| 171 | * piix_dma_2_pio - return the PIO mode matching DMA | |
| 172 | * @xfer_rate: transfer speed | |
| 173 | * | |
| 174 | * Returns the nearest equivalent PIO timing for the PIO or DMA | |
| 175 | * mode requested by the controller. | |
| 176 | */ | |
| 177 | ||
| 178 | static u8 piix_dma_2_pio (u8 xfer_rate) { | |
| 179 | switch(xfer_rate) { | |
| 180 | case XFER_UDMA_6: | |
| 181 | case XFER_UDMA_5: | |
| 182 | case XFER_UDMA_4: | |
| 183 | case XFER_UDMA_3: | |
| 184 | case XFER_UDMA_2: | |
| 185 | case XFER_UDMA_1: | |
| 186 | case XFER_UDMA_0: | |
| 187 | case XFER_MW_DMA_2: | |
| 188 | case XFER_PIO_4: | |
| 189 | return 4; | |
| 190 | case XFER_MW_DMA_1: | |
| 191 | case XFER_PIO_3: | |
| 192 | return 3; | |
| 193 | case XFER_SW_DMA_2: | |
| 194 | case XFER_PIO_2: | |
| 195 | return 2; | |
| 196 | case XFER_MW_DMA_0: | |
| 197 | case XFER_SW_DMA_1: | |
| 198 | case XFER_SW_DMA_0: | |
| 199 | case XFER_PIO_1: | |
| 200 | case XFER_PIO_0: | |
| 201 | case XFER_PIO_SLOW: | |
| 202 | default: | |
| 203 | return 0; | |
| 204 | } | |
| 205 | } | |
| 206 | ||
| 207 | /** | |
| 208 | * piix_tune_drive - tune a drive attached to a PIIX | |
| 209 | * @drive: drive to tune | |
| 210 | * @pio: desired PIO mode | |
| 211 | * | |
| 212 | * Set the interface PIO mode based upon the settings done by AMI BIOS | |
| 213 | * (might be useful if drive is not registered in CMOS for any reason). | |
| 214 | */ | |
| 215 | static void piix_tune_drive (ide_drive_t *drive, u8 pio) | |
| 216 | { | |
| 217 | ide_hwif_t *hwif = HWIF(drive); | |
| 218 | struct pci_dev *dev = hwif->pci_dev; | |
| 219 | int is_slave = (&hwif->drives[1] == drive); | |
| 220 | int master_port = hwif->channel ? 0x42 : 0x40; | |
| 221 | int slave_port = 0x44; | |
| 222 | unsigned long flags; | |
| 223 | u16 master_data; | |
| 224 | u8 slave_data; | |
| 4fb0f76d | 225 | static DEFINE_SPINLOCK(tune_lock); |
| 5ac24697 | 226 | int control = 0; |
| 4fb0f76d | 227 | |
| 1da177e4 | 228 | /* ISP RTC */ |
| 5ac24697 AC |
229 | static const u8 timings[][2]= { |
| 230 | { 0, 0 }, | |
| 231 | { 0, 0 }, | |
| 232 | { 1, 0 }, | |
| 233 | { 2, 1 }, | |
| 234 | { 2, 3 }, }; | |
| 1da177e4 LT |
235 | |
| 236 | pio = ide_get_best_pio_mode(drive, pio, 5, NULL); | |
| 4fb0f76d AC |
237 | |
| 238 | /* | |
| 239 | * Master vs slave is synchronized above us but the slave register is | |
| 240 | * shared by the two hwifs so the corner case of two slave timeouts in | |
| 241 | * parallel must be locked. | |
| 242 | */ | |
| 243 | spin_lock_irqsave(&tune_lock, flags); | |
| 1da177e4 | 244 | pci_read_config_word(dev, master_port, &master_data); |
| 5ac24697 AC |
245 | |
| 246 | if (pio >= 2) | |
| 247 | control |= 1; /* Programmable timing on */ | |
| 248 | if (drive->media == ide_disk) | |
| 249 | control |= 4; /* Prefetch, post write */ | |
| 250 | if (pio >= 3) | |
| 251 | control |= 2; /* IORDY */ | |
| 1da177e4 LT |
252 | if (is_slave) { |
| 253 | master_data = master_data | 0x4000; | |
| 5ac24697 | 254 | if (pio > 1) { |
| 1da177e4 | 255 | /* enable PPE, IE and TIME */ |
| 5ac24697 AC |
256 | master_data = master_data | (control << 4); |
| 257 | } else { | |
| 258 | master_data &= ~0x0070; | |
| 259 | } | |
| 1da177e4 LT |
260 | pci_read_config_byte(dev, slave_port, &slave_data); |
| 261 | slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0); | |
| 262 | slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0)); | |
| 263 | } else { | |
| 264 | master_data = master_data & 0xccf8; | |
| 5ac24697 | 265 | if (pio > 1) { |
| 1da177e4 | 266 | /* enable PPE, IE and TIME */ |
| 5ac24697 AC |
267 | master_data = master_data | control; |
| 268 | } | |
| 1da177e4 LT |
269 | master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8); |
| 270 | } | |
| 271 | pci_write_config_word(dev, master_port, master_data); | |
| 272 | if (is_slave) | |
| 273 | pci_write_config_byte(dev, slave_port, slave_data); | |
| 4fb0f76d | 274 | spin_unlock_irqrestore(&tune_lock, flags); |
| 1da177e4 LT |
275 | } |
| 276 | ||
| 277 | /** | |
| 278 | * piix_tune_chipset - tune a PIIX interface | |
| 279 | * @drive: IDE drive to tune | |
| 280 | * @xferspeed: speed to configure | |
| 281 | * | |
| 282 | * Set a PIIX interface channel to the desired speeds. This involves | |
| 283 | * requires the right timing data into the PIIX configuration space | |
| 284 | * then setting the drive parameters appropriately | |
| 285 | */ | |
| 286 | ||
| 287 | static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed) | |
| 288 | { | |
| 289 | ide_hwif_t *hwif = HWIF(drive); | |
| 290 | struct pci_dev *dev = hwif->pci_dev; | |
| 291 | u8 maslave = hwif->channel ? 0x42 : 0x40; | |
| 292 | u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed); | |
| 293 | int a_speed = 3 << (drive->dn * 4); | |
| 294 | int u_flag = 1 << drive->dn; | |
| 295 | int v_flag = 0x01 << drive->dn; | |
| 296 | int w_flag = 0x10 << drive->dn; | |
| 297 | int u_speed = 0; | |
| 298 | int sitre; | |
| 299 | u16 reg4042, reg4a; | |
| 300 | u8 reg48, reg54, reg55; | |
| 301 | ||
| 302 | pci_read_config_word(dev, maslave, ®4042); | |
| 303 | sitre = (reg4042 & 0x4000) ? 1 : 0; | |
| 304 | pci_read_config_byte(dev, 0x48, ®48); | |
| 305 | pci_read_config_word(dev, 0x4a, ®4a); | |
| 306 | pci_read_config_byte(dev, 0x54, ®54); | |
| 307 | pci_read_config_byte(dev, 0x55, ®55); | |
| 308 | ||
| 309 | switch(speed) { | |
| 310 | case XFER_UDMA_4: | |
| 311 | case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break; | |
| 312 | case XFER_UDMA_5: | |
| 313 | case XFER_UDMA_3: | |
| 314 | case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break; | |
| 315 | case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break; | |
| 316 | case XFER_MW_DMA_2: | |
| 317 | case XFER_MW_DMA_1: | |
| 318 | case XFER_SW_DMA_2: break; | |
| 319 | case XFER_PIO_4: | |
| 320 | case XFER_PIO_3: | |
| 321 | case XFER_PIO_2: | |
| 322 | case XFER_PIO_0: break; | |
| 323 | default: return -1; | |
| 324 | } | |
| 325 | ||
| 326 | if (speed >= XFER_UDMA_0) { | |
| 327 | if (!(reg48 & u_flag)) | |
| 328 | pci_write_config_byte(dev, 0x48, reg48 | u_flag); | |
| 329 | if (speed == XFER_UDMA_5) { | |
| 330 | pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); | |
| 331 | } else { | |
| 332 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
| 333 | } | |
| 334 | if ((reg4a & a_speed) != u_speed) | |
| 335 | pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); | |
| 336 | if (speed > XFER_UDMA_2) { | |
| 337 | if (!(reg54 & v_flag)) | |
| 338 | pci_write_config_byte(dev, 0x54, reg54 | v_flag); | |
| 339 | } else | |
| 340 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
| 341 | } else { | |
| 342 | if (reg48 & u_flag) | |
| 343 | pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); | |
| 344 | if (reg4a & a_speed) | |
| 345 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); | |
| 346 | if (reg54 & v_flag) | |
| 347 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); | |
| 348 | if (reg55 & w_flag) | |
| 349 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); | |
| 350 | } | |
| 351 | ||
| 352 | piix_tune_drive(drive, piix_dma_2_pio(speed)); | |
| 353 | return (ide_config_drive_speed(drive, speed)); | |
| 354 | } | |
| 355 | ||
| 1da177e4 LT |
356 | /** |
| 357 | * piix_config_drive_for_dma - configure drive for DMA | |
| 358 | * @drive: IDE drive to configure | |
| 359 | * | |
| 360 | * Set up a PIIX interface channel for the best available speed. | |
| 44854add SS |
361 | * We prefer UDMA if it is available and then MWDMA. If DMA is |
| 362 | * not available we switch to PIO and return 0. | |
| 1da177e4 LT |
363 | */ |
| 364 | ||
| 365 | static int piix_config_drive_for_dma (ide_drive_t *drive) | |
| 366 | { | |
| 367 | u8 speed = ide_dma_speed(drive, piix_ratemask(drive)); | |
| 1da177e4 | 368 | |
| 44854add SS |
369 | /* |
| 370 | * If no DMA speed was available or the chipset has DMA bugs | |
| 371 | * then disable DMA and use PIO | |
| 372 | */ | |
| 373 | if (!speed || no_piix_dma) | |
| 374 | return 0; | |
| 1da177e4 LT |
375 | |
| 376 | (void) piix_tune_chipset(drive, speed); | |
| 377 | return ide_dma_enable(drive); | |
| 378 | } | |
| 379 | ||
| 380 | /** | |
| 381 | * piix_config_drive_xfer_rate - set up an IDE device | |
| 382 | * @drive: IDE drive to configure | |
| 383 | * | |
| 384 | * Set up the PIIX interface for the best available speed on this | |
| 385 | * interface, preferring DMA to PIO. | |
| 386 | */ | |
| 387 | ||
| 388 | static int piix_config_drive_xfer_rate (ide_drive_t *drive) | |
| 389 | { | |
| 390 | ide_hwif_t *hwif = HWIF(drive); | |
| 391 | struct hd_driveid *id = drive->id; | |
| 392 | ||
| 393 | drive->init_speed = 0; | |
| 394 | ||
| 395 | if ((id->capability & 1) && drive->autodma) { | |
| 396 | ||
| 44854add SS |
397 | if (ide_use_dma(drive) && piix_config_drive_for_dma(drive)) |
| 398 | return hwif->ide_dma_on(drive); | |
| 1da177e4 LT |
399 | |
| 400 | goto fast_ata_pio; | |
| 401 | ||
| 402 | } else if ((id->capability & 8) || (id->field_valid & 2)) { | |
| 403 | fast_ata_pio: | |
| 404 | /* Find best PIO mode. */ | |
| 44854add SS |
405 | (void) hwif->speedproc(drive, XFER_PIO_0 + |
| 406 | ide_get_best_pio_mode(drive, 255, 4, NULL)); | |
| 1da177e4 LT |
407 | return hwif->ide_dma_off_quietly(drive); |
| 408 | } | |
| 409 | /* IORDY not supported */ | |
| 410 | return 0; | |
| 411 | } | |
| 412 | ||
| 413 | /** | |
| 414 | * init_chipset_piix - set up the PIIX chipset | |
| 415 | * @dev: PCI device to set up | |
| 416 | * @name: Name of the device | |
| 417 | * | |
| 418 | * Initialize the PCI device as required. For the PIIX this turns | |
| 419 | * out to be nice and simple | |
| 420 | */ | |
| 421 | ||
| 422 | static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name) | |
| 423 | { | |
| 424 | switch(dev->device) { | |
| 425 | case PCI_DEVICE_ID_INTEL_82801EB_1: | |
| 426 | case PCI_DEVICE_ID_INTEL_82801AA_1: | |
| 427 | case PCI_DEVICE_ID_INTEL_82801AB_1: | |
| 428 | case PCI_DEVICE_ID_INTEL_82801BA_8: | |
| 429 | case PCI_DEVICE_ID_INTEL_82801BA_9: | |
| 430 | case PCI_DEVICE_ID_INTEL_82801CA_10: | |
| 431 | case PCI_DEVICE_ID_INTEL_82801CA_11: | |
| 432 | case PCI_DEVICE_ID_INTEL_82801DB_1: | |
| 433 | case PCI_DEVICE_ID_INTEL_82801DB_10: | |
| 434 | case PCI_DEVICE_ID_INTEL_82801DB_11: | |
| 435 | case PCI_DEVICE_ID_INTEL_82801EB_11: | |
| 436 | case PCI_DEVICE_ID_INTEL_82801E_11: | |
| 437 | case PCI_DEVICE_ID_INTEL_ESB_2: | |
| 438 | case PCI_DEVICE_ID_INTEL_ICH6_19: | |
| 439 | case PCI_DEVICE_ID_INTEL_ICH7_21: | |
| d69332b8 | 440 | case PCI_DEVICE_ID_INTEL_ESB2_18: |
| b7bed9ec | 441 | case PCI_DEVICE_ID_INTEL_ICH8_6: |
| 1da177e4 LT |
442 | { |
| 443 | unsigned int extra = 0; | |
| 444 | pci_read_config_dword(dev, 0x54, &extra); | |
| 445 | pci_write_config_dword(dev, 0x54, extra|0x400); | |
| 446 | } | |
| 447 | default: | |
| 448 | break; | |
| 449 | } | |
| 450 | ||
| 451 | return 0; | |
| 452 | } | |
| 453 | ||
| 454 | /** | |
| 455 | * init_hwif_piix - fill in the hwif for the PIIX | |
| 456 | * @hwif: IDE interface | |
| 457 | * | |
| 458 | * Set up the ide_hwif_t for the PIIX interface according to the | |
| 459 | * capabilities of the hardware. | |
| 460 | */ | |
| 461 | ||
| 462 | static void __devinit init_hwif_piix(ide_hwif_t *hwif) | |
| 463 | { | |
| 464 | u8 reg54h = 0, reg55h = 0, ata66 = 0; | |
| 465 | u8 mask = hwif->channel ? 0xc0 : 0x30; | |
| 466 | ||
| 467 | #ifndef CONFIG_IA64 | |
| 468 | if (!hwif->irq) | |
| 469 | hwif->irq = hwif->channel ? 15 : 14; | |
| 470 | #endif /* CONFIG_IA64 */ | |
| 471 | ||
| 472 | if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) { | |
| 473 | /* This is a painful system best to let it self tune for now */ | |
| 474 | return; | |
| 475 | } | |
| ee2f344b AC |
476 | /* ESB2 appears to generate spurious DMA interrupts in PIO mode |
| 477 | when in native mode */ | |
| 478 | if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_ESB2_18) | |
| 479 | hwif->atapi_irq_bogon = 1; | |
| 1da177e4 LT |
480 | |
| 481 | hwif->autodma = 0; | |
| 482 | hwif->tuneproc = &piix_tune_drive; | |
| 483 | hwif->speedproc = &piix_tune_chipset; | |
| 484 | hwif->drives[0].autotune = 1; | |
| 485 | hwif->drives[1].autotune = 1; | |
| 486 | ||
| 487 | if (!hwif->dma_base) | |
| 488 | return; | |
| 489 | ||
| 490 | hwif->atapi_dma = 1; | |
| 491 | hwif->ultra_mask = 0x3f; | |
| 492 | hwif->mwdma_mask = 0x06; | |
| 493 | hwif->swdma_mask = 0x04; | |
| 494 | ||
| 495 | switch(hwif->pci_dev->device) { | |
| 496 | case PCI_DEVICE_ID_INTEL_82371MX: | |
| 497 | hwif->mwdma_mask = 0x80; | |
| 498 | hwif->swdma_mask = 0x80; | |
| 499 | case PCI_DEVICE_ID_INTEL_82371FB_0: | |
| 500 | case PCI_DEVICE_ID_INTEL_82371FB_1: | |
| 501 | case PCI_DEVICE_ID_INTEL_82371SB_1: | |
| 502 | hwif->ultra_mask = 0x80; | |
| 503 | break; | |
| 504 | case PCI_DEVICE_ID_INTEL_82371AB: | |
| 505 | case PCI_DEVICE_ID_INTEL_82443MX_1: | |
| 506 | case PCI_DEVICE_ID_INTEL_82451NX: | |
| 507 | case PCI_DEVICE_ID_INTEL_82801AB_1: | |
| 508 | hwif->ultra_mask = 0x07; | |
| 509 | break; | |
| 510 | default: | |
| 511 | pci_read_config_byte(hwif->pci_dev, 0x54, ®54h); | |
| 512 | pci_read_config_byte(hwif->pci_dev, 0x55, ®55h); | |
| 513 | ata66 = (reg54h & mask) ? 1 : 0; | |
| 514 | break; | |
| 515 | } | |
| 516 | ||
| 517 | if (!(hwif->udma_four)) | |
| 518 | hwif->udma_four = ata66; | |
| 519 | hwif->ide_dma_check = &piix_config_drive_xfer_rate; | |
| 520 | if (!noautodma) | |
| 521 | hwif->autodma = 1; | |
| 522 | ||
| 523 | hwif->drives[1].autodma = hwif->autodma; | |
| 524 | hwif->drives[0].autodma = hwif->autodma; | |
| 525 | } | |
| 526 | ||
| 527 | #define DECLARE_PIIX_DEV(name_str) \ | |
| 528 | { \ | |
| 529 | .name = name_str, \ | |
| 530 | .init_chipset = init_chipset_piix, \ | |
| 531 | .init_hwif = init_hwif_piix, \ | |
| 532 | .channels = 2, \ | |
| 533 | .autodma = AUTODMA, \ | |
| 534 | .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \ | |
| 535 | .bootable = ON_BOARD, \ | |
| 536 | } | |
| 537 | ||
| 538 | static ide_pci_device_t piix_pci_info[] __devinitdata = { | |
| 539 | /* 0 */ DECLARE_PIIX_DEV("PIIXa"), | |
| 540 | /* 1 */ DECLARE_PIIX_DEV("PIIXb"), | |
| 541 | ||
| 542 | { /* 2 */ | |
| 543 | .name = "MPIIX", | |
| 544 | .init_hwif = init_hwif_piix, | |
| 545 | .channels = 2, | |
| 546 | .autodma = NODMA, | |
| 547 | .enablebits = {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}}, | |
| 548 | .bootable = ON_BOARD, | |
| 549 | }, | |
| 550 | ||
| 551 | /* 3 */ DECLARE_PIIX_DEV("PIIX3"), | |
| 552 | /* 4 */ DECLARE_PIIX_DEV("PIIX4"), | |
| 553 | /* 5 */ DECLARE_PIIX_DEV("ICH0"), | |
| 554 | /* 6 */ DECLARE_PIIX_DEV("PIIX4"), | |
| 555 | /* 7 */ DECLARE_PIIX_DEV("ICH"), | |
| 556 | /* 8 */ DECLARE_PIIX_DEV("PIIX4"), | |
| 557 | /* 9 */ DECLARE_PIIX_DEV("PIIX4"), | |
| 558 | /* 10 */ DECLARE_PIIX_DEV("ICH2"), | |
| 559 | /* 11 */ DECLARE_PIIX_DEV("ICH2M"), | |
| 560 | /* 12 */ DECLARE_PIIX_DEV("ICH3M"), | |
| 561 | /* 13 */ DECLARE_PIIX_DEV("ICH3"), | |
| 562 | /* 14 */ DECLARE_PIIX_DEV("ICH4"), | |
| 563 | /* 15 */ DECLARE_PIIX_DEV("ICH5"), | |
| 564 | /* 16 */ DECLARE_PIIX_DEV("C-ICH"), | |
| 565 | /* 17 */ DECLARE_PIIX_DEV("ICH4"), | |
| 566 | /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"), | |
| 567 | /* 19 */ DECLARE_PIIX_DEV("ICH5"), | |
| 568 | /* 20 */ DECLARE_PIIX_DEV("ICH6"), | |
| 569 | /* 21 */ DECLARE_PIIX_DEV("ICH7"), | |
| 570 | /* 22 */ DECLARE_PIIX_DEV("ICH4"), | |
| d69332b8 | 571 | /* 23 */ DECLARE_PIIX_DEV("ESB2"), |
| b7bed9ec | 572 | /* 24 */ DECLARE_PIIX_DEV("ICH8M"), |
| 1da177e4 LT |
573 | }; |
| 574 | ||
| 575 | /** | |
| 576 | * piix_init_one - called when a PIIX is found | |
| 577 | * @dev: the piix device | |
| 578 | * @id: the matching pci id | |
| 579 | * | |
| 580 | * Called when the PCI registration layer (or the IDE initialization) | |
| 581 | * finds a device matching our IDE device tables. | |
| 582 | */ | |
| 583 | ||
| 584 | static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
| 585 | { | |
| 586 | ide_pci_device_t *d = &piix_pci_info[id->driver_data]; | |
| 587 | ||
| 588 | return ide_setup_pci_device(dev, d); | |
| 589 | } | |
| 590 | ||
| 591 | /** | |
| 592 | * piix_check_450nx - Check for problem 450NX setup | |
| 593 | * | |
| 594 | * Check for the present of 450NX errata #19 and errata #25. If | |
| 595 | * they are found, disable use of DMA IDE | |
| 596 | */ | |
| 597 | ||
| 598 | static void __devinit piix_check_450nx(void) | |
| 599 | { | |
| 600 | struct pci_dev *pdev = NULL; | |
| 601 | u16 cfg; | |
| 602 | u8 rev; | |
| 1424e504 | 603 | while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL) |
| 1da177e4 LT |
604 | { |
| 605 | /* Look for 450NX PXB. Check for problem configurations | |
| 606 | A PCI quirk checks bit 6 already */ | |
| 607 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); | |
| 608 | pci_read_config_word(pdev, 0x41, &cfg); | |
| 609 | /* Only on the original revision: IDE DMA can hang */ | |
| 610 | if(rev == 0x00) | |
| 611 | no_piix_dma = 1; | |
| 612 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
| 613 | else if(cfg & (1<<14) && rev < 5) | |
| 614 | no_piix_dma = 2; | |
| 615 | } | |
| 616 | if(no_piix_dma) | |
| 617 | printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n"); | |
| 618 | if(no_piix_dma == 2) | |
| 619 | printk(KERN_WARNING "piix: A BIOS update may resolve this.\n"); | |
| 620 | } | |
| 621 | ||
| 622 | static struct pci_device_id piix_pci_tbl[] = { | |
| 623 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
| 624 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, | |
| 625 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, | |
| 626 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, | |
| 627 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, | |
| 628 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5}, | |
| 629 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6}, | |
| 630 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7}, | |
| 631 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8}, | |
| 632 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9}, | |
| 633 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10}, | |
| 634 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11}, | |
| 635 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12}, | |
| 636 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13}, | |
| 637 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14}, | |
| 638 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15}, | |
| 639 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16}, | |
| 640 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17}, | |
| 641 | #ifdef CONFIG_BLK_DEV_IDE_SATA | |
| 642 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18}, | |
| 643 | #endif | |
| 644 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19}, | |
| 645 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20}, | |
| 646 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21}, | |
| 647 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22}, | |
| d69332b8 | 648 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23}, |
| b7bed9ec | 649 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 24}, |
| 1da177e4 LT |
650 | { 0, }, |
| 651 | }; | |
| 652 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
| 653 | ||
| 654 | static struct pci_driver driver = { | |
| 655 | .name = "PIIX_IDE", | |
| 656 | .id_table = piix_pci_tbl, | |
| 657 | .probe = piix_init_one, | |
| 658 | }; | |
| 659 | ||
| 660 | static int __init piix_ide_init(void) | |
| 661 | { | |
| 662 | piix_check_450nx(); | |
| 663 | return ide_pci_register_driver(&driver); | |
| 664 | } | |
| 665 | ||
| 666 | module_init(piix_ide_init); | |
| 667 | ||
| 668 | MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz"); | |
| 669 | MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE"); | |
| 670 | MODULE_LICENSE("GPL"); |