[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / piix.c

/*
 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
 *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
 *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
 *
 *  May be copied or modified under the terms of the GNU General Public License
 *
 * Documentation:
 *
 *	Publically available from Intel web site. Errata documentation
 * is also publically available. As an aide to anyone hacking on this
 * driver the list of errata that are relevant is below.going back to
 * PIIX4. Older device documentation is now a bit tricky to find.
 *
 * Errata of note:
 *
 * Unfixable
 *	PIIX4    errata #9	- Only on ultra obscure hw
 *	ICH3	 errata #13     - Not observed to affect real hw
 *				  by Intel
 *
 * Things we must deal with
 *	PIIX4	errata #10	- BM IDE hang with non UDMA
 *				  (must stop/start dma to recover)
 *	440MX   errata #15	- As PIIX4 errata #10
 *	PIIX4	errata #15	- Must not read control registers
 * 				  during a PIO transfer
 *	440MX   errata #13	- As PIIX4 errata #15
 *	ICH2	errata #21	- DMA mode 0 doesn't work right
 *	ICH0/1  errata #55	- As ICH2 errata #21
 *	ICH2	spec c #9	- Extra operations needed to handle
 *				  drive hotswap [NOT YET SUPPORTED]
 *	ICH2    spec c #20	- IDE PRD must not cross a 64K boundary
 *				  and must be dword aligned
 *	ICH2    spec c #24	- UDMA mode 4,5 t85/86 should be 6ns not 3.3
 *
 * Should have been BIOS fixed:
 *	450NX:	errata #19	- DMA hangs on old 450NX
 *	450NX:  errata #20	- DMA hangs on old 450NX
 *	450NX:  errata #25	- Corruption with DMA on old 450NX
 *	ICH3    errata #15      - IDE deadlock under high load
 *				  (BIOS must set dev 31 fn 0 bit 23)
 *	ICH3	errata #18	- Don't use native mode
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

static int no_piix_dma;

/**
 *	piix_set_pio_mode	-	set host controller for PIO mode
 *	@drive: drive
 *	@pio: PIO mode number
 *
 *	Set the interface PIO mode based upon the settings done by AMI BIOS.
 */

static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	int is_slave		= drive->dn & 1;
	int master_port		= hwif->channel ? 0x42 : 0x40;
	int slave_port		= 0x44;
	unsigned long flags;
	u16 master_data;
	u8 slave_data;
	static DEFINE_SPINLOCK(tune_lock);
	int control = 0;

				     /* ISP  RTC */
	static const u8 timings[][2]= {
					{ 0, 0 },
					{ 0, 0 },
					{ 1, 0 },
					{ 2, 1 },
					{ 2, 3 }, };

	/*
	 * Master vs slave is synchronized above us but the slave register is
	 * shared by the two hwifs so the corner case of two slave timeouts in
	 * parallel must be locked.
	 */
	spin_lock_irqsave(&tune_lock, flags);
	pci_read_config_word(dev, master_port, &master_data);

	if (pio > 1)
		control |= 1;	/* Programmable timing on */
	if (drive->media == ide_disk)
		control |= 4;	/* Prefetch, post write */
	if (pio > 2)
		control |= 2;	/* IORDY */
	if (is_slave) {
		master_data |=  0x4000;
		master_data &= ~0x0070;
		if (pio > 1) {
			/* Set PPE, IE and TIME */
			master_data |= control << 4;
		}
		pci_read_config_byte(dev, slave_port, &slave_data);
		slave_data &= hwif->channel ? 0x0f : 0xf0;
		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
			       (hwif->channel ? 4 : 0);
	} else {
		master_data &= ~0x3307;
		if (pio > 1) {
			/* enable PPE, IE and TIME */
			master_data |= control;
		}
		master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
	}
	pci_write_config_word(dev, master_port, master_data);
	if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
	spin_unlock_irqrestore(&tune_lock, flags);
}

/**
 *	piix_set_dma_mode	-	set host controller for DMA mode
 *	@drive: drive
 *	@speed: DMA mode
 *
 *	Set a PIIX host controller to the desired DMA mode.  This involves
 *	programming the right timing data into the PCI configuration space.
 */

static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 maslave		= hwif->channel ? 0x42 : 0x40;
	int a_speed		= 3 << (drive->dn * 4);
	int u_flag		= 1 << drive->dn;
	int v_flag		= 0x01 << drive->dn;
	int w_flag		= 0x10 << drive->dn;
	int u_speed		= 0;
	int			sitre;
	u16			reg4042, reg4a;
	u8			reg48, reg54, reg55;

	pci_read_config_word(dev, maslave, &reg4042);
	sitre = (reg4042 & 0x4000) ? 1 : 0;
	pci_read_config_byte(dev, 0x48, &reg48);
	pci_read_config_word(dev, 0x4a, &reg4a);
	pci_read_config_byte(dev, 0x54, &reg54);
	pci_read_config_byte(dev, 0x55, &reg55);

	if (speed >= XFER_UDMA_0) {
		u8 udma = speed - XFER_UDMA_0;

		u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);

		if (!(reg48 & u_flag))
			pci_write_config_byte(dev, 0x48, reg48 | u_flag);
		if (speed == XFER_UDMA_5) {
			pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
		} else {
			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
		}
		if ((reg4a & a_speed) != u_speed)
			pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
		if (speed > XFER_UDMA_2) {
			if (!(reg54 & v_flag))
				pci_write_config_byte(dev, 0x54, reg54 | v_flag);
		} else
			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	} else {
		const u8 mwdma_to_pio[] = { 0, 3, 4 };
		u8 pio;

		if (reg48 & u_flag)
			pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
		if (reg4a & a_speed)
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
		if (reg54 & v_flag)
			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
		if (reg55 & w_flag)
			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);

		if (speed >= XFER_MW_DMA_0)
			pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
		else
			pio = 2; /* only SWDMA2 is allowed */

		piix_set_pio_mode(drive, pio);
	}
}

/**
 *	init_chipset_ich	-	set up the ICH chipset
 *	@dev: PCI device to set up
 *	@name: Name of the device
 *
 *	Initialize the PCI device as required.  For the ICH this turns
 *	out to be nice and simple.
 */

static unsigned int __devinit init_chipset_ich(struct pci_dev *dev, const char *name)
{
	u32 extra = 0;

	pci_read_config_dword(dev, 0x54, &extra);
	pci_write_config_dword(dev, 0x54, extra | 0x400);

	return 0;
}

/**
 *	piix_dma_clear_irq	-	clear BMDMA status
 *	@drive: IDE drive to clear
 *
 *	Called from ide_intr() for PIO interrupts
 *	to clear BMDMA status as needed by ICHx
 */
static void piix_dma_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	u8 dma_stat;

	/* clear the INTR & ERROR bits */
	dma_stat = inb(hwif->dma_status);
	/* Should we force the bit as well ? */
	outb(dma_stat, hwif->dma_status);
}

struct ich_laptop {
	u16 device;
	u16 subvendor;
	u16 subdevice;
};

/*
 *	List of laptops that use short cables rather than 80 wire
 */

static const struct ich_laptop ich_laptop[] = {
	/* devid, subvendor, subdev */
	{ 0x27DF, 0x1025, 0x0102 },	/* ICH7 on Acer 5602aWLMi */
	{ 0x27DF, 0x0005, 0x0280 },	/* ICH7 on Acer 5602WLMi */
	{ 0x27DF, 0x1025, 0x0110 },	/* ICH7 on Acer 3682WLMi */
	{ 0x27DF, 0x1043, 0x1267 },	/* ICH7 on Asus W5F */
	{ 0x27DF, 0x103C, 0x30A1 },	/* ICH7 on HP Compaq nc2400 */
	{ 0x24CA, 0x1025, 0x0061 },	/* ICH4 on Acer Aspire 2023WLMi */
	/* end marker */
	{ 0, }
};

static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	const struct ich_laptop *lap = &ich_laptop[0];
	u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;

	/* check for specials */
	while (lap->device) {
		if (lap->device == pdev->device &&
		    lap->subvendor == pdev->subsystem_vendor &&
		    lap->subdevice == pdev->subsystem_device) {
			return ATA_CBL_PATA40_SHORT;
		}
		lap++;
	}

	pci_read_config_byte(pdev, 0x54, &reg54h);

	return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
}

/**
 *	init_hwif_piix		-	fill in the hwif for the PIIX
 *	@hwif: IDE interface
 *
 *	Set up the ide_hwif_t for the PIIX interface according to the
 *	capabilities of the hardware.
 */

static void __devinit init_hwif_piix(ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &piix_set_pio_mode;
	hwif->set_dma_mode = &piix_set_dma_mode;

	hwif->cable_detect = piix_cable_detect;

	if (!hwif->dma_base)
		return;

	if (no_piix_dma)
		hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
}

static void __devinit init_hwif_ich(ide_hwif_t *hwif)
{
	init_hwif_piix(hwif);

	/* ICHx need to clear the BMDMA status for all interrupts */
	if (hwif->dma_base)
		hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
}

#ifndef CONFIG_IA64
 #define IDE_HFLAGS_PIIX IDE_HFLAG_LEGACY_IRQS
#else
 #define IDE_HFLAGS_PIIX 0
#endif

#define DECLARE_PIIX_DEV(name_str, udma) \
	{						\
		.name		= name_str,		\
		.init_hwif	= init_hwif_piix,	\
		.enablebits	= {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
		.host_flags	= IDE_HFLAGS_PIIX,	\
		.pio_mask	= ATA_PIO4,		\
		.swdma_mask	= ATA_SWDMA2_ONLY,	\
		.mwdma_mask	= ATA_MWDMA12_ONLY,	\
		.udma_mask	= udma,			\
	}

#define DECLARE_ICH_DEV(name_str, udma) \
	{ \
		.name		= name_str, \
		.init_chipset	= init_chipset_ich, \
		.init_hwif	= init_hwif_ich, \
		.enablebits	= {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
		.host_flags	= IDE_HFLAGS_PIIX, \
		.pio_mask	= ATA_PIO4, \
		.swdma_mask	= ATA_SWDMA2_ONLY, \
		.mwdma_mask	= ATA_MWDMA12_ONLY, \
		.udma_mask	= udma, \
	}

static const struct ide_port_info piix_pci_info[] __devinitdata = {
	/*  0 */ DECLARE_PIIX_DEV("PIIXa",	0x00),	/* no udma */
	/*  1 */ DECLARE_PIIX_DEV("PIIXb",	0x00),	/* no udma */

	/*  2 */
	{	/*
		 * MPIIX actually has only a single IDE channel mapped to
		 * the primary or secondary ports depending on the value
		 * of the bit 14 of the IDETIM register at offset 0x6c
		 */
		.name		= "MPIIX",
		.enablebits	= {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
		.host_flags	= IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA |
				  IDE_HFLAGS_PIIX,
		.pio_mask	= ATA_PIO4,
		/* This is a painful system best to let it self tune for now */
	},

	/*  3 */ DECLARE_PIIX_DEV("PIIX3",	0x00),	/* no udma */
	/*  4 */ DECLARE_PIIX_DEV("PIIX4",	ATA_UDMA2),
	/*  5 */ DECLARE_ICH_DEV("ICH0",	ATA_UDMA2),
	/*  6 */ DECLARE_PIIX_DEV("PIIX4",	ATA_UDMA2),
	/*  7 */ DECLARE_ICH_DEV("ICH",		ATA_UDMA4),
	/*  8 */ DECLARE_PIIX_DEV("PIIX4",	ATA_UDMA4),
	/*  9 */ DECLARE_PIIX_DEV("PIIX4",	ATA_UDMA2),
	/* 10 */ DECLARE_ICH_DEV("ICH2",	ATA_UDMA5),
	/* 11 */ DECLARE_ICH_DEV("ICH2M",	ATA_UDMA5),
	/* 12 */ DECLARE_ICH_DEV("ICH3M",	ATA_UDMA5),
	/* 13 */ DECLARE_ICH_DEV("ICH3",	ATA_UDMA5),
	/* 14 */ DECLARE_ICH_DEV("ICH4",	ATA_UDMA5),
	/* 15 */ DECLARE_ICH_DEV("ICH5",	ATA_UDMA5),
	/* 16 */ DECLARE_ICH_DEV("C-ICH",	ATA_UDMA5),
	/* 17 */ DECLARE_ICH_DEV("ICH4",	ATA_UDMA5),
	/* 18 */ DECLARE_ICH_DEV("ICH5-SATA",	ATA_UDMA5),
	/* 19 */ DECLARE_ICH_DEV("ICH5",	ATA_UDMA5),
	/* 20 */ DECLARE_ICH_DEV("ICH6",	ATA_UDMA5),
	/* 21 */ DECLARE_ICH_DEV("ICH7",	ATA_UDMA5),
	/* 22 */ DECLARE_ICH_DEV("ICH4",	ATA_UDMA5),
	/* 23 */ DECLARE_ICH_DEV("ESB2",	ATA_UDMA5),
	/* 24 */ DECLARE_ICH_DEV("ICH8M",	ATA_UDMA5),
};

/**
 *	piix_init_one	-	called when a PIIX is found
 *	@dev: the piix device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &piix_pci_info[id->driver_data]);
}

/**
 *	piix_check_450nx	-	Check for problem 450NX setup
 *	
 *	Check for the present of 450NX errata #19 and errata #25. If
 *	they are found, disable use of DMA IDE
 */

static void __devinit piix_check_450nx(void)
{
	struct pci_dev *pdev = NULL;
	u16 cfg;
	while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
	{
		/* Look for 450NX PXB. Check for problem configurations
		   A PCI quirk checks bit 6 already */
		pci_read_config_word(pdev, 0x41, &cfg);
		/* Only on the original revision: IDE DMA can hang */
		if (pdev->revision == 0x00)
			no_piix_dma = 1;
		/* On all revisions below 5 PXB bus lock must be disabled for IDE */
		else if (cfg & (1<<14) && pdev->revision < 5)
			no_piix_dma = 2;
	}
	if(no_piix_dma)
		printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
	if(no_piix_dma == 2)
		printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
}		

static const struct pci_device_id piix_pci_tbl[] = {
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0),   0 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1),   1 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX),     2 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1),   3 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB),     4 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1),   5 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1),   6 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1),   7 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1),   8 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX),     9 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9),  10 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8),  11 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 12 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 13 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 14 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 15 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11),  16 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 17 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1),  18 },
#endif
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2),      19 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19),    20 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21),    21 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1),  22 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18),    23 },
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6),     24 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);

static struct pci_driver driver = {
	.name		= "PIIX_IDE",
	.id_table	= piix_pci_tbl,
	.probe		= piix_init_one,
};

static int __init piix_ide_init(void)
{
	piix_check_450nx();
	return ide_pci_register_driver(&driver);
}

module_init(piix_ide_init);

MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
	3	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
	4	* Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
07af4276	5	* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	6	*
	7	* May be copied or modified under the terms of the GNU General Public License
	8	*
2be564b0	9	* Documentation:
1da177e4	10	*
1da177e4 LT	11	* Publically available from Intel web site. Errata documentation
	12	* is also publically available. As an aide to anyone hacking on this
	13	* driver the list of errata that are relevant is below.going back to
	14	* PIIX4. Older device documentation is now a bit tricky to find.
	15	*
	16	* Errata of note:
	17	*
	18	* Unfixable
	19	* PIIX4 errata #9 - Only on ultra obscure hw
	20	* ICH3 errata #13 - Not observed to affect real hw
	21	* by Intel
	22	*
	23	* Things we must deal with
	24	* PIIX4 errata #10 - BM IDE hang with non UDMA
	25	* (must stop/start dma to recover)
	26	* 440MX errata #15 - As PIIX4 errata #10
	27	* PIIX4 errata #15 - Must not read control registers
	28	* during a PIO transfer
	29	* 440MX errata #13 - As PIIX4 errata #15
	30	* ICH2 errata #21 - DMA mode 0 doesn't work right
	31	* ICH0/1 errata #55 - As ICH2 errata #21
	32	* ICH2 spec c #9 - Extra operations needed to handle
	33	* drive hotswap [NOT YET SUPPORTED]
	34	* ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
	35	* and must be dword aligned
	36	* ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
	37	*
	38	* Should have been BIOS fixed:
	39	* 450NX: errata #19 - DMA hangs on old 450NX
	40	* 450NX: errata #20 - DMA hangs on old 450NX
	41	* 450NX: errata #25 - Corruption with DMA on old 450NX
	42	* ICH3 errata #15 - IDE deadlock under high load
	43	* (BIOS must set dev 31 fn 0 bit 23)
	44	* ICH3 errata #18 - Don't use native mode
	45	*/
	46
1da177e4 LT	47	#include <linux/types.h>
	48	#include <linux/module.h>
	49	#include <linux/kernel.h>
1da177e4 LT	50	#include <linux/pci.h>
	51	#include <linux/hdreg.h>
	52	#include <linux/ide.h>
1da177e4 LT	53	#include <linux/init.h>
	54
	55	#include <asm/io.h>
	56
	57	static int no_piix_dma;
	58
1da177e4	59	/**
88b2b32b BZ	60	* piix_set_pio_mode - set host controller for PIO mode
	61	* @drive: drive
	62	* @pio: PIO mode number
1da177e4	63	*
07af4276	64	* Set the interface PIO mode based upon the settings done by AMI BIOS.
1da177e4	65	*/
88b2b32b BZ	66
88b2b32b BZ	67	static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4 LT	68	{
1da177e4 LT	69	ide_hwif_t *hwif = HWIF(drive);
36501650	70	struct pci_dev *dev = to_pci_dev(hwif->dev);
30dfd12f	71	int is_slave = drive->dn & 1;
1da177e4 LT	72	int master_port = hwif->channel ? 0x42 : 0x40;
	73	int slave_port = 0x44;
	74	unsigned long flags;
	75	u16 master_data;
	76	u8 slave_data;
4fb0f76d	77	static DEFINE_SPINLOCK(tune_lock);
5ac24697	78	int control = 0;
4fb0f76d	79
30dfd12f	80	/* ISP RTC */
5ac24697 AC	81	static const u8 timings[][2]= {
	82	{ 0, 0 },
	83	{ 0, 0 },
	84	{ 1, 0 },
	85	{ 2, 1 },
	86	{ 2, 3 }, };
1da177e4	87
4fb0f76d AC	88	/*
	89	* Master vs slave is synchronized above us but the slave register is
	90	* shared by the two hwifs so the corner case of two slave timeouts in
	91	* parallel must be locked.
	92	*/
	93	spin_lock_irqsave(&tune_lock, flags);
1da177e4	94	pci_read_config_word(dev, master_port, &master_data);
5ac24697	95
30dfd12f	96	if (pio > 1)
5ac24697 AC	97	control \|= 1; /* Programmable timing on */
	98	if (drive->media == ide_disk)
	99	control \|= 4; /* Prefetch, post write */
30dfd12f	100	if (pio > 2)
5ac24697	101	control \|= 2; /* IORDY */
1da177e4	102	if (is_slave) {
30dfd12f SS	103	master_data \|= 0x4000;
30dfd12f SS	104	master_data &= ~0x0070;
5ac24697	105	if (pio > 1) {
07af4276 SS	106	/* Set PPE, IE and TIME */
07af4276 SS	107	master_data \|= control << 4;
5ac24697	108	}
1da177e4	109	pci_read_config_byte(dev, slave_port, &slave_data);
07af4276 SS	110	slave_data &= hwif->channel ? 0x0f : 0xf0;
	111	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) <<
	112	(hwif->channel ? 4 : 0);
1da177e4	113	} else {
30dfd12f	114	master_data &= ~0x3307;
5ac24697	115	if (pio > 1) {
1da177e4	116	/* enable PPE, IE and TIME */
07af4276	117	master_data \|= control;
5ac24697	118	}
07af4276	119	master_data \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
1da177e4 LT	120	}
	121	pci_write_config_word(dev, master_port, master_data);
	122	if (is_slave)
	123	pci_write_config_byte(dev, slave_port, slave_data);
4fb0f76d	124	spin_unlock_irqrestore(&tune_lock, flags);
1da177e4 LT	125	}
1da177e4 LT	126
07af4276	127	/**
88b2b32b BZ	128	* piix_set_dma_mode - set host controller for DMA mode
	129	* @drive: drive
	130	* @speed: DMA mode
1da177e4	131	*
88b2b32b BZ	132	* Set a PIIX host controller to the desired DMA mode. This involves
88b2b32b BZ	133	* programming the right timing data into the PCI configuration space.
1da177e4	134	*/
f212ff28	135
88b2b32b	136	static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	137	{
1da177e4 LT	138	ide_hwif_t *hwif = HWIF(drive);
36501650	139	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	140	u8 maslave = hwif->channel ? 0x42 : 0x40;
1da177e4 LT	141	int a_speed = 3 << (drive->dn * 4);
	142	int u_flag = 1 << drive->dn;
	143	int v_flag = 0x01 << drive->dn;
	144	int w_flag = 0x10 << drive->dn;
	145	int u_speed = 0;
	146	int sitre;
	147	u16 reg4042, reg4a;
1c54a93d	148	u8 reg48, reg54, reg55;
1da177e4 LT	149
	150	pci_read_config_word(dev, maslave, &reg4042);
	151	sitre = (reg4042 & 0x4000) ? 1 : 0;
	152	pci_read_config_byte(dev, 0x48, &reg48);
	153	pci_read_config_word(dev, 0x4a, &reg4a);
	154	pci_read_config_byte(dev, 0x54, &reg54);
	155	pci_read_config_byte(dev, 0x55, &reg55);
	156
1da177e4	157	if (speed >= XFER_UDMA_0) {
4db90a14 BZ	158	u8 udma = speed - XFER_UDMA_0;
	159
	160	u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
	161
1da177e4 LT	162	if (!(reg48 & u_flag))
	163	pci_write_config_byte(dev, 0x48, reg48 \| u_flag);
	164	if (speed == XFER_UDMA_5) {
	165	pci_write_config_byte(dev, 0x55, (u8) reg55\|w_flag);
	166	} else {
	167	pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
	168	}
	169	if ((reg4a & a_speed) != u_speed)
	170	pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) \| u_speed);
	171	if (speed > XFER_UDMA_2) {
	172	if (!(reg54 & v_flag))
	173	pci_write_config_byte(dev, 0x54, reg54 \| v_flag);
	174	} else
	175	pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	176	} else {
8c91abf8	177	const u8 mwdma_to_pio[] = { 0, 3, 4 };
1c54a93d	178	u8 pio;
8c91abf8	179
1da177e4 LT	180	if (reg48 & u_flag)
	181	pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
	182	if (reg4a & a_speed)
	183	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
	184	if (reg54 & v_flag)
	185	pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	186	if (reg55 & w_flag)
	187	pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
8c91abf8 BZ	188
	189	if (speed >= XFER_MW_DMA_0)
	190	pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
	191	else
	192	pio = 2; /* only SWDMA2 is allowed */
1da177e4	193
1c54a93d BZ	194	piix_set_pio_mode(drive, pio);
1c54a93d BZ	195	}
1da177e4 LT	196	}
1da177e4 LT	197
1da177e4	198	/**
40d2dd7e	199	* init_chipset_ich - set up the ICH chipset
f0dd8712 AL	200	* @dev: PCI device to set up
	201	* @name: Name of the device
	202	*
40d2dd7e BZ	203	* Initialize the PCI device as required. For the ICH this turns
40d2dd7e BZ	204	* out to be nice and simple.
f0dd8712 AL	205	*/
f0dd8712 AL	206
40d2dd7e	207	static unsigned int __devinit init_chipset_ich(struct pci_dev dev, const char name)
f0dd8712	208	{
40d2dd7e BZ	209	u32 extra = 0;
	210
	211	pci_read_config_dword(dev, 0x54, &extra);
	212	pci_write_config_dword(dev, 0x54, extra \| 0x400);
f0dd8712 AL	213
	214	return 0;
	215	}
	216
	217	/**
	218	* piix_dma_clear_irq - clear BMDMA status
	219	* @drive: IDE drive to clear
	220	*
	221	* Called from ide_intr() for PIO interrupts
	222	* to clear BMDMA status as needed by ICHx
	223	*/
	224	static void piix_dma_clear_irq(ide_drive_t *drive)
	225	{
	226	ide_hwif_t *hwif = HWIF(drive);
	227	u8 dma_stat;
	228
	229	/* clear the INTR & ERROR bits */
31e8a465	230	dma_stat = inb(hwif->dma_status);
f0dd8712	231	/* Should we force the bit as well ? */
31e8a465	232	outb(dma_stat, hwif->dma_status);
f0dd8712 AL	233	}
f0dd8712 AL	234
7207626f BZ	235	struct ich_laptop {
	236	u16 device;
	237	u16 subvendor;
	238	u16 subdevice;
	239	};
	240
	241	/*
	242	* List of laptops that use short cables rather than 80 wire
	243	*/
	244
	245	static const struct ich_laptop ich_laptop[] = {
	246	/* devid, subvendor, subdev */
afda5e4d	247	{ 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
7207626f BZ	248	{ 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
	249	{ 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
	250	{ 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
dd0fd40d	251	{ 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
7207626f BZ	252	{ 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
	253	/* end marker */
	254	{ 0, }
	255	};
	256
49521f97	257	static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
74594fd1	258	{
36501650	259	struct pci_dev *pdev = to_pci_dev(hwif->dev);
7207626f	260	const struct ich_laptop *lap = &ich_laptop[0];
74594fd1 BZ	261	u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
74594fd1 BZ	262
7207626f BZ	263	/* check for specials */
	264	while (lap->device) {
	265	if (lap->device == pdev->device &&
	266	lap->subvendor == pdev->subsystem_vendor &&
	267	lap->subdevice == pdev->subsystem_device) {
	268	return ATA_CBL_PATA40_SHORT;
	269	}
	270	lap++;
	271	}
	272
	273	pci_read_config_byte(pdev, 0x54, &reg54h);
74594fd1	274
49521f97	275	return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
74594fd1 BZ	276	}
74594fd1 BZ	277
1da177e4 LT	278	/**
	279	* init_hwif_piix - fill in the hwif for the PIIX
	280	* @hwif: IDE interface
	281	*
	282	* Set up the ide_hwif_t for the PIIX interface according to the
	283	* capabilities of the hardware.
	284	*/
	285
	286	static void __devinit init_hwif_piix(ide_hwif_t *hwif)
	287	{
26bcb879	288	hwif->set_pio_mode = &piix_set_pio_mode;
88b2b32b BZ	289	hwif->set_dma_mode = &piix_set_dma_mode;
88b2b32b BZ	290
bfa14b42 BZ	291	hwif->cable_detect = piix_cable_detect;
bfa14b42 BZ	292
1da177e4 LT	293	if (!hwif->dma_base)
	294	return;
	295
74594fd1 BZ	296	if (no_piix_dma)
74594fd1 BZ	297	hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
1da177e4 LT	298	}
1da177e4 LT	299
40d2dd7e BZ	300	static void __devinit init_hwif_ich(ide_hwif_t *hwif)
	301	{
	302	init_hwif_piix(hwif);
	303
	304	/* ICHx need to clear the BMDMA status for all interrupts */
	305	if (hwif->dma_base)
	306	hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
	307	}
	308
3985ee3b	309	#ifndef CONFIG_IA64
5e71d9c5	310	#define IDE_HFLAGS_PIIX IDE_HFLAG_LEGACY_IRQS
3985ee3b	311	#else
5e71d9c5	312	#define IDE_HFLAGS_PIIX 0
3985ee3b BZ	313	#endif
3985ee3b BZ	314
18137207	315	#define DECLARE_PIIX_DEV(name_str, udma) \
1da177e4 LT	316	{ \
1da177e4 LT	317	.name = name_str, \
1da177e4	318	.init_hwif = init_hwif_piix, \
1da177e4	319	.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
3985ee3b	320	.host_flags = IDE_HFLAGS_PIIX, \
4099d143	321	.pio_mask = ATA_PIO4, \
5f8b6c34 BZ	322	.swdma_mask = ATA_SWDMA2_ONLY, \
5f8b6c34 BZ	323	.mwdma_mask = ATA_MWDMA12_ONLY, \
18137207	324	.udma_mask = udma, \
1da177e4 LT	325	}
1da177e4 LT	326
40d2dd7e BZ	327	#define DECLARE_ICH_DEV(name_str, udma) \
	328	{ \
	329	.name = name_str, \
	330	.init_chipset = init_chipset_ich, \
	331	.init_hwif = init_hwif_ich, \
	332	.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
3985ee3b	333	.host_flags = IDE_HFLAGS_PIIX, \
40d2dd7e BZ	334	.pio_mask = ATA_PIO4, \
	335	.swdma_mask = ATA_SWDMA2_ONLY, \
	336	.mwdma_mask = ATA_MWDMA12_ONLY, \
	337	.udma_mask = udma, \
	338	}
	339
85620436	340	static const struct ide_port_info piix_pci_info[] __devinitdata = {
5f8b6c34 BZ	341	/* 0 / DECLARE_PIIX_DEV("PIIXa", 0x00), / no udma */
5f8b6c34 BZ	342	/* 1 / DECLARE_PIIX_DEV("PIIXb", 0x00), / no udma */
1da177e4	343
d2872239 SS	344	/* 2 */
	345	{ /*
	346	* MPIIX actually has only a single IDE channel mapped to
	347	* the primary or secondary ports depending on the value
	348	* of the bit 14 of the IDETIM register at offset 0x6c
	349	*/
1da177e4	350	.name = "MPIIX",
d2872239	351	.enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
47b68788	352	.host_flags = IDE_HFLAG_ISA_PORTS \| IDE_HFLAG_NO_DMA \|
3985ee3b	353	IDE_HFLAGS_PIIX,
4099d143	354	.pio_mask = ATA_PIO4,
3985ee3b	355	/* This is a painful system best to let it self tune for now */
1da177e4 LT	356	},
1da177e4 LT	357
5f8b6c34 BZ	358	/* 3 / DECLARE_PIIX_DEV("PIIX3", 0x00), / no udma */
5f8b6c34 BZ	359	/* 4 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
40d2dd7e	360	/* 5 */ DECLARE_ICH_DEV("ICH0", ATA_UDMA2),
5f8b6c34	361	/* 6 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
40d2dd7e	362	/* 7 */ DECLARE_ICH_DEV("ICH", ATA_UDMA4),
5f8b6c34 BZ	363	/* 8 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA4),
5f8b6c34 BZ	364	/* 9 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
40d2dd7e BZ	365	/* 10 */ DECLARE_ICH_DEV("ICH2", ATA_UDMA5),
	366	/* 11 */ DECLARE_ICH_DEV("ICH2M", ATA_UDMA5),
	367	/* 12 */ DECLARE_ICH_DEV("ICH3M", ATA_UDMA5),
	368	/* 13 */ DECLARE_ICH_DEV("ICH3", ATA_UDMA5),
	369	/* 14 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
	370	/* 15 */ DECLARE_ICH_DEV("ICH5", ATA_UDMA5),
	371	/* 16 */ DECLARE_ICH_DEV("C-ICH", ATA_UDMA5),
	372	/* 17 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
	373	/* 18 */ DECLARE_ICH_DEV("ICH5-SATA", ATA_UDMA5),
	374	/* 19 */ DECLARE_ICH_DEV("ICH5", ATA_UDMA5),
	375	/* 20 */ DECLARE_ICH_DEV("ICH6", ATA_UDMA5),
	376	/* 21 */ DECLARE_ICH_DEV("ICH7", ATA_UDMA5),
	377	/* 22 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
	378	/* 23 */ DECLARE_ICH_DEV("ESB2", ATA_UDMA5),
	379	/* 24 */ DECLARE_ICH_DEV("ICH8M", ATA_UDMA5),
1da177e4 LT	380	};
	381
	382	/**
	383	* piix_init_one - called when a PIIX is found
	384	* @dev: the piix device
	385	* @id: the matching pci id
	386	*
	387	* Called when the PCI registration layer (or the IDE initialization)
	388	* finds a device matching our IDE device tables.
	389	*/
	390
	391	static int __devinit piix_init_one(struct pci_dev dev, const struct pci_device_id id)
	392	{
039788e1	393	return ide_setup_pci_device(dev, &piix_pci_info[id->driver_data]);
1da177e4 LT	394	}
	395
	396	/**
	397	* piix_check_450nx - Check for problem 450NX setup
	398	*
	399	* Check for the present of 450NX errata #19 and errata #25. If
	400	* they are found, disable use of DMA IDE
	401	*/
	402
	403	static void __devinit piix_check_450nx(void)
	404	{
	405	struct pci_dev *pdev = NULL;
	406	u16 cfg;
1424e504	407	while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
1da177e4 LT	408	{
	409	/* Look for 450NX PXB. Check for problem configurations
	410	A PCI quirk checks bit 6 already */
1da177e4 LT	411	pci_read_config_word(pdev, 0x41, &cfg);
1da177e4 LT	412	/* Only on the original revision: IDE DMA can hang */
44c10138	413	if (pdev->revision == 0x00)
1da177e4 LT	414	no_piix_dma = 1;
1da177e4 LT	415	/* On all revisions below 5 PXB bus lock must be disabled for IDE */
44c10138	416	else if (cfg & (1<<14) && pdev->revision < 5)
1da177e4 LT	417	no_piix_dma = 2;
	418	}
	419	if(no_piix_dma)
	420	printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
	421	if(no_piix_dma == 2)
	422	printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
	423	}
	424
9cbcc5e3 BZ	425	static const struct pci_device_id piix_pci_tbl[] = {
	426	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0), 0 },
	427	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1), 1 },
	428	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), 2 },
	429	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1), 3 },
	430	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB), 4 },
	431	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1), 5 },
	432	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1), 6 },
	433	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1), 7 },
	434	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1), 8 },
	435	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX), 9 },
	436	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9), 10 },
	437	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8), 11 },
	438	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 12 },
	439	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 13 },
	440	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 14 },
	441	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 15 },
	442	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11), 16 },
	443	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 17 },
1da177e4	444	#ifdef CONFIG_BLK_DEV_IDE_SATA
9cbcc5e3	445	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1), 18 },
1da177e4	446	#endif
9cbcc5e3 BZ	447	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2), 19 },
	448	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19), 20 },
	449	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21), 21 },
	450	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1), 22 },
	451	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18), 23 },
	452	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6), 24 },
1da177e4 LT	453	{ 0, },
	454	};
	455	MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
	456
	457	static struct pci_driver driver = {
	458	.name = "PIIX_IDE",
	459	.id_table = piix_pci_tbl,
	460	.probe = piix_init_one,
	461	};
	462
	463	static int __init piix_ide_init(void)
	464	{
	465	piix_check_450nx();
	466	return ide_pci_register_driver(&driver);
	467	}
	468
	469	module_init(piix_ide_init);
	470
	471	MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
	472	MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
	473	MODULE_LICENSE("GPL");