[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / pdc202xx_old.c

/*
 *  linux/drivers/ide/pci/pdc202xx_old.c	Version 0.50	Mar 3, 2007
 *
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007		MontaVista Software, Inc.
 *  Copyright (C) 2007			Bartlomiej Zolnierkiewicz
 *
 *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
 *  compiled into the kernel if you have more than one card installed.
 *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
 *  safe chipset tuning, including this support is harmless
 *
 *  Promise Ultra66 cards with BIOS v1.11 this
 *  compiled into the kernel if you have more than one card installed.
 *
 *  Promise Ultra100 cards.
 *
 *  The latest chipset code will support the following ::
 *  Three Ultra33 controllers and 12 drives.
 *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
 *  The 8/4 ratio is a BIOS code limit by promise.
 *
 *  UNLESS you enable "CONFIG_PDC202XX_BURST"
 *
 */

/*
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/irq.h>

#define PDC202XX_DEBUG_DRIVE_INFO	0

static const char *pdc_quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP KA9.1",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP KX13.6",
	"QUANTUM FIREBALLP KX20.5",
	"QUANTUM FIREBALLP KX27.3",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static void pdc_old_disable_66MHz_clock(ide_hwif_t *);

static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 drive_pci		= 0x60 + (drive->dn << 2);
	u8 speed		= ide_rate_filter(drive, xferspeed);

	u8			AP = 0, BP = 0, CP = 0;
	u8			TA = 0, TB = 0, TC = 0;

#if PDC202XX_DEBUG_DRIVE_INFO
	u32			drive_conf = 0;
	pci_read_config_dword(dev, drive_pci, &drive_conf);
#endif

	/*
	 * TODO: do this once per channel
	 */
	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
		pdc_old_disable_66MHz_clock(hwif);

	pci_read_config_byte(dev, drive_pci,     &AP);
	pci_read_config_byte(dev, drive_pci + 1, &BP);
	pci_read_config_byte(dev, drive_pci + 2, &CP);

	switch(speed) {
		case XFER_UDMA_5:
		case XFER_UDMA_4:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_2:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_3:
		case XFER_UDMA_1:	TB = 0x40; TC = 0x02; break;
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:	TB = 0x60; TC = 0x03; break;
		case XFER_MW_DMA_1:	TB = 0x60; TC = 0x04; break;
		case XFER_MW_DMA_0:	TB = 0xE0; TC = 0x0F; break;
		case XFER_SW_DMA_2:	TB = 0x60; TC = 0x05; break;
		case XFER_SW_DMA_1:	TB = 0x80; TC = 0x06; break;
		case XFER_SW_DMA_0:	TB = 0xC0; TC = 0x0B; break;
		case XFER_PIO_4:	TA = 0x01; TB = 0x04; break;
		case XFER_PIO_3:	TA = 0x02; TB = 0x06; break;
		case XFER_PIO_2:	TA = 0x03; TB = 0x08; break;
		case XFER_PIO_1:	TA = 0x05; TB = 0x0C; break;
		case XFER_PIO_0:
		default:		TA = 0x09; TB = 0x13; break;
	}

	if (speed < XFER_SW_DMA_0) {
		/*
		 * preserve SYNC_INT / ERDDY_EN bits while clearing
		 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
		 */
		AP &= ~0x3f;
		if (drive->id->capability & 4)
			AP |= 0x20;	/* set IORDY_EN bit */
		if (drive->media == ide_disk)
			AP |= 0x10;	/* set Prefetch_EN bit */
		/* clear PB[4:0] bits of register B */
		BP &= ~0x1f;
		pci_write_config_byte(dev, drive_pci,     AP | TA);
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
	} else {
		/* clear MB[2:0] bits of register B */
		BP &= ~0xe0;
		/* clear MC[3:0] bits of register C */
		CP &= ~0x0f;
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
		pci_write_config_byte(dev, drive_pci + 2, CP | TC);
	}

#if PDC202XX_DEBUG_DRIVE_INFO
	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
		drive->name, ide_xfer_verbose(speed),
		drive->dn, drive_conf);
	pci_read_config_dword(dev, drive_pci, &drive_conf);
	printk("0x%08x\n", drive_conf);
#endif

	return ide_config_drive_speed(drive, speed);
}

static void pdc202xx_tune_drive(ide_drive_t *drive, u8 pio)
{
	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
	pdc202xx_tune_chipset(drive, XFER_PIO_0 + pio);
}

static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
{
	u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
	pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
	return (CIS & mask) ? 1 : 0;
}

/*
 * Set the control register to use the 66MHz system
 * clock for UDMA 3/4/5 mode operation when necessary.
 *
 * FIXME: this register is shared by both channels, some locking is needed
 *
 * It may also be possible to leave the 66MHz clock on
 * and readjust the timing parameters.
 */
static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->dma_master + 0x11;
	u8 clock = inb(clock_reg);

	outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->dma_master + 0x11;
	u8 clock = inb(clock_reg);

	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
}

static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
{
	drive->init_speed = 0;

	if (ide_tune_dma(drive))
		return 0;

	if (ide_use_fast_pio(drive))
		pdc202xx_tune_drive(drive, 255);

	return -1;
}

static int pdc202xx_quirkproc (ide_drive_t *drive)
{
	const char **list, *model = drive->id->model;

	for (list = pdc_quirk_drives; *list != NULL; list++)
		if (strstr(model, *list) != NULL)
			return 2;
	return 0;
}

static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
{
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_enable_66MHz_clock(drive->hwif);
	if (drive->media != ide_disk || drive->addressing == 1) {
		struct request *rq	= HWGROUP(drive)->rq;
		ide_hwif_t *hwif	= HWIF(drive);
		unsigned long high_16   = hwif->dma_master;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u32 word_count	= 0;
		u8 clock = inb(high_16 + 0x11);

		outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
		word_count = (rq->nr_sectors << 8);
		word_count = (rq_data_dir(rq) == READ) ?
					word_count | 0x05000000 :
					word_count | 0x06000000;
		outl(word_count, atapi_reg);
	}
	ide_dma_start(drive);
}

static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
{
	if (drive->media != ide_disk || drive->addressing == 1) {
		ide_hwif_t *hwif	= HWIF(drive);
		unsigned long high_16	= hwif->dma_master;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u8 clock		= 0;

		outl(0, atapi_reg); /* zero out extra */
		clock = inb(high_16 + 0x11);
		outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
	}
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_disable_66MHz_clock(drive->hwif);
	return __ide_dma_end(drive);
}

static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	unsigned long high_16	= hwif->dma_master;
	u8 dma_stat		= inb(hwif->dma_status);
	u8 sc1d			= inb(high_16 + 0x001d);

	if (hwif->channel) {
		/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
		if ((sc1d & 0x50) == 0x50)
			goto somebody_else;
		else if ((sc1d & 0x40) == 0x40)
			return (dma_stat & 4) == 4;
	} else {
		/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
		if ((sc1d & 0x05) == 0x05)
			goto somebody_else;
		else if ((sc1d & 0x04) == 0x04)
			return (dma_stat & 4) == 4;
	}
somebody_else:
	return (dma_stat & 4) == 4;	/* return 1 if INTR asserted */
}

static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
{
	if (HWIF(drive)->resetproc != NULL)
		HWIF(drive)->resetproc(drive);
	return __ide_dma_lostirq(drive);
}

static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
{
	if (HWIF(drive)->resetproc != NULL)
		HWIF(drive)->resetproc(drive);
	return __ide_dma_timeout(drive);
}

static void pdc202xx_reset_host (ide_hwif_t *hwif)
{
	unsigned long high_16	= hwif->dma_master;
	u8 udma_speed_flag	= inb(high_16 | 0x001f);

	outb(udma_speed_flag | 0x10, high_16 | 0x001f);
	mdelay(100);
	outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
	mdelay(2000);	/* 2 seconds ?! */

	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
		hwif->channel ? "Secondary" : "Primary");
}

static void pdc202xx_reset (ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	ide_hwif_t *mate	= hwif->mate;
	
	pdc202xx_reset_host(hwif);
	pdc202xx_reset_host(mate);
	pdc202xx_tune_drive(drive, 255);
}

static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
							const char *name)
{
	/* This doesn't appear needed */
	if (dev->resource[PCI_ROM_RESOURCE].start) {
		pci_write_config_dword(dev, PCI_ROM_ADDRESS,
			dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
		printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
			(unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
	}

	return dev->irq;
}

static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
{
	struct pci_dev *dev = hwif->pci_dev;

	/* PDC20265 has problems with large LBA48 requests */
	if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
	    (dev->device == PCI_DEVICE_ID_PROMISE_20265))
		hwif->rqsize = 256;

	hwif->autodma = 0;
	hwif->tuneproc  = &pdc202xx_tune_drive;
	hwif->quirkproc = &pdc202xx_quirkproc;

	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
		hwif->resetproc = &pdc202xx_reset;

	hwif->speedproc = &pdc202xx_tune_chipset;

	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;

	hwif->ultra_mask = hwif->cds->udma_mask;
	hwif->mwdma_mask = 0x07;
	hwif->swdma_mask = 0x07;
	hwif->atapi_dma = 1;

	hwif->err_stops_fifo = 1;

	hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
	hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
	hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;

	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
		if (!(hwif->udma_four))
			hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
		hwif->dma_start = &pdc202xx_old_ide_dma_start;
		hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
	} 
	hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;

	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
}

static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
{
	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;

	if (hwif->channel) {
		ide_setup_dma(hwif, dmabase, 8);
		return;
	}

	udma_speed_flag	= inb(dmabase | 0x1f);
	primary_mode	= inb(dmabase | 0x1a);
	secondary_mode	= inb(dmabase | 0x1b);
	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
		"Primary %s Mode " \
		"Secondary %s Mode.\n", hwif->cds->name,
		(udma_speed_flag & 1) ? "EN" : "DIS",
		(primary_mode & 1) ? "MASTER" : "PCI",
		(secondary_mode & 1) ? "MASTER" : "PCI" );

#ifdef CONFIG_PDC202XX_BURST
	if (!(udma_speed_flag & 1)) {
		printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
			hwif->cds->name, udma_speed_flag,
			(udma_speed_flag|1));
		outb(udma_speed_flag | 1, dmabase | 0x1f);
		printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
	}
#endif /* CONFIG_PDC202XX_BURST */

	ide_setup_dma(hwif, dmabase, 8);
}

static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
					   ide_pci_device_t *d)
{
	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
		u8 irq = 0, irq2 = 0;
		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
		/* 0xbc */
		pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
		if (irq != irq2) {
			pci_write_config_byte(dev,
				(PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
			printk(KERN_INFO "%s: pci-config space interrupt "
				"mirror fixed.\n", d->name);
		}
	}
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_pdc20265(struct pci_dev *dev,
					 ide_pci_device_t *d)
{
	if ((dev->bus->self) &&
	    (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
	    ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
	     (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
		printk(KERN_INFO "ide: Skipping Promise PDC20265 "
			"attached to I2O RAID controller.\n");
		return -ENODEV;
	}
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
					 ide_pci_device_t *d)
{
	return ide_setup_pci_device(dev, d);
}

static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "PDC20246",
		.init_setup	= init_setup_pdc202ata4,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.extra		= 16,
		.udma_mask	= 0x07, /* udma0-2 */
	},{	/* 1 */
		.name		= "PDC20262",
		.init_setup	= init_setup_pdc202ata4,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.extra		= 48,
		.udma_mask	= 0x1f, /* udma0-4 */
	},{	/* 2 */
		.name		= "PDC20263",
		.init_setup	= init_setup_pdc202ata4,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.extra		= 48,
		.udma_mask	= 0x1f, /* udma0-4 */
	},{	/* 3 */
		.name		= "PDC20265",
		.init_setup	= init_setup_pdc20265,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.extra		= 48,
		.udma_mask	= 0x3f, /* udma0-5 */
	},{	/* 4 */
		.name		= "PDC20267",
		.init_setup	= init_setup_pdc202xx,
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.extra		= 48,
		.udma_mask	= 0x3f, /* udma0-5 */
	}
};

/**
 *	pdc202xx_init_one	-	called when a PDC202xx is found
 *	@dev: the pdc202xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];

	return d->init_setup(dev, d);
}

static struct pci_device_id pdc202xx_pci_tbl[] = {
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);

static struct pci_driver driver = {
	.name		= "Promise_Old_IDE",
	.id_table	= pdc202xx_pci_tbl,
	.probe		= pdc202xx_init_one,
};

static int __init pdc202xx_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(pdc202xx_ide_init);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
4fce3164	2	* linux/drivers/ide/pci/pdc202xx_old.c Version 0.50 Mar 3, 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
fed21641	5	* Copyright (C) 2006-2007 MontaVista Software, Inc.
4fce3164	6	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	7	*
	8	* Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
	9	* compiled into the kernel if you have more than one card installed.
	10	* Note that BIOS v1.29 is reported to fix the problem. Since this is
	11	* safe chipset tuning, including this support is harmless
	12	*
	13	* Promise Ultra66 cards with BIOS v1.11 this
	14	* compiled into the kernel if you have more than one card installed.
	15	*
	16	* Promise Ultra100 cards.
	17	*
	18	* The latest chipset code will support the following ::
	19	* Three Ultra33 controllers and 12 drives.
	20	* 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
	21	* The 8/4 ratio is a BIOS code limit by promise.
	22	*
	23	* UNLESS you enable "CONFIG_PDC202XX_BURST"
	24	*
	25	*/
	26
	27	/*
	28	* Portions Copyright (C) 1999 Promise Technology, Inc.
	29	* Author: Frank Tiernan (frankt@promise.com)
	30	* Released under terms of General Public License
	31	*/
	32
1da177e4 LT	33	#include <linux/types.h>
	34	#include <linux/module.h>
	35	#include <linux/kernel.h>
	36	#include <linux/delay.h>
	37	#include <linux/timer.h>
	38	#include <linux/mm.h>
	39	#include <linux/ioport.h>
	40	#include <linux/blkdev.h>
	41	#include <linux/hdreg.h>
	42	#include <linux/interrupt.h>
	43	#include <linux/pci.h>
	44	#include <linux/init.h>
	45	#include <linux/ide.h>
	46
	47	#include <asm/io.h>
	48	#include <asm/irq.h>
	49
1da177e4 LT	50	#define PDC202XX_DEBUG_DRIVE_INFO 0
	51
	52	static const char *pdc_quirk_drives[] = {
	53	"QUANTUM FIREBALLlct08 08",
	54	"QUANTUM FIREBALLP KA6.4",
	55	"QUANTUM FIREBALLP KA9.1",
	56	"QUANTUM FIREBALLP LM20.4",
	57	"QUANTUM FIREBALLP KX13.6",
	58	"QUANTUM FIREBALLP KX20.5",
	59	"QUANTUM FIREBALLP KX27.3",
	60	"QUANTUM FIREBALLP LM20.5",
	61	NULL
	62	};
	63
4fce3164	64	static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
1da177e4	65
1da177e4 LT	66	static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
	67	{
	68	ide_hwif_t *hwif = HWIF(drive);
	69	struct pci_dev *dev = hwif->pci_dev;
	70	u8 drive_pci = 0x60 + (drive->dn << 2);
2d5eaa6d	71	u8 speed = ide_rate_filter(drive, xferspeed);
1da177e4	72
4fce3164	73	u8 AP = 0, BP = 0, CP = 0;
1da177e4 LT	74	u8 TA = 0, TB = 0, TC = 0;
1da177e4 LT	75
4fce3164 BZ	76	#if PDC202XX_DEBUG_DRIVE_INFO
4fce3164 BZ	77	u32 drive_conf = 0;
1da177e4	78	pci_read_config_dword(dev, drive_pci, &drive_conf);
4fce3164	79	#endif
1da177e4	80
4fce3164 BZ	81	/*
	82	* TODO: do this once per channel
	83	*/
	84	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
	85	pdc_old_disable_66MHz_clock(hwif);
1da177e4	86
4fce3164 BZ	87	pci_read_config_byte(dev, drive_pci, &AP);
	88	pci_read_config_byte(dev, drive_pci + 1, &BP);
	89	pci_read_config_byte(dev, drive_pci + 2, &CP);
1da177e4 LT	90
1da177e4 LT	91	switch(speed) {
1da177e4 LT	92	case XFER_UDMA_5:
	93	case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
	94	case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
	95	case XFER_UDMA_3:
	96	case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
	97	case XFER_UDMA_0:
	98	case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
	99	case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
4fce3164	100	case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
1da177e4 LT	101	case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break;
	102	case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break;
	103	case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break;
	104	case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
	105	case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
	106	case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
	107	case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
	108	case XFER_PIO_0:
	109	default: TA = 0x09; TB = 0x13; break;
	110	}
	111
	112	if (speed < XFER_SW_DMA_0) {
4fce3164 BZ	113	/*
	114	* preserve SYNC_INT / ERDDY_EN bits while clearing
	115	* Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
	116	*/
	117	AP &= ~0x3f;
	118	if (drive->id->capability & 4)
	119	AP \|= 0x20; /* set IORDY_EN bit */
	120	if (drive->media == ide_disk)
	121	AP \|= 0x10; /* set Prefetch_EN bit */
	122	/* clear PB[4:0] bits of register B */
	123	BP &= ~0x1f;
	124	pci_write_config_byte(dev, drive_pci, AP \| TA);
	125	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
1da177e4	126	} else {
4fce3164 BZ	127	/* clear MB[2:0] bits of register B */
	128	BP &= ~0xe0;
	129	/* clear MC[3:0] bits of register C */
	130	CP &= ~0x0f;
	131	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
	132	pci_write_config_byte(dev, drive_pci + 2, CP \| TC);
1da177e4 LT	133	}
	134
	135	#if PDC202XX_DEBUG_DRIVE_INFO
	136	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
	137	drive->name, ide_xfer_verbose(speed),
	138	drive->dn, drive_conf);
4fce3164	139	pci_read_config_dword(dev, drive_pci, &drive_conf);
1da177e4	140	printk("0x%08x\n", drive_conf);
4fce3164	141	#endif
1da177e4	142
4fce3164	143	return ide_config_drive_speed(drive, speed);
1da177e4 LT	144	}
1da177e4 LT	145
fed21641	146	static void pdc202xx_tune_drive(ide_drive_t *drive, u8 pio)
1da177e4	147	{
fed21641 SS	148	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
fed21641 SS	149	pdc202xx_tune_chipset(drive, XFER_PIO_0 + pio);
1da177e4 LT	150	}
	151
	152	static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
	153	{
	154	u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
	155	pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
	156	return (CIS & mask) ? 1 : 0;
	157	}
	158
	159	/*
	160	* Set the control register to use the 66MHz system
	161	* clock for UDMA 3/4/5 mode operation when necessary.
	162	*
4fce3164 BZ	163	* FIXME: this register is shared by both channels, some locking is needed
4fce3164 BZ	164	*
1da177e4 LT	165	* It may also be possible to leave the 66MHz clock on
	166	* and readjust the timing parameters.
	167	*/
	168	static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
	169	{
	170	unsigned long clock_reg = hwif->dma_master + 0x11;
0ecdca26	171	u8 clock = inb(clock_reg);
1da177e4	172
0ecdca26	173	outb(clock \| (hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	174	}
	175
	176	static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
	177	{
	178	unsigned long clock_reg = hwif->dma_master + 0x11;
0ecdca26	179	u8 clock = inb(clock_reg);
1da177e4	180
0ecdca26	181	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	182	}
1da177e4 LT	183
1da177e4 LT	184	static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
1da177e4 LT	185	{
1da177e4 LT	186	drive->init_speed = 0;
1da177e4 LT	187
bd203b57	188	if (ide_tune_dma(drive))
3608b5d7	189	return 0;
1da177e4	190
d8f4469d	191	if (ide_use_fast_pio(drive))
fed21641	192	pdc202xx_tune_drive(drive, 255);
d8f4469d	193
3608b5d7	194	return -1;
1da177e4 LT	195	}
	196
	197	static int pdc202xx_quirkproc (ide_drive_t *drive)
	198	{
d24ec426 SS	199	const char *list, model = drive->id->model;
	200
	201	for (list = pdc_quirk_drives; *list != NULL; list++)
	202	if (strstr(model, *list) != NULL)
	203	return 2;
	204	return 0;
1da177e4 LT	205	}
	206
	207	static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
	208	{
	209	if (drive->current_speed > XFER_UDMA_2)
	210	pdc_old_enable_66MHz_clock(drive->hwif);
f3d5b34c	211	if (drive->media != ide_disk \|\| drive->addressing == 1) {
1da177e4 LT	212	struct request *rq = HWGROUP(drive)->rq;
1da177e4 LT	213	ide_hwif_t *hwif = HWIF(drive);
1da177e4 LT	214	unsigned long high_16 = hwif->dma_master;
	215	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
	216	u32 word_count = 0;
0ecdca26	217	u8 clock = inb(high_16 + 0x11);
1da177e4	218
0ecdca26	219	outb(clock \| (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
1da177e4 LT	220	word_count = (rq->nr_sectors << 8);
	221	word_count = (rq_data_dir(rq) == READ) ?
	222	word_count \| 0x05000000 :
	223	word_count \| 0x06000000;
0ecdca26	224	outl(word_count, atapi_reg);
1da177e4 LT	225	}
	226	ide_dma_start(drive);
	227	}
	228
	229	static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
	230	{
f3d5b34c	231	if (drive->media != ide_disk \|\| drive->addressing == 1) {
1da177e4	232	ide_hwif_t *hwif = HWIF(drive);
1da177e4 LT	233	unsigned long high_16 = hwif->dma_master;
	234	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
	235	u8 clock = 0;
	236
0ecdca26 BZ	237	outl(0, atapi_reg); /* zero out extra */
	238	clock = inb(high_16 + 0x11);
	239	outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
1da177e4 LT	240	}
	241	if (drive->current_speed > XFER_UDMA_2)
	242	pdc_old_disable_66MHz_clock(drive->hwif);
	243	return __ide_dma_end(drive);
	244	}
	245
	246	static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
	247	{
	248	ide_hwif_t *hwif = HWIF(drive);
1da177e4	249	unsigned long high_16 = hwif->dma_master;
0ecdca26 BZ	250	u8 dma_stat = inb(hwif->dma_status);
0ecdca26 BZ	251	u8 sc1d = inb(high_16 + 0x001d);
1da177e4 LT	252
	253	if (hwif->channel) {
	254	/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
	255	if ((sc1d & 0x50) == 0x50)
	256	goto somebody_else;
	257	else if ((sc1d & 0x40) == 0x40)
	258	return (dma_stat & 4) == 4;
	259	} else {
	260	/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
	261	if ((sc1d & 0x05) == 0x05)
	262	goto somebody_else;
	263	else if ((sc1d & 0x04) == 0x04)
	264	return (dma_stat & 4) == 4;
	265	}
	266	somebody_else:
	267	return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
	268	}
	269
	270	static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
	271	{
	272	if (HWIF(drive)->resetproc != NULL)
	273	HWIF(drive)->resetproc(drive);
	274	return __ide_dma_lostirq(drive);
	275	}
	276
	277	static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
	278	{
	279	if (HWIF(drive)->resetproc != NULL)
	280	HWIF(drive)->resetproc(drive);
	281	return __ide_dma_timeout(drive);
	282	}
	283
	284	static void pdc202xx_reset_host (ide_hwif_t *hwif)
	285	{
1da177e4	286	unsigned long high_16 = hwif->dma_master;
0ecdca26	287	u8 udma_speed_flag = inb(high_16 \| 0x001f);
1da177e4	288
0ecdca26	289	outb(udma_speed_flag \| 0x10, high_16 \| 0x001f);
1da177e4	290	mdelay(100);
0ecdca26	291	outb(udma_speed_flag & ~0x10, high_16 \| 0x001f);
1da177e4 LT	292	mdelay(2000); /* 2 seconds ?! */
	293
	294	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
	295	hwif->channel ? "Secondary" : "Primary");
	296	}
	297
	298	static void pdc202xx_reset (ide_drive_t *drive)
	299	{
	300	ide_hwif_t *hwif = HWIF(drive);
	301	ide_hwif_t *mate = hwif->mate;
	302
	303	pdc202xx_reset_host(hwif);
	304	pdc202xx_reset_host(mate);
fed21641	305	pdc202xx_tune_drive(drive, 255);
1da177e4 LT	306	}
1da177e4 LT	307
57e834e2 AC	308	static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
57e834e2 AC	309	const char *name)
1da177e4	310	{
57e834e2	311	/* This doesn't appear needed */
1da177e4 LT	312	if (dev->resource[PCI_ROM_RESOURCE].start) {
	313	pci_write_config_dword(dev, PCI_ROM_ADDRESS,
	314	dev->resource[PCI_ROM_RESOURCE].start \| PCI_ROM_ADDRESS_ENABLE);
08f46de9 GKH	315	printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
08f46de9 GKH	316	(unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
1da177e4 LT	317	}
1da177e4 LT	318
1da177e4 LT	319	return dev->irq;
	320	}
	321
	322	static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
	323	{
	324	struct pci_dev *dev = hwif->pci_dev;
	325
	326	/* PDC20265 has problems with large LBA48 requests */
	327	if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) \|\|
	328	(dev->device == PCI_DEVICE_ID_PROMISE_20265))
	329	hwif->rqsize = 256;
	330
	331	hwif->autodma = 0;
fed21641	332	hwif->tuneproc = &pdc202xx_tune_drive;
1da177e4 LT	333	hwif->quirkproc = &pdc202xx_quirkproc;
1da177e4 LT	334
8b6ebe01	335	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
1da177e4	336	hwif->resetproc = &pdc202xx_reset;
1da177e4 LT	337
	338	hwif->speedproc = &pdc202xx_tune_chipset;
	339
	340	hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
	341
18137207	342	hwif->ultra_mask = hwif->cds->udma_mask;
1da177e4 LT	343	hwif->mwdma_mask = 0x07;
1da177e4 LT	344	hwif->swdma_mask = 0x07;
f3d5b34c	345	hwif->atapi_dma = 1;
1da177e4	346
57e834e2 AC	347	hwif->err_stops_fifo = 1;
57e834e2 AC	348
1da177e4 LT	349	hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
	350	hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
	351	hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
	352
	353	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
	354	if (!(hwif->udma_four))
	355	hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
	356	hwif->dma_start = &pdc202xx_old_ide_dma_start;
	357	hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
	358	}
	359	hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
	360
	361	if (!noautodma)
	362	hwif->autodma = 1;
	363	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1da177e4 LT	364	}
	365
	366	static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
	367	{
	368	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
	369
	370	if (hwif->channel) {
	371	ide_setup_dma(hwif, dmabase, 8);
	372	return;
	373	}
	374
0ecdca26 BZ	375	udma_speed_flag = inb(dmabase \| 0x1f);
	376	primary_mode = inb(dmabase \| 0x1a);
	377	secondary_mode = inb(dmabase \| 0x1b);
1da177e4 LT	378	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
	379	"Primary %s Mode " \
	380	"Secondary %s Mode.\n", hwif->cds->name,
	381	(udma_speed_flag & 1) ? "EN" : "DIS",
	382	(primary_mode & 1) ? "MASTER" : "PCI",
	383	(secondary_mode & 1) ? "MASTER" : "PCI" );
	384
	385	#ifdef CONFIG_PDC202XX_BURST
	386	if (!(udma_speed_flag & 1)) {
	387	printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
	388	hwif->cds->name, udma_speed_flag,
	389	(udma_speed_flag\|1));
0ecdca26 BZ	390	outb(udma_speed_flag \| 1, dmabase \| 0x1f);
0ecdca26 BZ	391	printk("%sACTIVE\n", (inb(dmabase \| 0x1f) & 1) ? "" : "IN");
1da177e4 LT	392	}
1da177e4 LT	393	#endif /* CONFIG_PDC202XX_BURST */
1da177e4 LT	394
	395	ide_setup_dma(hwif, dmabase, 8);
	396	}
	397
	398	static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
	399	ide_pci_device_t *d)
	400	{
	401	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
	402	u8 irq = 0, irq2 = 0;
	403	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	404	/* 0xbc */
	405	pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)\|0x80, &irq2);
	406	if (irq != irq2) {
	407	pci_write_config_byte(dev,
	408	(PCI_INTERRUPT_LINE)\|0x80, irq); /* 0xbc */
	409	printk(KERN_INFO "%s: pci-config space interrupt "
	410	"mirror fixed.\n", d->name);
	411	}
	412	}
1da177e4 LT	413	return ide_setup_pci_device(dev, d);
	414	}
	415
	416	static int __devinit init_setup_pdc20265(struct pci_dev *dev,
	417	ide_pci_device_t *d)
	418	{
	419	if ((dev->bus->self) &&
	420	(dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
	421	((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) \|\|
	422	(dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
	423	printk(KERN_INFO "ide: Skipping Promise PDC20265 "
	424	"attached to I2O RAID controller.\n");
	425	return -ENODEV;
	426	}
1da177e4 LT	427	return ide_setup_pci_device(dev, d);
	428	}
	429
	430	static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
	431	ide_pci_device_t *d)
	432	{
	433	return ide_setup_pci_device(dev, d);
	434	}
	435
	436	static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
	437	{ /* 0 */
	438	.name = "PDC20246",
	439	.init_setup = init_setup_pdc202ata4,
	440	.init_chipset = init_chipset_pdc202xx,
	441	.init_hwif = init_hwif_pdc202xx,
	442	.init_dma = init_dma_pdc202xx,
	443	.channels = 2,
	444	.autodma = AUTODMA,
1da177e4 LT	445	.bootable = OFF_BOARD,
1da177e4 LT	446	.extra = 16,
18137207	447	.udma_mask = 0x07, /* udma0-2 */
1da177e4 LT	448	},{ /* 1 */
	449	.name = "PDC20262",
	450	.init_setup = init_setup_pdc202ata4,
	451	.init_chipset = init_chipset_pdc202xx,
	452	.init_hwif = init_hwif_pdc202xx,
	453	.init_dma = init_dma_pdc202xx,
	454	.channels = 2,
	455	.autodma = AUTODMA,
1da177e4 LT	456	.bootable = OFF_BOARD,
1da177e4 LT	457	.extra = 48,
18137207	458	.udma_mask = 0x1f, /* udma0-4 */
1da177e4 LT	459	},{ /* 2 */
	460	.name = "PDC20263",
	461	.init_setup = init_setup_pdc202ata4,
	462	.init_chipset = init_chipset_pdc202xx,
	463	.init_hwif = init_hwif_pdc202xx,
	464	.init_dma = init_dma_pdc202xx,
	465	.channels = 2,
	466	.autodma = AUTODMA,
1da177e4 LT	467	.bootable = OFF_BOARD,
1da177e4 LT	468	.extra = 48,
18137207	469	.udma_mask = 0x1f, /* udma0-4 */
1da177e4 LT	470	},{ /* 3 */
	471	.name = "PDC20265",
	472	.init_setup = init_setup_pdc20265,
	473	.init_chipset = init_chipset_pdc202xx,
	474	.init_hwif = init_hwif_pdc202xx,
	475	.init_dma = init_dma_pdc202xx,
	476	.channels = 2,
	477	.autodma = AUTODMA,
1da177e4 LT	478	.bootable = OFF_BOARD,
1da177e4 LT	479	.extra = 48,
18137207	480	.udma_mask = 0x3f, /* udma0-5 */
1da177e4 LT	481	},{ /* 4 */
	482	.name = "PDC20267",
	483	.init_setup = init_setup_pdc202xx,
	484	.init_chipset = init_chipset_pdc202xx,
	485	.init_hwif = init_hwif_pdc202xx,
	486	.init_dma = init_dma_pdc202xx,
	487	.channels = 2,
	488	.autodma = AUTODMA,
1da177e4 LT	489	.bootable = OFF_BOARD,
1da177e4 LT	490	.extra = 48,
18137207	491	.udma_mask = 0x3f, /* udma0-5 */
1da177e4 LT	492	}
	493	};
	494
	495	/**
	496	* pdc202xx_init_one - called when a PDC202xx is found
	497	* @dev: the pdc202xx device
	498	* @id: the matching pci id
	499	*
	500	* Called when the PCI registration layer (or the IDE initialization)
	501	* finds a device matching our IDE device tables.
	502	*/
	503
	504	static int __devinit pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
	505	{
	506	ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
	507
	508	return d->init_setup(dev, d);
	509	}
	510
	511	static struct pci_device_id pdc202xx_pci_tbl[] = {
	512	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
	513	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
	514	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
	515	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
	516	{ PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
	517	{ 0, },
	518	};
	519	MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
	520
	521	static struct pci_driver driver = {
	522	.name = "Promise_Old_IDE",
	523	.id_table = pdc202xx_pci_tbl,
	524	.probe = pdc202xx_init_one,
	525	};
	526
82ab1eec	527	static int __init pdc202xx_ide_init(void)
1da177e4 LT	528	{
	529	return ide_pci_register_driver(&driver);
	530	}
	531
	532	module_init(pdc202xx_ide_init);
	533
	534	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	535	MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
	536	MODULE_LICENSE("GPL");