[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / pdc202xx_old.c

/*
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007		MontaVista Software, Inc.
 *  Copyright (C) 2007			Bartlomiej Zolnierkiewicz
 *
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>

#define PDC202XX_DEBUG_DRIVE_INFO	0

static const char *pdc_quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP KA9.1",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP KX13.6",
	"QUANTUM FIREBALLP KX20.5",
	"QUANTUM FIREBALLP KX27.3",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static void pdc_old_disable_66MHz_clock(ide_hwif_t *);

static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 drive_pci		= 0x60 + (drive->dn << 2);

	u8			AP = 0, BP = 0, CP = 0;
	u8			TA = 0, TB = 0, TC = 0;

#if PDC202XX_DEBUG_DRIVE_INFO
	u32			drive_conf = 0;
	pci_read_config_dword(dev, drive_pci, &drive_conf);
#endif

	/*
	 * TODO: do this once per channel
	 */
	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
		pdc_old_disable_66MHz_clock(hwif);

	pci_read_config_byte(dev, drive_pci,     &AP);
	pci_read_config_byte(dev, drive_pci + 1, &BP);
	pci_read_config_byte(dev, drive_pci + 2, &CP);

	switch(speed) {
		case XFER_UDMA_5:
		case XFER_UDMA_4:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_2:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_3:
		case XFER_UDMA_1:	TB = 0x40; TC = 0x02; break;
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:	TB = 0x60; TC = 0x03; break;
		case XFER_MW_DMA_1:	TB = 0x60; TC = 0x04; break;
		case XFER_MW_DMA_0:	TB = 0xE0; TC = 0x0F; break;
		case XFER_PIO_4:	TA = 0x01; TB = 0x04; break;
		case XFER_PIO_3:	TA = 0x02; TB = 0x06; break;
		case XFER_PIO_2:	TA = 0x03; TB = 0x08; break;
		case XFER_PIO_1:	TA = 0x05; TB = 0x0C; break;
		case XFER_PIO_0:
		default:		TA = 0x09; TB = 0x13; break;
	}

	if (speed < XFER_SW_DMA_0) {
		/*
		 * preserve SYNC_INT / ERDDY_EN bits while clearing
		 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
		 */
		AP &= ~0x3f;
		if (drive->id->capability & 4)
			AP |= 0x20;	/* set IORDY_EN bit */
		if (drive->media == ide_disk)
			AP |= 0x10;	/* set Prefetch_EN bit */
		/* clear PB[4:0] bits of register B */
		BP &= ~0x1f;
		pci_write_config_byte(dev, drive_pci,     AP | TA);
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
	} else {
		/* clear MB[2:0] bits of register B */
		BP &= ~0xe0;
		/* clear MC[3:0] bits of register C */
		CP &= ~0x0f;
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
		pci_write_config_byte(dev, drive_pci + 2, CP | TC);
	}

#if PDC202XX_DEBUG_DRIVE_INFO
	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
		drive->name, ide_xfer_verbose(speed),
		drive->dn, drive_conf);
	pci_read_config_dword(dev, drive_pci, &drive_conf);
	printk("0x%08x\n", drive_conf);
#endif
}

static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
}

static u8 __devinit pdc2026x_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);

	pci_read_config_word(dev, 0x50, &CIS);

	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

/*
 * Set the control register to use the 66MHz system
 * clock for UDMA 3/4/5 mode operation when necessary.
 *
 * FIXME: this register is shared by both channels, some locking is needed
 *
 * It may also be possible to leave the 66MHz clock on
 * and readjust the timing parameters.
 */
static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc202xx_quirkproc(ide_drive_t *drive)
{
	const char **list, *model = drive->id->model;

	for (list = pdc_quirk_drives; *list != NULL; list++)
		if (strstr(model, *list) != NULL) {
			drive->quirk_list = 2;
			return;
		}

	drive->quirk_list = 0;
}

static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
{
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_enable_66MHz_clock(drive->hwif);
	if (drive->media != ide_disk || drive->addressing == 1) {
		struct request *rq	= HWGROUP(drive)->rq;
		ide_hwif_t *hwif	= HWIF(drive);
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u32 word_count	= 0;
		u8 clock = inb(high_16 + 0x11);

		outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
		word_count = (rq->nr_sectors << 8);
		word_count = (rq_data_dir(rq) == READ) ?
					word_count | 0x05000000 :
					word_count | 0x06000000;
		outl(word_count, atapi_reg);
	}
	ide_dma_start(drive);
}

static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
{
	if (drive->media != ide_disk || drive->addressing == 1) {
		ide_hwif_t *hwif	= HWIF(drive);
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u8 clock		= 0;

		outl(0, atapi_reg); /* zero out extra */
		clock = inb(high_16 + 0x11);
		outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
	}
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_disable_66MHz_clock(drive->hwif);
	return __ide_dma_end(drive);
}

static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	unsigned long high_16	= hwif->extra_base - 16;
	u8 dma_stat		= inb(hwif->dma_status);
	u8 sc1d			= inb(high_16 + 0x001d);

	if (hwif->channel) {
		/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
		if ((sc1d & 0x50) == 0x50)
			goto somebody_else;
		else if ((sc1d & 0x40) == 0x40)
			return (dma_stat & 4) == 4;
	} else {
		/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
		if ((sc1d & 0x05) == 0x05)
			goto somebody_else;
		else if ((sc1d & 0x04) == 0x04)
			return (dma_stat & 4) == 4;
	}
somebody_else:
	return (dma_stat & 4) == 4;	/* return 1 if INTR asserted */
}

static void pdc202xx_reset_host (ide_hwif_t *hwif)
{
	unsigned long high_16	= hwif->extra_base - 16;
	u8 udma_speed_flag	= inb(high_16 | 0x001f);

	outb(udma_speed_flag | 0x10, high_16 | 0x001f);
	mdelay(100);
	outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
	mdelay(2000);	/* 2 seconds ?! */

	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
		hwif->channel ? "Secondary" : "Primary");
}

static void pdc202xx_reset (ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	ide_hwif_t *mate	= hwif->mate;

	pdc202xx_reset_host(hwif);
	pdc202xx_reset_host(mate);

	ide_set_max_pio(drive);
}

static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
{
	pdc202xx_reset(drive);
	ide_dma_lost_irq(drive);
}

static void pdc202xx_dma_timeout(ide_drive_t *drive)
{
	pdc202xx_reset(drive);
	ide_dma_timeout(drive);
}

static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
							const char *name)
{
	return dev->irq;
}

static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (hwif->dma_base == 0)
		return;

	hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
	hwif->dma_timeout = &pdc202xx_dma_timeout;

	if (dev->device != PCI_DEVICE_ID_PROMISE_20246) {
		hwif->dma_start = &pdc202xx_old_ide_dma_start;
		hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
	} 
	hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
}

static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
{
	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;

	if (hwif->channel) {
		ide_setup_dma(hwif, dmabase);
		return;
	}

	udma_speed_flag	= inb(dmabase | 0x1f);
	primary_mode	= inb(dmabase | 0x1a);
	secondary_mode	= inb(dmabase | 0x1b);
	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
		"Primary %s Mode " \
		"Secondary %s Mode.\n", hwif->cds->name,
		(udma_speed_flag & 1) ? "EN" : "DIS",
		(primary_mode & 1) ? "MASTER" : "PCI",
		(secondary_mode & 1) ? "MASTER" : "PCI" );

	if (!(udma_speed_flag & 1)) {
		printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
			hwif->cds->name, udma_speed_flag,
			(udma_speed_flag|1));
		outb(udma_speed_flag | 1, dmabase | 0x1f);
		printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
	}

	ide_setup_dma(hwif, dmabase);
}

static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
					   const char *name)
{
	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
		u8 irq = 0, irq2 = 0;
		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
		/* 0xbc */
		pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
		if (irq != irq2) {
			pci_write_config_byte(dev,
				(PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
			printk(KERN_INFO "%s: PCI config space interrupt "
					 "mirror fixed\n", name);
		}
	}
}

#define IDE_HFLAGS_PDC202XX \
	(IDE_HFLAG_ERROR_STOPS_FIFO | \
	 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
	 IDE_HFLAG_OFF_BOARD)

static const struct ide_port_ops pdc20246_port_ops = {
	.set_pio_mode		= pdc202xx_set_pio_mode,
	.set_dma_mode		= pdc202xx_set_mode,
	.quirkproc		= pdc202xx_quirkproc,
};

static const struct ide_port_ops pdc2026x_port_ops = {
	.set_pio_mode		= pdc202xx_set_pio_mode,
	.set_dma_mode		= pdc202xx_set_mode,
	.quirkproc		= pdc202xx_quirkproc,
	.resetproc		= pdc202xx_reset,
	.cable_detect		= pdc2026x_cable_detect,
};

#define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
	{ \
		.name		= name_str, \
		.init_chipset	= init_chipset_pdc202xx, \
		.init_hwif	= init_hwif_pdc202xx, \
		.init_dma	= init_dma_pdc202xx, \
		.port_ops	= &pdc2026x_port_ops, \
		.host_flags	= IDE_HFLAGS_PDC202XX | extra_flags, \
		.pio_mask	= ATA_PIO4, \
		.mwdma_mask	= ATA_MWDMA2, \
		.udma_mask	= udma, \
	}

static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "PDC20246",
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.port_ops	= &pdc20246_port_ops,
		.host_flags	= IDE_HFLAGS_PDC202XX,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},

	/* 1 */ DECLARE_PDC2026X_DEV("PDC20262", ATA_UDMA4, 0),
	/* 2 */ DECLARE_PDC2026X_DEV("PDC20263", ATA_UDMA4, 0),
	/* 3 */ DECLARE_PDC2026X_DEV("PDC20265", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
	/* 4 */ DECLARE_PDC2026X_DEV("PDC20267", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
};

/**
 *	pdc202xx_init_one	-	called when a PDC202xx is found
 *	@dev: the pdc202xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	const struct ide_port_info *d;
	u8 idx = id->driver_data;

	d = &pdc202xx_chipsets[idx];

	if (idx < 3)
		pdc202ata4_fixup_irq(dev, d->name);

	if (idx == 3) {
		struct pci_dev *bridge = dev->bus->self;

		if (bridge &&
		    bridge->vendor == PCI_VENDOR_ID_INTEL &&
		    (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
		     bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
			printk(KERN_INFO "ide: Skipping Promise PDC20265 "
				"attached to I2O RAID controller\n");
			return -ENODEV;
		}
	}

	return ide_setup_pci_device(dev, d);
}

static const struct pci_device_id pdc202xx_pci_tbl[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);

static struct pci_driver driver = {
	.name		= "Promise_Old_IDE",
	.id_table	= pdc202xx_pci_tbl,
	.probe		= pdc202xx_init_one,
};

static int __init pdc202xx_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(pdc202xx_ide_init);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
fed21641	3	* Copyright (C) 2006-2007 MontaVista Software, Inc.
4fce3164	4	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4	5	*
1da177e4 LT	6	* Portions Copyright (C) 1999 Promise Technology, Inc.
	7	* Author: Frank Tiernan (frankt@promise.com)
	8	* Released under terms of General Public License
	9	*/
	10
1da177e4 LT	11	#include <linux/types.h>
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/delay.h>
1da177e4 LT	15	#include <linux/blkdev.h>
1da177e4 LT	16	#include <linux/hdreg.h>
1da177e4 LT	17	#include <linux/pci.h>
	18	#include <linux/init.h>
	19	#include <linux/ide.h>
	20
	21	#include <asm/io.h>
1da177e4	22
1da177e4 LT	23	#define PDC202XX_DEBUG_DRIVE_INFO 0
	24
	25	static const char *pdc_quirk_drives[] = {
	26	"QUANTUM FIREBALLlct08 08",
	27	"QUANTUM FIREBALLP KA6.4",
	28	"QUANTUM FIREBALLP KA9.1",
	29	"QUANTUM FIREBALLP LM20.4",
	30	"QUANTUM FIREBALLP KX13.6",
	31	"QUANTUM FIREBALLP KX20.5",
	32	"QUANTUM FIREBALLP KX27.3",
	33	"QUANTUM FIREBALLP LM20.5",
	34	NULL
	35	};
	36
4fce3164	37	static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
1da177e4	38
88b2b32b	39	static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	40	{
1da177e4 LT	41	ide_hwif_t *hwif = HWIF(drive);
36501650	42	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	43	u8 drive_pci = 0x60 + (drive->dn << 2);
1da177e4	44
4fce3164	45	u8 AP = 0, BP = 0, CP = 0;
1da177e4 LT	46	u8 TA = 0, TB = 0, TC = 0;
1da177e4 LT	47
4fce3164 BZ	48	#if PDC202XX_DEBUG_DRIVE_INFO
4fce3164 BZ	49	u32 drive_conf = 0;
1da177e4	50	pci_read_config_dword(dev, drive_pci, &drive_conf);
4fce3164	51	#endif
1da177e4	52
4fce3164 BZ	53	/*
	54	* TODO: do this once per channel
	55	*/
	56	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
	57	pdc_old_disable_66MHz_clock(hwif);
1da177e4	58
4fce3164 BZ	59	pci_read_config_byte(dev, drive_pci, &AP);
	60	pci_read_config_byte(dev, drive_pci + 1, &BP);
	61	pci_read_config_byte(dev, drive_pci + 2, &CP);
1da177e4 LT	62
1da177e4 LT	63	switch(speed) {
1da177e4 LT	64	case XFER_UDMA_5:
	65	case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
	66	case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
	67	case XFER_UDMA_3:
	68	case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
	69	case XFER_UDMA_0:
	70	case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
	71	case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
4fce3164	72	case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
1da177e4 LT	73	case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
	74	case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
	75	case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
	76	case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
	77	case XFER_PIO_0:
	78	default: TA = 0x09; TB = 0x13; break;
	79	}
	80
	81	if (speed < XFER_SW_DMA_0) {
4fce3164 BZ	82	/*
	83	* preserve SYNC_INT / ERDDY_EN bits while clearing
	84	* Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
	85	*/
	86	AP &= ~0x3f;
	87	if (drive->id->capability & 4)
	88	AP \|= 0x20; /* set IORDY_EN bit */
	89	if (drive->media == ide_disk)
	90	AP \|= 0x10; /* set Prefetch_EN bit */
	91	/* clear PB[4:0] bits of register B */
	92	BP &= ~0x1f;
	93	pci_write_config_byte(dev, drive_pci, AP \| TA);
	94	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
1da177e4	95	} else {
4fce3164 BZ	96	/* clear MB[2:0] bits of register B */
	97	BP &= ~0xe0;
	98	/* clear MC[3:0] bits of register C */
	99	CP &= ~0x0f;
	100	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
	101	pci_write_config_byte(dev, drive_pci + 2, CP \| TC);
1da177e4 LT	102	}
	103
	104	#if PDC202XX_DEBUG_DRIVE_INFO
	105	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
	106	drive->name, ide_xfer_verbose(speed),
	107	drive->dn, drive_conf);
4fce3164	108	pci_read_config_dword(dev, drive_pci, &drive_conf);
1da177e4	109	printk("0x%08x\n", drive_conf);
4fce3164	110	#endif
1da177e4 LT	111	}
1da177e4 LT	112
26bcb879	113	static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	114	{
88b2b32b	115	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
1da177e4 LT	116	}
1da177e4 LT	117
ac95beed	118	static u8 __devinit pdc2026x_cable_detect(ide_hwif_t *hwif)
1da177e4	119	{
36501650	120	struct pci_dev *dev = to_pci_dev(hwif->dev);
1bee4d1d	121	u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
49521f97	122
36501650	123	pci_read_config_word(dev, 0x50, &CIS);
49521f97 BZ	124
49521f97 BZ	125	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1da177e4 LT	126	}
	127
	128	/*
	129	* Set the control register to use the 66MHz system
	130	* clock for UDMA 3/4/5 mode operation when necessary.
	131	*
4fce3164 BZ	132	* FIXME: this register is shared by both channels, some locking is needed
4fce3164 BZ	133	*
1da177e4 LT	134	* It may also be possible to leave the 66MHz clock on
	135	* and readjust the timing parameters.
	136	*/
	137	static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
	138	{
1c029fd6	139	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	140	u8 clock = inb(clock_reg);
1da177e4	141
0ecdca26	142	outb(clock \| (hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	143	}
	144
	145	static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
	146	{
1c029fd6	147	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	148	u8 clock = inb(clock_reg);
1da177e4	149
0ecdca26	150	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	151	}
1da177e4 LT	152
f01393e4	153	static void pdc202xx_quirkproc(ide_drive_t *drive)
1da177e4	154	{
d24ec426 SS	155	const char *list, model = drive->id->model;
	156
	157	for (list = pdc_quirk_drives; *list != NULL; list++)
f01393e4 BZ	158	if (strstr(model, *list) != NULL) {
	159	drive->quirk_list = 2;
	160	return;
	161	}
	162
	163	drive->quirk_list = 0;
1da177e4 LT	164	}
	165
	166	static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
	167	{
	168	if (drive->current_speed > XFER_UDMA_2)
	169	pdc_old_enable_66MHz_clock(drive->hwif);
f3d5b34c	170	if (drive->media != ide_disk \|\| drive->addressing == 1) {
1da177e4 LT	171	struct request *rq = HWGROUP(drive)->rq;
1da177e4 LT	172	ide_hwif_t *hwif = HWIF(drive);
1c029fd6	173	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	174	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
1da177e4 LT	175	u32 word_count = 0;
0ecdca26	176	u8 clock = inb(high_16 + 0x11);
1da177e4	177
0ecdca26	178	outb(clock \| (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
1da177e4 LT	179	word_count = (rq->nr_sectors << 8);
	180	word_count = (rq_data_dir(rq) == READ) ?
	181	word_count \| 0x05000000 :
	182	word_count \| 0x06000000;
0ecdca26	183	outl(word_count, atapi_reg);
1da177e4 LT	184	}
	185	ide_dma_start(drive);
	186	}
	187
	188	static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
	189	{
f3d5b34c	190	if (drive->media != ide_disk \|\| drive->addressing == 1) {
1da177e4	191	ide_hwif_t *hwif = HWIF(drive);
1c029fd6	192	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	193	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
	194	u8 clock = 0;
	195
0ecdca26 BZ	196	outl(0, atapi_reg); /* zero out extra */
	197	clock = inb(high_16 + 0x11);
	198	outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
1da177e4 LT	199	}
	200	if (drive->current_speed > XFER_UDMA_2)
	201	pdc_old_disable_66MHz_clock(drive->hwif);
	202	return __ide_dma_end(drive);
	203	}
	204
	205	static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
	206	{
	207	ide_hwif_t *hwif = HWIF(drive);
1c029fd6	208	unsigned long high_16 = hwif->extra_base - 16;
0ecdca26 BZ	209	u8 dma_stat = inb(hwif->dma_status);
0ecdca26 BZ	210	u8 sc1d = inb(high_16 + 0x001d);
1da177e4 LT	211
	212	if (hwif->channel) {
	213	/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
	214	if ((sc1d & 0x50) == 0x50)
	215	goto somebody_else;
	216	else if ((sc1d & 0x40) == 0x40)
	217	return (dma_stat & 4) == 4;
	218	} else {
	219	/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
	220	if ((sc1d & 0x05) == 0x05)
	221	goto somebody_else;
	222	else if ((sc1d & 0x04) == 0x04)
	223	return (dma_stat & 4) == 4;
	224	}
	225	somebody_else:
	226	return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
	227	}
	228
1da177e4 LT	229	static void pdc202xx_reset_host (ide_hwif_t *hwif)
1da177e4 LT	230	{
1c029fd6	231	unsigned long high_16 = hwif->extra_base - 16;
0ecdca26	232	u8 udma_speed_flag = inb(high_16 \| 0x001f);
1da177e4	233
0ecdca26	234	outb(udma_speed_flag \| 0x10, high_16 \| 0x001f);
1da177e4	235	mdelay(100);
0ecdca26	236	outb(udma_speed_flag & ~0x10, high_16 \| 0x001f);
1da177e4 LT	237	mdelay(2000); /* 2 seconds ?! */
	238
	239	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
	240	hwif->channel ? "Secondary" : "Primary");
	241	}
	242
	243	static void pdc202xx_reset (ide_drive_t *drive)
	244	{
	245	ide_hwif_t *hwif = HWIF(drive);
	246	ide_hwif_t *mate = hwif->mate;
26bcb879	247
1da177e4 LT	248	pdc202xx_reset_host(hwif);
1da177e4 LT	249	pdc202xx_reset_host(mate);
26bcb879 BZ	250
26bcb879 BZ	251	ide_set_max_pio(drive);
1da177e4 LT	252	}
1da177e4 LT	253
ac95beed BZ	254	static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
	255	{
	256	pdc202xx_reset(drive);
	257	ide_dma_lost_irq(drive);
	258	}
	259
	260	static void pdc202xx_dma_timeout(ide_drive_t *drive)
	261	{
	262	pdc202xx_reset(drive);
	263	ide_dma_timeout(drive);
	264	}
	265
57e834e2 AC	266	static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
57e834e2 AC	267	const char *name)
1da177e4	268	{
1da177e4 LT	269	return dev->irq;
	270	}
	271
	272	static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
	273	{
36501650 BZ	274	struct pci_dev *dev = to_pci_dev(hwif->dev);
36501650 BZ	275
e98d6e50 BZ	276	if (hwif->dma_base == 0)
	277	return;
	278
841d2a9b	279	hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
c283f5db	280	hwif->dma_timeout = &pdc202xx_dma_timeout;
1da177e4	281
36501650	282	if (dev->device != PCI_DEVICE_ID_PROMISE_20246) {
1da177e4 LT	283	hwif->dma_start = &pdc202xx_old_ide_dma_start;
	284	hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
	285	}
	286	hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
1da177e4 LT	287	}
	288
	289	static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
	290	{
	291	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
	292
	293	if (hwif->channel) {
ecf32796	294	ide_setup_dma(hwif, dmabase);
1da177e4 LT	295	return;
	296	}
	297
0ecdca26 BZ	298	udma_speed_flag = inb(dmabase \| 0x1f);
	299	primary_mode = inb(dmabase \| 0x1a);
	300	secondary_mode = inb(dmabase \| 0x1b);
1da177e4 LT	301	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
	302	"Primary %s Mode " \
	303	"Secondary %s Mode.\n", hwif->cds->name,
	304	(udma_speed_flag & 1) ? "EN" : "DIS",
	305	(primary_mode & 1) ? "MASTER" : "PCI",
	306	(secondary_mode & 1) ? "MASTER" : "PCI" );
	307
1da177e4 LT	308	if (!(udma_speed_flag & 1)) {
	309	printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
	310	hwif->cds->name, udma_speed_flag,
	311	(udma_speed_flag\|1));
0ecdca26 BZ	312	outb(udma_speed_flag \| 1, dmabase \| 0x1f);
0ecdca26 BZ	313	printk("%sACTIVE\n", (inb(dmabase \| 0x1f) & 1) ? "" : "IN");
1da177e4	314	}
1da177e4	315
ecf32796	316	ide_setup_dma(hwif, dmabase);
1da177e4 LT	317	}
1da177e4 LT	318
97f84baa BZ	319	static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
97f84baa BZ	320	const char *name)
1da177e4 LT	321	{
	322	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
	323	u8 irq = 0, irq2 = 0;
	324	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	325	/* 0xbc */
	326	pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)\|0x80, &irq2);
	327	if (irq != irq2) {
	328	pci_write_config_byte(dev,
	329	(PCI_INTERRUPT_LINE)\|0x80, irq); /* 0xbc */
97f84baa BZ	330	printk(KERN_INFO "%s: PCI config space interrupt "
97f84baa BZ	331	"mirror fixed\n", name);
1da177e4 LT	332	}
1da177e4 LT	333	}
1da177e4 LT	334	}
1da177e4 LT	335
4db90a14 BZ	336	#define IDE_HFLAGS_PDC202XX \
	337	(IDE_HFLAG_ERROR_STOPS_FIFO \| \
	338	IDE_HFLAG_ABUSE_SET_DMA_MODE \| \
	339	IDE_HFLAG_OFF_BOARD)
	340
ac95beed BZ	341	static const struct ide_port_ops pdc20246_port_ops = {
	342	.set_pio_mode = pdc202xx_set_pio_mode,
	343	.set_dma_mode = pdc202xx_set_mode,
	344	.quirkproc = pdc202xx_quirkproc,
	345	};
	346
	347	static const struct ide_port_ops pdc2026x_port_ops = {
	348	.set_pio_mode = pdc202xx_set_pio_mode,
	349	.set_dma_mode = pdc202xx_set_mode,
	350	.quirkproc = pdc202xx_quirkproc,
	351	.resetproc = pdc202xx_reset,
	352	.cable_detect = pdc2026x_cable_detect,
	353	};
	354
272a3709	355	#define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
5ef8cb5d BZ	356	{ \
	357	.name = name_str, \
	358	.init_chipset = init_chipset_pdc202xx, \
	359	.init_hwif = init_hwif_pdc202xx, \
	360	.init_dma = init_dma_pdc202xx, \
ac95beed	361	.port_ops = &pdc2026x_port_ops, \
4db90a14	362	.host_flags = IDE_HFLAGS_PDC202XX \| extra_flags, \
5ef8cb5d BZ	363	.pio_mask = ATA_PIO4, \
	364	.mwdma_mask = ATA_MWDMA2, \
	365	.udma_mask = udma, \
	366	}
	367
85620436	368	static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
1da177e4 LT	369	{ /* 0 */
1da177e4 LT	370	.name = "PDC20246",
1da177e4 LT	371	.init_chipset = init_chipset_pdc202xx,
	372	.init_hwif = init_hwif_pdc202xx,
	373	.init_dma = init_dma_pdc202xx,
ac95beed	374	.port_ops = &pdc20246_port_ops,
4db90a14	375	.host_flags = IDE_HFLAGS_PDC202XX,
4099d143	376	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	377	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	378	.udma_mask = ATA_UDMA2,
5ef8cb5d BZ	379	},
5ef8cb5d BZ	380
272a3709 BZ	381	/* 1 */ DECLARE_PDC2026X_DEV("PDC20262", ATA_UDMA4, 0),
	382	/* 2 */ DECLARE_PDC2026X_DEV("PDC20263", ATA_UDMA4, 0),
	383	/* 3 */ DECLARE_PDC2026X_DEV("PDC20265", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
	384	/* 4 */ DECLARE_PDC2026X_DEV("PDC20267", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
1da177e4 LT	385	};
	386
	387	/**
	388	* pdc202xx_init_one - called when a PDC202xx is found
	389	* @dev: the pdc202xx device
	390	* @id: the matching pci id
	391	*
	392	* Called when the PCI registration layer (or the IDE initialization)
	393	* finds a device matching our IDE device tables.
	394	*/
	395
	396	static int __devinit pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
	397	{
85620436	398	const struct ide_port_info *d;
97f84baa BZ	399	u8 idx = id->driver_data;
	400
	401	d = &pdc202xx_chipsets[idx];
	402
	403	if (idx < 3)
	404	pdc202ata4_fixup_irq(dev, d->name);
	405
	406	if (idx == 3) {
	407	struct pci_dev *bridge = dev->bus->self;
1da177e4	408
97f84baa BZ	409	if (bridge &&
	410	bridge->vendor == PCI_VENDOR_ID_INTEL &&
	411	(bridge->device == PCI_DEVICE_ID_INTEL_I960 \|\|
	412	bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
	413	printk(KERN_INFO "ide: Skipping Promise PDC20265 "
	414	"attached to I2O RAID controller\n");
	415	return -ENODEV;
	416	}
	417	}
	418
	419	return ide_setup_pci_device(dev, d);
1da177e4 LT	420	}
1da177e4 LT	421
9cbcc5e3 BZ	422	static const struct pci_device_id pdc202xx_pci_tbl[] = {
	423	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	424	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	425	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
	426	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
	427	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
1da177e4 LT	428	{ 0, },
	429	};
	430	MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
	431
	432	static struct pci_driver driver = {
	433	.name = "Promise_Old_IDE",
	434	.id_table = pdc202xx_pci_tbl,
	435	.probe = pdc202xx_init_one,
	436	};
	437
82ab1eec	438	static int __init pdc202xx_ide_init(void)
1da177e4 LT	439	{
	440	return ide_pci_register_driver(&driver);
	441	}
	442
	443	module_init(pdc202xx_ide_init);
	444
	445	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	446	MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
	447	MODULE_LICENSE("GPL");