[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / pdc202xx_old.c

/*
 *  linux/drivers/ide/pci/pdc202xx_old.c	Version 0.52	Aug 27, 2007
 *
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007		MontaVista Software, Inc.
 *  Copyright (C) 2007			Bartlomiej Zolnierkiewicz
 *
 *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
 *  compiled into the kernel if you have more than one card installed.
 *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
 *  safe chipset tuning, including this support is harmless
 *
 *  Promise Ultra66 cards with BIOS v1.11 this
 *  compiled into the kernel if you have more than one card installed.
 *
 *  Promise Ultra100 cards.
 *
 *  The latest chipset code will support the following ::
 *  Three Ultra33 controllers and 12 drives.
 *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
 *  The 8/4 ratio is a BIOS code limit by promise.
 *
 *  UNLESS you enable "CONFIG_PDC202XX_BURST"
 *
 */

/*
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/irq.h>

#define PDC202XX_DEBUG_DRIVE_INFO	0

static const char *pdc_quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP KA9.1",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP KX13.6",
	"QUANTUM FIREBALLP KX20.5",
	"QUANTUM FIREBALLP KX27.3",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static void pdc_old_disable_66MHz_clock(ide_hwif_t *);

static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 drive_pci		= 0x60 + (drive->dn << 2);

	u8			AP = 0, BP = 0, CP = 0;
	u8			TA = 0, TB = 0, TC = 0;

#if PDC202XX_DEBUG_DRIVE_INFO
	u32			drive_conf = 0;
	pci_read_config_dword(dev, drive_pci, &drive_conf);
#endif

	/*
	 * TODO: do this once per channel
	 */
	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
		pdc_old_disable_66MHz_clock(hwif);

	pci_read_config_byte(dev, drive_pci,     &AP);
	pci_read_config_byte(dev, drive_pci + 1, &BP);
	pci_read_config_byte(dev, drive_pci + 2, &CP);

	switch(speed) {
		case XFER_UDMA_5:
		case XFER_UDMA_4:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_2:	TB = 0x20; TC = 0x01; break;
		case XFER_UDMA_3:
		case XFER_UDMA_1:	TB = 0x40; TC = 0x02; break;
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:	TB = 0x60; TC = 0x03; break;
		case XFER_MW_DMA_1:	TB = 0x60; TC = 0x04; break;
		case XFER_MW_DMA_0:	TB = 0xE0; TC = 0x0F; break;
		case XFER_PIO_4:	TA = 0x01; TB = 0x04; break;
		case XFER_PIO_3:	TA = 0x02; TB = 0x06; break;
		case XFER_PIO_2:	TA = 0x03; TB = 0x08; break;
		case XFER_PIO_1:	TA = 0x05; TB = 0x0C; break;
		case XFER_PIO_0:
		default:		TA = 0x09; TB = 0x13; break;
	}

	if (speed < XFER_SW_DMA_0) {
		/*
		 * preserve SYNC_INT / ERDDY_EN bits while clearing
		 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
		 */
		AP &= ~0x3f;
		if (drive->id->capability & 4)
			AP |= 0x20;	/* set IORDY_EN bit */
		if (drive->media == ide_disk)
			AP |= 0x10;	/* set Prefetch_EN bit */
		/* clear PB[4:0] bits of register B */
		BP &= ~0x1f;
		pci_write_config_byte(dev, drive_pci,     AP | TA);
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
	} else {
		/* clear MB[2:0] bits of register B */
		BP &= ~0xe0;
		/* clear MC[3:0] bits of register C */
		CP &= ~0x0f;
		pci_write_config_byte(dev, drive_pci + 1, BP | TB);
		pci_write_config_byte(dev, drive_pci + 2, CP | TC);
	}

#if PDC202XX_DEBUG_DRIVE_INFO
	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
		drive->name, ide_xfer_verbose(speed),
		drive->dn, drive_conf);
	pci_read_config_dword(dev, drive_pci, &drive_conf);
	printk("0x%08x\n", drive_conf);
#endif
}

static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
}

static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
{
	u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);

	pci_read_config_word(hwif->pci_dev, 0x50, &CIS);

	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

/*
 * Set the control register to use the 66MHz system
 * clock for UDMA 3/4/5 mode operation when necessary.
 *
 * FIXME: this register is shared by both channels, some locking is needed
 *
 * It may also be possible to leave the 66MHz clock on
 * and readjust the timing parameters.
 */
static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
{
	unsigned long clock_reg = hwif->extra_base + 0x01;
	u8 clock = inb(clock_reg);

	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
}

static void pdc202xx_quirkproc(ide_drive_t *drive)
{
	const char **list, *model = drive->id->model;

	for (list = pdc_quirk_drives; *list != NULL; list++)
		if (strstr(model, *list) != NULL) {
			drive->quirk_list = 2;
			return;
		}

	drive->quirk_list = 0;
}

static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
{
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_enable_66MHz_clock(drive->hwif);
	if (drive->media != ide_disk || drive->addressing == 1) {
		struct request *rq	= HWGROUP(drive)->rq;
		ide_hwif_t *hwif	= HWIF(drive);
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u32 word_count	= 0;
		u8 clock = inb(high_16 + 0x11);

		outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
		word_count = (rq->nr_sectors << 8);
		word_count = (rq_data_dir(rq) == READ) ?
					word_count | 0x05000000 :
					word_count | 0x06000000;
		outl(word_count, atapi_reg);
	}
	ide_dma_start(drive);
}

static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
{
	if (drive->media != ide_disk || drive->addressing == 1) {
		ide_hwif_t *hwif	= HWIF(drive);
		unsigned long high_16	= hwif->extra_base - 16;
		unsigned long atapi_reg	= high_16 + (hwif->channel ? 0x24 : 0x20);
		u8 clock		= 0;

		outl(0, atapi_reg); /* zero out extra */
		clock = inb(high_16 + 0x11);
		outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
	}
	if (drive->current_speed > XFER_UDMA_2)
		pdc_old_disable_66MHz_clock(drive->hwif);
	return __ide_dma_end(drive);
}

static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	unsigned long high_16	= hwif->extra_base - 16;
	u8 dma_stat		= inb(hwif->dma_status);
	u8 sc1d			= inb(high_16 + 0x001d);

	if (hwif->channel) {
		/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
		if ((sc1d & 0x50) == 0x50)
			goto somebody_else;
		else if ((sc1d & 0x40) == 0x40)
			return (dma_stat & 4) == 4;
	} else {
		/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
		if ((sc1d & 0x05) == 0x05)
			goto somebody_else;
		else if ((sc1d & 0x04) == 0x04)
			return (dma_stat & 4) == 4;
	}
somebody_else:
	return (dma_stat & 4) == 4;	/* return 1 if INTR asserted */
}

static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);

	if (hwif->resetproc != NULL)
		hwif->resetproc(drive);

	ide_dma_lost_irq(drive);
}

static void pdc202xx_dma_timeout(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);

	if (hwif->resetproc != NULL)
		hwif->resetproc(drive);

	ide_dma_timeout(drive);
}

static void pdc202xx_reset_host (ide_hwif_t *hwif)
{
	unsigned long high_16	= hwif->extra_base - 16;
	u8 udma_speed_flag	= inb(high_16 | 0x001f);

	outb(udma_speed_flag | 0x10, high_16 | 0x001f);
	mdelay(100);
	outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
	mdelay(2000);	/* 2 seconds ?! */

	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
		hwif->channel ? "Secondary" : "Primary");
}

static void pdc202xx_reset (ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	ide_hwif_t *mate	= hwif->mate;

	pdc202xx_reset_host(hwif);
	pdc202xx_reset_host(mate);

	ide_set_max_pio(drive);
}

static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
							const char *name)
{
	return dev->irq;
}

static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &pdc202xx_set_pio_mode;
	hwif->set_dma_mode = &pdc202xx_set_mode;

	hwif->quirkproc = &pdc202xx_quirkproc;

	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
		hwif->resetproc = &pdc202xx_reset;

	if (hwif->dma_base == 0)
		return;

	hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
	hwif->dma_timeout = &pdc202xx_dma_timeout;

	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
		if (hwif->cbl != ATA_CBL_PATA40_SHORT)
			hwif->cbl = pdc202xx_old_cable_detect(hwif);

		hwif->dma_start = &pdc202xx_old_ide_dma_start;
		hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
	} 
	hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
}

static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
{
	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;

	if (hwif->channel) {
		ide_setup_dma(hwif, dmabase);
		return;
	}

	udma_speed_flag	= inb(dmabase | 0x1f);
	primary_mode	= inb(dmabase | 0x1a);
	secondary_mode	= inb(dmabase | 0x1b);
	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
		"Primary %s Mode " \
		"Secondary %s Mode.\n", hwif->cds->name,
		(udma_speed_flag & 1) ? "EN" : "DIS",
		(primary_mode & 1) ? "MASTER" : "PCI",
		(secondary_mode & 1) ? "MASTER" : "PCI" );

#ifdef CONFIG_PDC202XX_BURST
	if (!(udma_speed_flag & 1)) {
		printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
			hwif->cds->name, udma_speed_flag,
			(udma_speed_flag|1));
		outb(udma_speed_flag | 1, dmabase | 0x1f);
		printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
	}
#endif /* CONFIG_PDC202XX_BURST */

	ide_setup_dma(hwif, dmabase);
}

static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
					   const char *name)
{
	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
		u8 irq = 0, irq2 = 0;
		pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
		/* 0xbc */
		pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
		if (irq != irq2) {
			pci_write_config_byte(dev,
				(PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
			printk(KERN_INFO "%s: PCI config space interrupt "
					 "mirror fixed\n", name);
		}
	}
}

#define IDE_HFLAGS_PDC202XX \
	(IDE_HFLAG_ERROR_STOPS_FIFO | \
	 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
	 IDE_HFLAG_OFF_BOARD)

#define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
	{ \
		.name		= name_str, \
		.init_chipset	= init_chipset_pdc202xx, \
		.init_hwif	= init_hwif_pdc202xx, \
		.init_dma	= init_dma_pdc202xx, \
		.extra		= 48, \
		.host_flags	= IDE_HFLAGS_PDC202XX | extra_flags, \
		.pio_mask	= ATA_PIO4, \
		.mwdma_mask	= ATA_MWDMA2, \
		.udma_mask	= udma, \
	}

static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "PDC20246",
		.init_chipset	= init_chipset_pdc202xx,
		.init_hwif	= init_hwif_pdc202xx,
		.init_dma	= init_dma_pdc202xx,
		.extra		= 16,
		.host_flags	= IDE_HFLAGS_PDC202XX,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},

	/* 1 */ DECLARE_PDC2026X_DEV("PDC20262", ATA_UDMA4, 0),
	/* 2 */ DECLARE_PDC2026X_DEV("PDC20263", ATA_UDMA4, 0),
	/* 3 */ DECLARE_PDC2026X_DEV("PDC20265", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
	/* 4 */ DECLARE_PDC2026X_DEV("PDC20267", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
};

/**
 *	pdc202xx_init_one	-	called when a PDC202xx is found
 *	@dev: the pdc202xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	const struct ide_port_info *d;
	u8 idx = id->driver_data;

	d = &pdc202xx_chipsets[idx];

	if (idx < 3)
		pdc202ata4_fixup_irq(dev, d->name);

	if (idx == 3) {
		struct pci_dev *bridge = dev->bus->self;

		if (bridge &&
		    bridge->vendor == PCI_VENDOR_ID_INTEL &&
		    (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
		     bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
			printk(KERN_INFO "ide: Skipping Promise PDC20265 "
				"attached to I2O RAID controller\n");
			return -ENODEV;
		}
	}

	return ide_setup_pci_device(dev, d);
}

static const struct pci_device_id pdc202xx_pci_tbl[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);

static struct pci_driver driver = {
	.name		= "Promise_Old_IDE",
	.id_table	= pdc202xx_pci_tbl,
	.probe		= pdc202xx_init_one,
};

static int __init pdc202xx_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(pdc202xx_ide_init);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
9adf768a	2	* linux/drivers/ide/pci/pdc202xx_old.c Version 0.52 Aug 27, 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
fed21641	5	* Copyright (C) 2006-2007 MontaVista Software, Inc.
4fce3164	6	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	7	*
	8	* Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
	9	* compiled into the kernel if you have more than one card installed.
	10	* Note that BIOS v1.29 is reported to fix the problem. Since this is
	11	* safe chipset tuning, including this support is harmless
	12	*
	13	* Promise Ultra66 cards with BIOS v1.11 this
	14	* compiled into the kernel if you have more than one card installed.
	15	*
	16	* Promise Ultra100 cards.
	17	*
	18	* The latest chipset code will support the following ::
	19	* Three Ultra33 controllers and 12 drives.
	20	* 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
	21	* The 8/4 ratio is a BIOS code limit by promise.
	22	*
	23	* UNLESS you enable "CONFIG_PDC202XX_BURST"
	24	*
	25	*/
	26
	27	/*
	28	* Portions Copyright (C) 1999 Promise Technology, Inc.
	29	* Author: Frank Tiernan (frankt@promise.com)
	30	* Released under terms of General Public License
	31	*/
	32
1da177e4 LT	33	#include <linux/types.h>
	34	#include <linux/module.h>
	35	#include <linux/kernel.h>
	36	#include <linux/delay.h>
	37	#include <linux/timer.h>
	38	#include <linux/mm.h>
	39	#include <linux/ioport.h>
	40	#include <linux/blkdev.h>
	41	#include <linux/hdreg.h>
	42	#include <linux/interrupt.h>
	43	#include <linux/pci.h>
	44	#include <linux/init.h>
	45	#include <linux/ide.h>
	46
	47	#include <asm/io.h>
	48	#include <asm/irq.h>
	49
1da177e4 LT	50	#define PDC202XX_DEBUG_DRIVE_INFO 0
	51
	52	static const char *pdc_quirk_drives[] = {
	53	"QUANTUM FIREBALLlct08 08",
	54	"QUANTUM FIREBALLP KA6.4",
	55	"QUANTUM FIREBALLP KA9.1",
	56	"QUANTUM FIREBALLP LM20.4",
	57	"QUANTUM FIREBALLP KX13.6",
	58	"QUANTUM FIREBALLP KX20.5",
	59	"QUANTUM FIREBALLP KX27.3",
	60	"QUANTUM FIREBALLP LM20.5",
	61	NULL
	62	};
	63
4fce3164	64	static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
1da177e4	65
88b2b32b	66	static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	67	{
	68	ide_hwif_t *hwif = HWIF(drive);
	69	struct pci_dev *dev = hwif->pci_dev;
	70	u8 drive_pci = 0x60 + (drive->dn << 2);
1da177e4	71
4fce3164	72	u8 AP = 0, BP = 0, CP = 0;
1da177e4 LT	73	u8 TA = 0, TB = 0, TC = 0;
1da177e4 LT	74
4fce3164 BZ	75	#if PDC202XX_DEBUG_DRIVE_INFO
4fce3164 BZ	76	u32 drive_conf = 0;
1da177e4	77	pci_read_config_dword(dev, drive_pci, &drive_conf);
4fce3164	78	#endif
1da177e4	79
4fce3164 BZ	80	/*
	81	* TODO: do this once per channel
	82	*/
	83	if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
	84	pdc_old_disable_66MHz_clock(hwif);
1da177e4	85
4fce3164 BZ	86	pci_read_config_byte(dev, drive_pci, &AP);
	87	pci_read_config_byte(dev, drive_pci + 1, &BP);
	88	pci_read_config_byte(dev, drive_pci + 2, &CP);
1da177e4 LT	89
1da177e4 LT	90	switch(speed) {
1da177e4 LT	91	case XFER_UDMA_5:
	92	case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
	93	case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
	94	case XFER_UDMA_3:
	95	case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
	96	case XFER_UDMA_0:
	97	case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
	98	case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
4fce3164	99	case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
1da177e4 LT	100	case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
	101	case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
	102	case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
	103	case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
	104	case XFER_PIO_0:
	105	default: TA = 0x09; TB = 0x13; break;
	106	}
	107
	108	if (speed < XFER_SW_DMA_0) {
4fce3164 BZ	109	/*
	110	* preserve SYNC_INT / ERDDY_EN bits while clearing
	111	* Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
	112	*/
	113	AP &= ~0x3f;
	114	if (drive->id->capability & 4)
	115	AP \|= 0x20; /* set IORDY_EN bit */
	116	if (drive->media == ide_disk)
	117	AP \|= 0x10; /* set Prefetch_EN bit */
	118	/* clear PB[4:0] bits of register B */
	119	BP &= ~0x1f;
	120	pci_write_config_byte(dev, drive_pci, AP \| TA);
	121	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
1da177e4	122	} else {
4fce3164 BZ	123	/* clear MB[2:0] bits of register B */
	124	BP &= ~0xe0;
	125	/* clear MC[3:0] bits of register C */
	126	CP &= ~0x0f;
	127	pci_write_config_byte(dev, drive_pci + 1, BP \| TB);
	128	pci_write_config_byte(dev, drive_pci + 2, CP \| TC);
1da177e4 LT	129	}
	130
	131	#if PDC202XX_DEBUG_DRIVE_INFO
	132	printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
	133	drive->name, ide_xfer_verbose(speed),
	134	drive->dn, drive_conf);
4fce3164	135	pci_read_config_dword(dev, drive_pci, &drive_conf);
1da177e4	136	printk("0x%08x\n", drive_conf);
4fce3164	137	#endif
1da177e4 LT	138	}
1da177e4 LT	139
26bcb879	140	static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	141	{
88b2b32b	142	pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
1da177e4 LT	143	}
	144
	145	static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
	146	{
	147	u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
49521f97	148
1da177e4	149	pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
49521f97 BZ	150
49521f97 BZ	151	return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1da177e4 LT	152	}
	153
	154	/*
	155	* Set the control register to use the 66MHz system
	156	* clock for UDMA 3/4/5 mode operation when necessary.
	157	*
4fce3164 BZ	158	* FIXME: this register is shared by both channels, some locking is needed
4fce3164 BZ	159	*
1da177e4 LT	160	* It may also be possible to leave the 66MHz clock on
	161	* and readjust the timing parameters.
	162	*/
	163	static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
	164	{
1c029fd6	165	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	166	u8 clock = inb(clock_reg);
1da177e4	167
0ecdca26	168	outb(clock \| (hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	169	}
	170
	171	static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
	172	{
1c029fd6	173	unsigned long clock_reg = hwif->extra_base + 0x01;
0ecdca26	174	u8 clock = inb(clock_reg);
1da177e4	175
0ecdca26	176	outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
1da177e4 LT	177	}
1da177e4 LT	178
f01393e4	179	static void pdc202xx_quirkproc(ide_drive_t *drive)
1da177e4	180	{
d24ec426 SS	181	const char *list, model = drive->id->model;
	182
	183	for (list = pdc_quirk_drives; *list != NULL; list++)
f01393e4 BZ	184	if (strstr(model, *list) != NULL) {
	185	drive->quirk_list = 2;
	186	return;
	187	}
	188
	189	drive->quirk_list = 0;
1da177e4 LT	190	}
	191
	192	static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
	193	{
	194	if (drive->current_speed > XFER_UDMA_2)
	195	pdc_old_enable_66MHz_clock(drive->hwif);
f3d5b34c	196	if (drive->media != ide_disk \|\| drive->addressing == 1) {
1da177e4 LT	197	struct request *rq = HWGROUP(drive)->rq;
1da177e4 LT	198	ide_hwif_t *hwif = HWIF(drive);
1c029fd6	199	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	200	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
1da177e4 LT	201	u32 word_count = 0;
0ecdca26	202	u8 clock = inb(high_16 + 0x11);
1da177e4	203
0ecdca26	204	outb(clock \| (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
1da177e4 LT	205	word_count = (rq->nr_sectors << 8);
	206	word_count = (rq_data_dir(rq) == READ) ?
	207	word_count \| 0x05000000 :
	208	word_count \| 0x06000000;
0ecdca26	209	outl(word_count, atapi_reg);
1da177e4 LT	210	}
	211	ide_dma_start(drive);
	212	}
	213
	214	static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
	215	{
f3d5b34c	216	if (drive->media != ide_disk \|\| drive->addressing == 1) {
1da177e4	217	ide_hwif_t *hwif = HWIF(drive);
1c029fd6	218	unsigned long high_16 = hwif->extra_base - 16;
1da177e4 LT	219	unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
	220	u8 clock = 0;
	221
0ecdca26 BZ	222	outl(0, atapi_reg); /* zero out extra */
	223	clock = inb(high_16 + 0x11);
	224	outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
1da177e4 LT	225	}
	226	if (drive->current_speed > XFER_UDMA_2)
	227	pdc_old_disable_66MHz_clock(drive->hwif);
	228	return __ide_dma_end(drive);
	229	}
	230
	231	static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
	232	{
	233	ide_hwif_t *hwif = HWIF(drive);
1c029fd6	234	unsigned long high_16 = hwif->extra_base - 16;
0ecdca26 BZ	235	u8 dma_stat = inb(hwif->dma_status);
0ecdca26 BZ	236	u8 sc1d = inb(high_16 + 0x001d);
1da177e4 LT	237
	238	if (hwif->channel) {
	239	/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
	240	if ((sc1d & 0x50) == 0x50)
	241	goto somebody_else;
	242	else if ((sc1d & 0x40) == 0x40)
	243	return (dma_stat & 4) == 4;
	244	} else {
	245	/* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
	246	if ((sc1d & 0x05) == 0x05)
	247	goto somebody_else;
	248	else if ((sc1d & 0x04) == 0x04)
	249	return (dma_stat & 4) == 4;
	250	}
	251	somebody_else:
	252	return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
	253	}
	254
841d2a9b	255	static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
1da177e4	256	{
841d2a9b SS	257	ide_hwif_t *hwif = HWIF(drive);
	258
	259	if (hwif->resetproc != NULL)
	260	hwif->resetproc(drive);
	261
	262	ide_dma_lost_irq(drive);
1da177e4 LT	263	}
1da177e4 LT	264
c283f5db	265	static void pdc202xx_dma_timeout(ide_drive_t *drive)
1da177e4	266	{
c283f5db SS	267	ide_hwif_t *hwif = HWIF(drive);
	268
	269	if (hwif->resetproc != NULL)
	270	hwif->resetproc(drive);
	271
	272	ide_dma_timeout(drive);
1da177e4 LT	273	}
	274
	275	static void pdc202xx_reset_host (ide_hwif_t *hwif)
	276	{
1c029fd6	277	unsigned long high_16 = hwif->extra_base - 16;
0ecdca26	278	u8 udma_speed_flag = inb(high_16 \| 0x001f);
1da177e4	279
0ecdca26	280	outb(udma_speed_flag \| 0x10, high_16 \| 0x001f);
1da177e4	281	mdelay(100);
0ecdca26	282	outb(udma_speed_flag & ~0x10, high_16 \| 0x001f);
1da177e4 LT	283	mdelay(2000); /* 2 seconds ?! */
	284
	285	printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
	286	hwif->channel ? "Secondary" : "Primary");
	287	}
	288
	289	static void pdc202xx_reset (ide_drive_t *drive)
	290	{
	291	ide_hwif_t *hwif = HWIF(drive);
	292	ide_hwif_t *mate = hwif->mate;
26bcb879	293
1da177e4 LT	294	pdc202xx_reset_host(hwif);
1da177e4 LT	295	pdc202xx_reset_host(mate);
26bcb879 BZ	296
26bcb879 BZ	297	ide_set_max_pio(drive);
1da177e4 LT	298	}
1da177e4 LT	299
57e834e2 AC	300	static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
57e834e2 AC	301	const char *name)
1da177e4	302	{
1da177e4 LT	303	return dev->irq;
	304	}
	305
	306	static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
	307	{
26bcb879	308	hwif->set_pio_mode = &pdc202xx_set_pio_mode;
88b2b32b	309	hwif->set_dma_mode = &pdc202xx_set_mode;
26bcb879	310
1da177e4 LT	311	hwif->quirkproc = &pdc202xx_quirkproc;
1da177e4 LT	312
8b6ebe01	313	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
1da177e4	314	hwif->resetproc = &pdc202xx_reset;
1da177e4	315
e98d6e50 BZ	316	if (hwif->dma_base == 0)
	317	return;
	318
841d2a9b	319	hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
c283f5db	320	hwif->dma_timeout = &pdc202xx_dma_timeout;
1da177e4 LT	321
1da177e4 LT	322	if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
49521f97 BZ	323	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
	324	hwif->cbl = pdc202xx_old_cable_detect(hwif);
	325
1da177e4 LT	326	hwif->dma_start = &pdc202xx_old_ide_dma_start;
	327	hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
	328	}
	329	hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
1da177e4 LT	330	}
	331
	332	static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
	333	{
	334	u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
	335
	336	if (hwif->channel) {
ecf32796	337	ide_setup_dma(hwif, dmabase);
1da177e4 LT	338	return;
	339	}
	340
0ecdca26 BZ	341	udma_speed_flag = inb(dmabase \| 0x1f);
	342	primary_mode = inb(dmabase \| 0x1a);
	343	secondary_mode = inb(dmabase \| 0x1b);
1da177e4 LT	344	printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
	345	"Primary %s Mode " \
	346	"Secondary %s Mode.\n", hwif->cds->name,
	347	(udma_speed_flag & 1) ? "EN" : "DIS",
	348	(primary_mode & 1) ? "MASTER" : "PCI",
	349	(secondary_mode & 1) ? "MASTER" : "PCI" );
	350
	351	#ifdef CONFIG_PDC202XX_BURST
	352	if (!(udma_speed_flag & 1)) {
	353	printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
	354	hwif->cds->name, udma_speed_flag,
	355	(udma_speed_flag\|1));
0ecdca26 BZ	356	outb(udma_speed_flag \| 1, dmabase \| 0x1f);
0ecdca26 BZ	357	printk("%sACTIVE\n", (inb(dmabase \| 0x1f) & 1) ? "" : "IN");
1da177e4 LT	358	}
1da177e4 LT	359	#endif /* CONFIG_PDC202XX_BURST */
1da177e4	360
ecf32796	361	ide_setup_dma(hwif, dmabase);
1da177e4 LT	362	}
1da177e4 LT	363
97f84baa BZ	364	static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
97f84baa BZ	365	const char *name)
1da177e4 LT	366	{
	367	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
	368	u8 irq = 0, irq2 = 0;
	369	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
	370	/* 0xbc */
	371	pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)\|0x80, &irq2);
	372	if (irq != irq2) {
	373	pci_write_config_byte(dev,
	374	(PCI_INTERRUPT_LINE)\|0x80, irq); /* 0xbc */
97f84baa BZ	375	printk(KERN_INFO "%s: PCI config space interrupt "
97f84baa BZ	376	"mirror fixed\n", name);
1da177e4 LT	377	}
1da177e4 LT	378	}
1da177e4 LT	379	}
1da177e4 LT	380
4db90a14 BZ	381	#define IDE_HFLAGS_PDC202XX \
	382	(IDE_HFLAG_ERROR_STOPS_FIFO \| \
	383	IDE_HFLAG_ABUSE_SET_DMA_MODE \| \
	384	IDE_HFLAG_OFF_BOARD)
	385
272a3709	386	#define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
5ef8cb5d BZ	387	{ \
	388	.name = name_str, \
	389	.init_chipset = init_chipset_pdc202xx, \
	390	.init_hwif = init_hwif_pdc202xx, \
	391	.init_dma = init_dma_pdc202xx, \
	392	.extra = 48, \
4db90a14	393	.host_flags = IDE_HFLAGS_PDC202XX \| extra_flags, \
5ef8cb5d BZ	394	.pio_mask = ATA_PIO4, \
	395	.mwdma_mask = ATA_MWDMA2, \
	396	.udma_mask = udma, \
	397	}
	398
85620436	399	static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
1da177e4 LT	400	{ /* 0 */
1da177e4 LT	401	.name = "PDC20246",
1da177e4 LT	402	.init_chipset = init_chipset_pdc202xx,
	403	.init_hwif = init_hwif_pdc202xx,
	404	.init_dma = init_dma_pdc202xx,
1da177e4	405	.extra = 16,
4db90a14	406	.host_flags = IDE_HFLAGS_PDC202XX,
4099d143	407	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	408	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	409	.udma_mask = ATA_UDMA2,
5ef8cb5d BZ	410	},
5ef8cb5d BZ	411
272a3709 BZ	412	/* 1 */ DECLARE_PDC2026X_DEV("PDC20262", ATA_UDMA4, 0),
	413	/* 2 */ DECLARE_PDC2026X_DEV("PDC20263", ATA_UDMA4, 0),
	414	/* 3 */ DECLARE_PDC2026X_DEV("PDC20265", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
	415	/* 4 */ DECLARE_PDC2026X_DEV("PDC20267", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
1da177e4 LT	416	};
	417
	418	/**
	419	* pdc202xx_init_one - called when a PDC202xx is found
	420	* @dev: the pdc202xx device
	421	* @id: the matching pci id
	422	*
	423	* Called when the PCI registration layer (or the IDE initialization)
	424	* finds a device matching our IDE device tables.
	425	*/
	426
	427	static int __devinit pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
	428	{
85620436	429	const struct ide_port_info *d;
97f84baa BZ	430	u8 idx = id->driver_data;
	431
	432	d = &pdc202xx_chipsets[idx];
	433
	434	if (idx < 3)
	435	pdc202ata4_fixup_irq(dev, d->name);
	436
	437	if (idx == 3) {
	438	struct pci_dev *bridge = dev->bus->self;
1da177e4	439
97f84baa BZ	440	if (bridge &&
	441	bridge->vendor == PCI_VENDOR_ID_INTEL &&
	442	(bridge->device == PCI_DEVICE_ID_INTEL_I960 \|\|
	443	bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
	444	printk(KERN_INFO "ide: Skipping Promise PDC20265 "
	445	"attached to I2O RAID controller\n");
	446	return -ENODEV;
	447	}
	448	}
	449
	450	return ide_setup_pci_device(dev, d);
1da177e4 LT	451	}
1da177e4 LT	452
9cbcc5e3 BZ	453	static const struct pci_device_id pdc202xx_pci_tbl[] = {
	454	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	455	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	456	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
	457	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
	458	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
1da177e4 LT	459	{ 0, },
	460	};
	461	MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
	462
	463	static struct pci_driver driver = {
	464	.name = "Promise_Old_IDE",
	465	.id_table = pdc202xx_pci_tbl,
	466	.probe = pdc202xx_init_one,
	467	};
	468
82ab1eec	469	static int __init pdc202xx_ide_init(void)
1da177e4 LT	470	{
	471	return ide_pci_register_driver(&driver);
	472	}
	473
	474	module_init(pdc202xx_ide_init);
	475
	476	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	477	MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
	478	MODULE_LICENSE("GPL");