[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / pdc202xx_new.c

/*
 *  Promise TX2/TX4/TX2000/133 IDE driver
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 *  Split from:
 *  linux/drivers/ide/pdc202xx.c	Version 0.35	Mar. 30, 2002
 *  Copyright (C) 1998-2002		Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2005-2007		MontaVista Software, Inc.
 *  Portions Copyright (C) 1999 Promise Technology, Inc.
 *  Author: Frank Tiernan (frankt@promise.com)
 *  Released under terms of General Public License
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/irq.h>

#ifdef CONFIG_PPC_PMAC
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#endif

#undef DEBUG

#ifdef DEBUG
#define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
#else
#define DBG(fmt, args...)
#endif

static const char *pdc_quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP KA9.1",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP KX13.6",
	"QUANTUM FIREBALLP KX20.5",
	"QUANTUM FIREBALLP KX27.3",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static u8 max_dma_rate(struct pci_dev *pdev)
{
	u8 mode;

	switch(pdev->device) {
		case PCI_DEVICE_ID_PROMISE_20277:
		case PCI_DEVICE_ID_PROMISE_20276:
		case PCI_DEVICE_ID_PROMISE_20275:
		case PCI_DEVICE_ID_PROMISE_20271:
		case PCI_DEVICE_ID_PROMISE_20269:
			mode = 4;
			break;
		case PCI_DEVICE_ID_PROMISE_20270:
		case PCI_DEVICE_ID_PROMISE_20268:
			mode = 3;
			break;
		default:
			return 0;
	}

	return mode;
}

/**
 * get_indexed_reg - Get indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
{
	u8 value;

	outb(index, hwif->dma_vendor1);
	value = inb(hwif->dma_vendor3);

	DBG("index[%02X] value[%02X]\n", index, value);
	return value;
}

/**
 * set_indexed_reg - Set indexed register
 * @hwif: for the port address
 * @index: index of the indexed register
 */
static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
{
	outb(index, hwif->dma_vendor1);
	outb(value, hwif->dma_vendor3);
	DBG("index[%02X] value[%02X]\n", index, value);
}

/*
 * ATA Timing Tables based on 133 MHz PLL output clock.
 *
 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
 * the timing registers automatically when "set features" command is
 * issued to the device. However, if the PLL output clock is 133 MHz,
 * the following tables must be used.
 */
static struct pio_timing {
	u8 reg0c, reg0d, reg13;
} pio_timings [] = {
	{ 0xfb, 0x2b, 0xac },	/* PIO mode 0, IORDY off, Prefetch off */
	{ 0x46, 0x29, 0xa4 },	/* PIO mode 1, IORDY off, Prefetch off */
	{ 0x23, 0x26, 0x64 },	/* PIO mode 2, IORDY off, Prefetch off */
	{ 0x27, 0x0d, 0x35 },	/* PIO mode 3, IORDY on,  Prefetch off */
	{ 0x23, 0x09, 0x25 },	/* PIO mode 4, IORDY on,  Prefetch off */
};

static struct mwdma_timing {
	u8 reg0e, reg0f;
} mwdma_timings [] = {
	{ 0xdf, 0x5f }, 	/* MWDMA mode 0 */
	{ 0x6b, 0x27 }, 	/* MWDMA mode 1 */
	{ 0x69, 0x25 }, 	/* MWDMA mode 2 */
};

static struct udma_timing {
	u8 reg10, reg11, reg12;
} udma_timings [] = {
	{ 0x4a, 0x0f, 0xd5 },	/* UDMA mode 0 */
	{ 0x3a, 0x0a, 0xd0 },	/* UDMA mode 1 */
	{ 0x2a, 0x07, 0xcd },	/* UDMA mode 2 */
	{ 0x1a, 0x05, 0xcd },	/* UDMA mode 3 */
	{ 0x1a, 0x03, 0xcd },	/* UDMA mode 4 */
	{ 0x1a, 0x02, 0xcb },	/* UDMA mode 5 */
	{ 0x1a, 0x01, 0xcb },	/* UDMA mode 6 */
};

static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	u8 adj			= (drive->dn & 1) ? 0x08 : 0x00;

	/*
	 * IDE core issues SETFEATURES_XFER to the drive first (thanks to
	 * IDE_HFLAG_POST_SET_MODE in ->host_flags).  PDC202xx hardware will
	 * automatically set the timing registers based on 100 MHz PLL output.
	 *
	 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	 * chips, we must override the default register settings...
	 */
	if (max_dma_rate(hwif->pci_dev) == 4) {
		u8 mode = speed & 0x07;

		if (speed >= XFER_UDMA_0) {
			set_indexed_reg(hwif, 0x10 + adj,
					udma_timings[mode].reg10);
			set_indexed_reg(hwif, 0x11 + adj,
					udma_timings[mode].reg11);
			set_indexed_reg(hwif, 0x12 + adj,
					udma_timings[mode].reg12);
		} else {
			set_indexed_reg(hwif, 0x0e + adj,
					mwdma_timings[mode].reg0e);
			set_indexed_reg(hwif, 0x0f + adj,
					mwdma_timings[mode].reg0f);
		}
	} else if (speed == XFER_UDMA_2) {
		/* Set tHOLD bit to 0 if using UDMA mode 2 */
		u8 tmp = get_indexed_reg(hwif, 0x10 + adj);

		set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
 	}
}

static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;

	if (max_dma_rate(hwif->pci_dev) == 4) {
		set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
		set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
		set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
	}
}

static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
{
	if (get_indexed_reg(hwif, 0x0b) & 0x04)
		return ATA_CBL_PATA40;
	else
		return ATA_CBL_PATA80;
}

static int pdcnew_quirkproc(ide_drive_t *drive)
{
	const char **list, *model = drive->id->model;

	for (list = pdc_quirk_drives; *list != NULL; list++)
		if (strstr(model, *list) != NULL)
			return 2;
	return 0;
}

static void pdcnew_reset(ide_drive_t *drive)
{
	/*
	 * Deleted this because it is redundant from the caller.
	 */
	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
		HWIF(drive)->channel ? "Secondary" : "Primary");
}

/**
 * read_counter - Read the byte count registers
 * @dma_base: for the port address
 */
static long __devinit read_counter(u32 dma_base)
{
	u32  pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	u8   cnt0, cnt1, cnt2, cnt3;
	long count = 0, last;
	int  retry = 3;

	do {
		last = count;

		/* Read the current count */
		outb(0x20, pri_dma_base + 0x01);
		cnt0 = inb(pri_dma_base + 0x03);
		outb(0x21, pri_dma_base + 0x01);
		cnt1 = inb(pri_dma_base + 0x03);
		outb(0x20, sec_dma_base + 0x01);
		cnt2 = inb(sec_dma_base + 0x03);
		outb(0x21, sec_dma_base + 0x01);
		cnt3 = inb(sec_dma_base + 0x03);

		count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;

		/*
		 * The 30-bit decrementing counter is read in 4 pieces.
		 * Incorrect value may be read when the most significant bytes
		 * are changing...
		 */
	} while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));

	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
		  cnt0, cnt1, cnt2, cnt3);

	return count;
}

/**
 * detect_pll_input_clock - Detect the PLL input clock in Hz.
 * @dma_base: for the port address
 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
 */
static long __devinit detect_pll_input_clock(unsigned long dma_base)
{
	struct timeval start_time, end_time;
	long start_count, end_count;
	long pll_input, usec_elapsed;
	u8 scr1;

	start_count = read_counter(dma_base);
	do_gettimeofday(&start_time);

	/* Start the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 | 0x40, dma_base + 0x03);

	/* Let the counter run for 10 ms. */
	mdelay(10);

	end_count = read_counter(dma_base);
	do_gettimeofday(&end_time);

	/* Stop the test mode */
	outb(0x01, dma_base + 0x01);
	scr1 = inb(dma_base + 0x03);
	DBG("scr1[%02X]\n", scr1);
	outb(scr1 & ~0x40, dma_base + 0x03);

	/*
	 * Calculate the input clock in Hz
	 * (the clock counter is 30 bit wide and counts down)
	 */
	usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
		(end_time.tv_usec - start_time.tv_usec);
	pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
		(10000000 / usec_elapsed);

	DBG("start[%ld] end[%ld]\n", start_count, end_count);

	return pll_input;
}

#ifdef CONFIG_PPC_PMAC
static void __devinit apple_kiwi_init(struct pci_dev *pdev)
{
	struct device_node *np = pci_device_to_OF_node(pdev);
	u8 conf;

	if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
		return;

	if (pdev->revision >= 0x03) {
		/* Setup chip magic config stuff (from darwin) */
		pci_read_config_byte (pdev, 0x40, &conf);
		pci_write_config_byte(pdev, 0x40, (conf | 0x01));
	}
}
#endif /* CONFIG_PPC_PMAC */

static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
{
	unsigned long dma_base = pci_resource_start(dev, 4);
	unsigned long sec_dma_base = dma_base + 0x08;
	long pll_input, pll_output, ratio;
	int f, r;
	u8 pll_ctl0, pll_ctl1;

	if (dma_base == 0)
		return -EFAULT;

#ifdef CONFIG_PPC_PMAC
	apple_kiwi_init(dev);
#endif

	/* Calculate the required PLL output frequency */
	switch(max_dma_rate(dev)) {
		case 4: /* it's 133 MHz for Ultra133 chips */
			pll_output = 133333333;
			break;
		case 3: /* and  100 MHz for Ultra100 chips */
		default:
			pll_output = 100000000;
			break;
	}

	/*
	 * Detect PLL input clock.
	 * On some systems, where PCI bus is running at non-standard clock rate
	 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	 * PDC20268 and newer chips employ PLL circuit to help correct timing
	 * registers setting.
	 */
	pll_input = detect_pll_input_clock(dma_base);
	printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);

	/* Sanity check */
	if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
		printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
		       name, pll_input);
		goto out;
	}

#ifdef DEBUG
	DBG("pll_output is %ld Hz\n", pll_output);

	/* Show the current clock value of PLL control register
	 * (maybe already configured by the BIOS)
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

	/*
	 * Calculate the ratio of F, R and NO
	 * POUT = (F + 2) / (( R + 2) * NO)
	 */
	ratio = pll_output / (pll_input / 1000);
	if (ratio < 8600L) { /* 8.6x */
		/* Using NO = 0x01, R = 0x0d */
		r = 0x0d;
	} else if (ratio < 12900L) { /* 12.9x */
		/* Using NO = 0x01, R = 0x08 */
		r = 0x08;
	} else if (ratio < 16100L) { /* 16.1x */
		/* Using NO = 0x01, R = 0x06 */
		r = 0x06;
	} else if (ratio < 64000L) { /* 64x */
		r = 0x00;
	} else {
		/* Invalid ratio */
		printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
		goto out;
	}

	f = (ratio * (r + 2)) / 1000 - 2;

	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);

	if (unlikely(f < 0 || f > 127)) {
		/* Invalid F */
		printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
		goto out;
	}

	pll_ctl0 = (u8) f;
	pll_ctl1 = (u8) r;

	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);

	outb(0x02,     sec_dma_base + 0x01);
	outb(pll_ctl0, sec_dma_base + 0x03);
	outb(0x03,     sec_dma_base + 0x01);
	outb(pll_ctl1, sec_dma_base + 0x03);

	/* Wait the PLL circuit to be stable */
	mdelay(30);

#ifdef DEBUG
	/*
	 *  Show the current clock value of PLL control register
	 */
	outb(0x02, sec_dma_base + 0x01);
	pll_ctl0 = inb(sec_dma_base + 0x03);
	outb(0x03, sec_dma_base + 0x01);
	pll_ctl1 = inb(sec_dma_base + 0x03);

	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
#endif

 out:
	return dev->irq;
}

static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
{
	hwif->set_pio_mode = &pdcnew_set_pio_mode;
	hwif->set_dma_mode = &pdcnew_set_dma_mode;

	hwif->quirkproc = &pdcnew_quirkproc;
	hwif->resetproc = &pdcnew_reset;

	if (hwif->dma_base == 0)
		return;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
		hwif->cbl = pdcnew_cable_detect(hwif);
}

static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
{
	struct pci_dev *dev2;

	dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
						PCI_FUNC(dev->devfn)));

	if (dev2 &&
	    dev2->vendor == dev->vendor &&
	    dev2->device == dev->device) {

		if (dev2->irq != dev->irq) {
			dev2->irq = dev->irq;
			printk(KERN_INFO "PDC20270: PCI config space "
					 "interrupt fixed\n");
		}

		return dev2;
	}

	return NULL;
}

#define DECLARE_PDCNEW_DEV(name_str, udma) \
	{ \
		.name		= name_str, \
		.init_chipset	= init_chipset_pdcnew, \
		.init_hwif	= init_hwif_pdc202new, \
		.host_flags	= IDE_HFLAG_POST_SET_MODE | \
				  IDE_HFLAG_ERROR_STOPS_FIFO | \
				  IDE_HFLAG_OFF_BOARD, \
		.pio_mask	= ATA_PIO4, \
		.mwdma_mask	= ATA_MWDMA2, \
		.udma_mask	= udma, \
	}

static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
	/* 0 */ DECLARE_PDCNEW_DEV("PDC20268", ATA_UDMA5),
	/* 1 */ DECLARE_PDCNEW_DEV("PDC20269", ATA_UDMA6),
	/* 2 */ DECLARE_PDCNEW_DEV("PDC20270", ATA_UDMA5),
	/* 3 */ DECLARE_PDCNEW_DEV("PDC20271", ATA_UDMA6),
	/* 4 */ DECLARE_PDCNEW_DEV("PDC20275", ATA_UDMA6),
	/* 5 */ DECLARE_PDCNEW_DEV("PDC20276", ATA_UDMA6),
	/* 6 */ DECLARE_PDCNEW_DEV("PDC20277", ATA_UDMA6),
};

/**
 *	pdc202new_init_one	-	called when a pdc202xx is found
 *	@dev: the pdc202new device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	const struct ide_port_info *d;
	struct pci_dev *bridge = dev->bus->self;
	u8 idx = id->driver_data;

	d = &pdcnew_chipsets[idx];

	if (idx == 2 && bridge &&
	    bridge->vendor == PCI_VENDOR_ID_DEC &&
	    bridge->device == PCI_DEVICE_ID_DEC_21150) {
		struct pci_dev *dev2;

		if (PCI_SLOT(dev->devfn) & 2)
			return -ENODEV;

		dev2 = pdc20270_get_dev2(dev);

		if (dev2) {
			int ret = ide_setup_pci_devices(dev, dev2, d);
			if (ret < 0)
				pci_dev_put(dev2);
			return ret;
		}
	}

	if (idx == 5 && bridge &&
	    bridge->vendor == PCI_VENDOR_ID_INTEL &&
	    (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
	     bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
		printk(KERN_INFO "PDC20276: attached to I2O RAID controller, "
				 "skipping\n");
		return -ENODEV;
	}

	return ide_setup_pci_device(dev, d);
}

static const struct pci_device_id pdc202new_pci_tbl[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 3 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 4 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 5 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 6 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);

static struct pci_driver driver = {
	.name		= "Promise_IDE",
	.id_table	= pdc202new_pci_tbl,
	.probe		= pdc202new_init_one,
};

static int __init pdc202new_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(pdc202new_ide_init);

MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Promise TX2/TX4/TX2000/133 IDE driver
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*
	9	* Split from:
	10	* linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
	11	* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
35198234	12	* Copyright (C) 2005-2007 MontaVista Software, Inc.
1da177e4 LT	13	* Portions Copyright (C) 1999 Promise Technology, Inc.
	14	* Author: Frank Tiernan (frankt@promise.com)
	15	* Released under terms of General Public License
	16	*/
	17
1da177e4 LT	18	#include <linux/module.h>
	19	#include <linux/types.h>
	20	#include <linux/kernel.h>
	21	#include <linux/delay.h>
	22	#include <linux/timer.h>
	23	#include <linux/mm.h>
	24	#include <linux/ioport.h>
	25	#include <linux/blkdev.h>
	26	#include <linux/hdreg.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/pci.h>
	29	#include <linux/init.h>
	30	#include <linux/ide.h>
	31
	32	#include <asm/io.h>
	33	#include <asm/irq.h>
	34
	35	#ifdef CONFIG_PPC_PMAC
	36	#include <asm/prom.h>
	37	#include <asm/pci-bridge.h>
	38	#endif
	39
47694bb8 SS	40	#undef DEBUG
	41
	42	#ifdef DEBUG
	43	#define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
	44	#else
	45	#define DBG(fmt, args...)
	46	#endif
	47
3c6bee1d	48	static const char *pdc_quirk_drives[] = {
1da177e4 LT	49	"QUANTUM FIREBALLlct08 08",
	50	"QUANTUM FIREBALLP KA6.4",
	51	"QUANTUM FIREBALLP KA9.1",
	52	"QUANTUM FIREBALLP LM20.4",
	53	"QUANTUM FIREBALLP KX13.6",
	54	"QUANTUM FIREBALLP KX20.5",
	55	"QUANTUM FIREBALLP KX27.3",
	56	"QUANTUM FIREBALLP LM20.5",
	57	NULL
	58	};
	59
47694bb8	60	static u8 max_dma_rate(struct pci_dev *pdev)
1da177e4 LT	61	{
	62	u8 mode;
	63
47694bb8	64	switch(pdev->device) {
1da177e4 LT	65	case PCI_DEVICE_ID_PROMISE_20277:
	66	case PCI_DEVICE_ID_PROMISE_20276:
	67	case PCI_DEVICE_ID_PROMISE_20275:
	68	case PCI_DEVICE_ID_PROMISE_20271:
	69	case PCI_DEVICE_ID_PROMISE_20269:
	70	mode = 4;
	71	break;
	72	case PCI_DEVICE_ID_PROMISE_20270:
	73	case PCI_DEVICE_ID_PROMISE_20268:
	74	mode = 3;
	75	break;
	76	default:
	77	return 0;
	78	}
47694bb8	79
1da177e4 LT	80	return mode;
	81	}
	82
47694bb8 SS	83	/**
	84	* get_indexed_reg - Get indexed register
	85	* @hwif: for the port address
	86	* @index: index of the indexed register
	87	*/
	88	static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
	89	{
	90	u8 value;
	91
0ecdca26 BZ	92	outb(index, hwif->dma_vendor1);
0ecdca26 BZ	93	value = inb(hwif->dma_vendor3);
47694bb8 SS	94
	95	DBG("index[%02X] value[%02X]\n", index, value);
	96	return value;
	97	}
	98
	99	/**
	100	* set_indexed_reg - Set indexed register
	101	* @hwif: for the port address
	102	* @index: index of the indexed register
	103	*/
	104	static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
	105	{
0ecdca26 BZ	106	outb(index, hwif->dma_vendor1);
0ecdca26 BZ	107	outb(value, hwif->dma_vendor3);
47694bb8 SS	108	DBG("index[%02X] value[%02X]\n", index, value);
	109	}
	110
	111	/*
	112	* ATA Timing Tables based on 133 MHz PLL output clock.
	113	*
	114	* If the PLL outputs 100 MHz clock, the ASIC hardware will set
	115	* the timing registers automatically when "set features" command is
	116	* issued to the device. However, if the PLL output clock is 133 MHz,
	117	* the following tables must be used.
	118	*/
	119	static struct pio_timing {
	120	u8 reg0c, reg0d, reg13;
	121	} pio_timings [] = {
	122	{ 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
	123	{ 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
	124	{ 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
	125	{ 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
	126	{ 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
	127	};
	128
	129	static struct mwdma_timing {
	130	u8 reg0e, reg0f;
	131	} mwdma_timings [] = {
	132	{ 0xdf, 0x5f }, /* MWDMA mode 0 */
	133	{ 0x6b, 0x27 }, /* MWDMA mode 1 */
	134	{ 0x69, 0x25 }, /* MWDMA mode 2 */
	135	};
	136
	137	static struct udma_timing {
	138	u8 reg10, reg11, reg12;
	139	} udma_timings [] = {
	140	{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
	141	{ 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
	142	{ 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
	143	{ 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
	144	{ 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
	145	{ 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
	146	{ 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
	147	};
	148
ad4ba7dc	149	static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	150	{
1da177e4 LT	151	ide_hwif_t *hwif = HWIF(drive);
47694bb8	152	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
1da177e4	153
47694bb8	154	/*
88b2b32b BZ	155	* IDE core issues SETFEATURES_XFER to the drive first (thanks to
88b2b32b BZ	156	* IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
47694bb8	157	* automatically set the timing registers based on 100 MHz PLL output.
88b2b32b	158	*
47694bb8 SS	159	* As we set up the PLL to output 133 MHz for UltraDMA/133 capable
	160	* chips, we must override the default register settings...
	161	*/
	162	if (max_dma_rate(hwif->pci_dev) == 4) {
	163	u8 mode = speed & 0x07;
	164
4db90a14 BZ	165	if (speed >= XFER_UDMA_0) {
	166	set_indexed_reg(hwif, 0x10 + adj,
	167	udma_timings[mode].reg10);
	168	set_indexed_reg(hwif, 0x11 + adj,
	169	udma_timings[mode].reg11);
	170	set_indexed_reg(hwif, 0x12 + adj,
	171	udma_timings[mode].reg12);
	172	} else {
	173	set_indexed_reg(hwif, 0x0e + adj,
	174	mwdma_timings[mode].reg0e);
	175	set_indexed_reg(hwif, 0x0f + adj,
	176	mwdma_timings[mode].reg0f);
47694bb8 SS	177	}
	178	} else if (speed == XFER_UDMA_2) {
	179	/* Set tHOLD bit to 0 if using UDMA mode 2 */
	180	u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
	181
	182	set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
	183	}
1da177e4 LT	184	}
1da177e4 LT	185
26bcb879	186	static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	187	{
ad4ba7dc BZ	188	ide_hwif_t *hwif = drive->hwif;
	189	u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
	190
	191	if (max_dma_rate(hwif->pci_dev) == 4) {
	192	set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
	193	set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
	194	set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
	195	}
1da177e4 LT	196	}
1da177e4 LT	197
47694bb8	198	static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
1da177e4	199	{
49521f97 BZ	200	if (get_indexed_reg(hwif, 0x0b) & 0x04)
	201	return ATA_CBL_PATA40;
	202	else
	203	return ATA_CBL_PATA80;
1da177e4	204	}
47694bb8	205
47694bb8	206	static int pdcnew_quirkproc(ide_drive_t *drive)
1da177e4	207	{
d24ec426 SS	208	const char *list, model = drive->id->model;
	209
	210	for (list = pdc_quirk_drives; *list != NULL; list++)
	211	if (strstr(model, *list) != NULL)
	212	return 2;
	213	return 0;
1da177e4 LT	214	}
1da177e4 LT	215
47694bb8	216	static void pdcnew_reset(ide_drive_t *drive)
1da177e4 LT	217	{
	218	/*
	219	* Deleted this because it is redundant from the caller.
	220	*/
47694bb8	221	printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
1da177e4 LT	222	HWIF(drive)->channel ? "Secondary" : "Primary");
	223	}
	224
47694bb8 SS	225	/**
	226	* read_counter - Read the byte count registers
	227	* @dma_base: for the port address
	228	*/
	229	static long __devinit read_counter(u32 dma_base)
	230	{
	231	u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
	232	u8 cnt0, cnt1, cnt2, cnt3;
	233	long count = 0, last;
	234	int retry = 3;
	235
	236	do {
	237	last = count;
	238
	239	/* Read the current count */
	240	outb(0x20, pri_dma_base + 0x01);
	241	cnt0 = inb(pri_dma_base + 0x03);
	242	outb(0x21, pri_dma_base + 0x01);
	243	cnt1 = inb(pri_dma_base + 0x03);
	244	outb(0x20, sec_dma_base + 0x01);
	245	cnt2 = inb(sec_dma_base + 0x03);
	246	outb(0x21, sec_dma_base + 0x01);
	247	cnt3 = inb(sec_dma_base + 0x03);
	248
	249	count = (cnt3 << 23) \| (cnt2 << 15) \| (cnt1 << 8) \| cnt0;
	250
	251	/*
	252	* The 30-bit decrementing counter is read in 4 pieces.
	253	* Incorrect value may be read when the most significant bytes
	254	* are changing...
	255	*/
	256	} while (retry-- && (((last ^ count) & 0x3fff8000) \|\| last < count));
	257
	258	DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
	259	cnt0, cnt1, cnt2, cnt3);
	260
	261	return count;
	262	}
	263
	264	/**
	265	* detect_pll_input_clock - Detect the PLL input clock in Hz.
	266	* @dma_base: for the port address
	267	* E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
	268	*/
	269	static long __devinit detect_pll_input_clock(unsigned long dma_base)
	270	{
8006bf56	271	struct timeval start_time, end_time;
47694bb8	272	long start_count, end_count;
8006bf56	273	long pll_input, usec_elapsed;
47694bb8 SS	274	u8 scr1;
	275
	276	start_count = read_counter(dma_base);
8006bf56	277	do_gettimeofday(&start_time);
47694bb8 SS	278
	279	/* Start the test mode */
	280	outb(0x01, dma_base + 0x01);
	281	scr1 = inb(dma_base + 0x03);
	282	DBG("scr1[%02X]\n", scr1);
	283	outb(scr1 \| 0x40, dma_base + 0x03);
	284
	285	/* Let the counter run for 10 ms. */
	286	mdelay(10);
	287
	288	end_count = read_counter(dma_base);
8006bf56	289	do_gettimeofday(&end_time);
47694bb8 SS	290
	291	/* Stop the test mode */
	292	outb(0x01, dma_base + 0x01);
	293	scr1 = inb(dma_base + 0x03);
	294	DBG("scr1[%02X]\n", scr1);
	295	outb(scr1 & ~0x40, dma_base + 0x03);
	296
	297	/*
	298	* Calculate the input clock in Hz
	299	* (the clock counter is 30 bit wide and counts down)
	300	*/
8006bf56 AL	301	usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
8006bf56 AL	302	(end_time.tv_usec - start_time.tv_usec);
56fe23d5	303	pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
8006bf56	304	(10000000 / usec_elapsed);
47694bb8 SS	305
	306	DBG("start[%ld] end[%ld]\n", start_count, end_count);
	307
	308	return pll_input;
	309	}
	310
1da177e4 LT	311	#ifdef CONFIG_PPC_PMAC
	312	static void __devinit apple_kiwi_init(struct pci_dev *pdev)
	313	{
	314	struct device_node *np = pci_device_to_OF_node(pdev);
1da177e4 LT	315	u8 conf;
1da177e4 LT	316
55b61fec	317	if (np == NULL \|\| !of_device_is_compatible(np, "kiwi-root"))
1da177e4 LT	318	return;
1da177e4 LT	319
fc212bb1	320	if (pdev->revision >= 0x03) {
1da177e4	321	/* Setup chip magic config stuff (from darwin) */
47694bb8 SS	322	pci_read_config_byte (pdev, 0x40, &conf);
47694bb8 SS	323	pci_write_config_byte(pdev, 0x40, (conf \| 0x01));
1da177e4	324	}
1da177e4 LT	325	}
	326	#endif /* CONFIG_PPC_PMAC */
	327
	328	static unsigned int __devinit init_chipset_pdcnew(struct pci_dev dev, const char name)
	329	{
47694bb8 SS	330	unsigned long dma_base = pci_resource_start(dev, 4);
	331	unsigned long sec_dma_base = dma_base + 0x08;
	332	long pll_input, pll_output, ratio;
	333	int f, r;
	334	u8 pll_ctl0, pll_ctl1;
	335
01cc643a BZ	336	if (dma_base == 0)
	337	return -EFAULT;
	338
1da177e4 LT	339	#ifdef CONFIG_PPC_PMAC
	340	apple_kiwi_init(dev);
	341	#endif
	342
47694bb8 SS	343	/* Calculate the required PLL output frequency */
	344	switch(max_dma_rate(dev)) {
	345	case 4: /* it's 133 MHz for Ultra133 chips */
	346	pll_output = 133333333;
	347	break;
	348	case 3: /* and 100 MHz for Ultra100 chips */
	349	default:
	350	pll_output = 100000000;
	351	break;
	352	}
	353
	354	/*
	355	* Detect PLL input clock.
	356	* On some systems, where PCI bus is running at non-standard clock rate
	357	* (e.g. 25 or 40 MHz), we have to adjust the cycle time.
	358	* PDC20268 and newer chips employ PLL circuit to help correct timing
	359	* registers setting.
	360	*/
	361	pll_input = detect_pll_input_clock(dma_base);
	362	printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
	363
	364	/* Sanity check */
	365	if (unlikely(pll_input < 5000000L \|\| pll_input > 70000000L)) {
	366	printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
	367	name, pll_input);
	368	goto out;
	369	}
	370
	371	#ifdef DEBUG
	372	DBG("pll_output is %ld Hz\n", pll_output);
	373
	374	/* Show the current clock value of PLL control register
	375	* (maybe already configured by the BIOS)
	376	*/
	377	outb(0x02, sec_dma_base + 0x01);
	378	pll_ctl0 = inb(sec_dma_base + 0x03);
	379	outb(0x03, sec_dma_base + 0x01);
	380	pll_ctl1 = inb(sec_dma_base + 0x03);
	381
	382	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
	383	#endif
	384
	385	/*
	386	* Calculate the ratio of F, R and NO
	387	* POUT = (F + 2) / (( R + 2) * NO)
	388	*/
	389	ratio = pll_output / (pll_input / 1000);
	390	if (ratio < 8600L) { /* 8.6x */
	391	/* Using NO = 0x01, R = 0x0d */
	392	r = 0x0d;
	393	} else if (ratio < 12900L) { /* 12.9x */
	394	/* Using NO = 0x01, R = 0x08 */
	395	r = 0x08;
	396	} else if (ratio < 16100L) { /* 16.1x */
	397	/* Using NO = 0x01, R = 0x06 */
	398	r = 0x06;
	399	} else if (ratio < 64000L) { /* 64x */
	400	r = 0x00;
	401	} else {
	402	/* Invalid ratio */
	403	printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
	404	goto out;
	405	}
	406
407	f = (ratio * (r + 2)) / 1000 - 2;
408
409	DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
410
411	if (unlikely(f < 0 \|\| f > 127)) {
412	/* Invalid F */
413	printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
414	goto out;
415	}
416
417	pll_ctl0 = (u8) f;
418	pll_ctl1 = (u8) r;
419
420	DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
421
422	outb(0x02, sec_dma_base + 0x01);
423	outb(pll_ctl0, sec_dma_base + 0x03);
424	outb(0x03, sec_dma_base + 0x01);
425	outb(pll_ctl1, sec_dma_base + 0x03);
426
427	/* Wait the PLL circuit to be stable */
428	mdelay(30);
429
430	#ifdef DEBUG
431	/*
432	* Show the current clock value of PLL control register
433	*/
434	outb(0x02, sec_dma_base + 0x01);
435	pll_ctl0 = inb(sec_dma_base + 0x03);
436	outb(0x03, sec_dma_base + 0x01);
437	pll_ctl1 = inb(sec_dma_base + 0x03);
438
439	DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
440	#endif
441
442	out:
1da177e4 LT	443	return dev->irq;
	444	}
	445
	446	static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
	447	{
26bcb879	448	hwif->set_pio_mode = &pdcnew_set_pio_mode;
ad4ba7dc	449	hwif->set_dma_mode = &pdcnew_set_dma_mode;
26bcb879	450
1da177e4	451	hwif->quirkproc = &pdcnew_quirkproc;
47694bb8	452	hwif->resetproc = &pdcnew_reset;
1da177e4	453
01cc643a BZ	454	if (hwif->dma_base == 0)
	455	return;
	456
49521f97 BZ	457	if (hwif->cbl != ATA_CBL_PATA40_SHORT)
49521f97 BZ	458	hwif->cbl = pdcnew_cable_detect(hwif);
1da177e4 LT	459	}
1da177e4 LT	460
099b1f42	461	static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
1da177e4	462	{
099b1f42 BZ	463	struct pci_dev *dev2;
099b1f42 BZ	464
eadb6ecf	465	dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
099b1f42	466	PCI_FUNC(dev->devfn)));
eadb6ecf	467
099b1f42 BZ	468	if (dev2 &&
	469	dev2->vendor == dev->vendor &&
	470	dev2->device == dev->device) {
	471
	472	if (dev2->irq != dev->irq) {
	473	dev2->irq = dev->irq;
	474	printk(KERN_INFO "PDC20270: PCI config space "
	475	"interrupt fixed\n");
1da177e4	476	}
07047935	477
099b1f42	478	return dev2;
1da177e4	479	}
099b1f42 BZ	480
099b1f42 BZ	481	return NULL;
1da177e4 LT	482	}
1da177e4 LT	483
05d7e6cb BZ	484	#define DECLARE_PDCNEW_DEV(name_str, udma) \
	485	{ \
	486	.name = name_str, \
	487	.init_chipset = init_chipset_pdcnew, \
	488	.init_hwif = init_hwif_pdc202new, \
	489	.host_flags = IDE_HFLAG_POST_SET_MODE \| \
ed67b923	490	IDE_HFLAG_ERROR_STOPS_FIFO \| \
05d7e6cb BZ	491	IDE_HFLAG_OFF_BOARD, \
	492	.pio_mask = ATA_PIO4, \
	493	.mwdma_mask = ATA_MWDMA2, \
	494	.udma_mask = udma, \
1da177e4	495	}
05d7e6cb	496
85620436	497	static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
05d7e6cb BZ	498	/* 0 */ DECLARE_PDCNEW_DEV("PDC20268", ATA_UDMA5),
	499	/* 1 */ DECLARE_PDCNEW_DEV("PDC20269", ATA_UDMA6),
	500	/* 2 */ DECLARE_PDCNEW_DEV("PDC20270", ATA_UDMA5),
	501	/* 3 */ DECLARE_PDCNEW_DEV("PDC20271", ATA_UDMA6),
	502	/* 4 */ DECLARE_PDCNEW_DEV("PDC20275", ATA_UDMA6),
	503	/* 5 */ DECLARE_PDCNEW_DEV("PDC20276", ATA_UDMA6),
	504	/* 6 */ DECLARE_PDCNEW_DEV("PDC20277", ATA_UDMA6),
1da177e4 LT	505	};
	506
	507	/**
	508	* pdc202new_init_one - called when a pdc202xx is found
	509	* @dev: the pdc202new device
	510	* @id: the matching pci id
	511	*
	512	* Called when the PCI registration layer (or the IDE initialization)
	513	* finds a device matching our IDE device tables.
	514	*/
	515
	516	static int __devinit pdc202new_init_one(struct pci_dev dev, const struct pci_device_id id)
	517	{
85620436	518	const struct ide_port_info *d;
099b1f42 BZ	519	struct pci_dev *bridge = dev->bus->self;
	520	u8 idx = id->driver_data;
	521
	522	d = &pdcnew_chipsets[idx];
	523
	524	if (idx == 2 && bridge &&
	525	bridge->vendor == PCI_VENDOR_ID_DEC &&
	526	bridge->device == PCI_DEVICE_ID_DEC_21150) {
	527	struct pci_dev *dev2;
	528
	529	if (PCI_SLOT(dev->devfn) & 2)
	530	return -ENODEV;
1da177e4	531
099b1f42 BZ	532	dev2 = pdc20270_get_dev2(dev);
	533
	534	if (dev2) {
	535	int ret = ide_setup_pci_devices(dev, dev2, d);
	536	if (ret < 0)
	537	pci_dev_put(dev2);
	538	return ret;
	539	}
	540	}
	541
	542	if (idx == 5 && bridge &&
	543	bridge->vendor == PCI_VENDOR_ID_INTEL &&
	544	(bridge->device == PCI_DEVICE_ID_INTEL_I960 \|\|
	545	bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
	546	printk(KERN_INFO "PDC20276: attached to I2O RAID controller, "
	547	"skipping\n");
	548	return -ENODEV;
	549	}
	550
	551	return ide_setup_pci_device(dev, d);
1da177e4 LT	552	}
1da177e4 LT	553
9cbcc5e3 BZ	554	static const struct pci_device_id pdc202new_pci_tbl[] = {
	555	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
	556	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
	557	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 2 },
	558	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 3 },
	559	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 4 },
	560	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 5 },
	561	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 6 },
1da177e4 LT	562	{ 0, },
	563	};
	564	MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
	565
	566	static struct pci_driver driver = {
	567	.name = "Promise_IDE",
	568	.id_table = pdc202new_pci_tbl,
	569	.probe = pdc202new_init_one,
	570	};
	571
82ab1eec	572	static int __init pdc202new_ide_init(void)
1da177e4 LT	573	{
	574	return ide_pci_register_driver(&driver);
	575	}
	576
	577	module_init(pdc202new_ide_init);
	578
	579	MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
	580	MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
	581	MODULE_LICENSE("GPL");