[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ide / pci / ns87415.c

/*
 * Copyright (C) 1997-1998	Mark Lord <mlord@pobox.com>
 * Copyright (C) 1998		Eddie C. Dost <ecd@skynet.be>
 * Copyright (C) 1999-2000	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2004		Grant Grundler <grundler at parisc-linux.org>
 *
 * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "ns87415"

#ifdef CONFIG_SUPERIO
/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
 * which use the integrated NS87514 cell for CD-ROM support.
 * i.e we have to support for CD-ROM installs.
 * See drivers/parisc/superio.c for more gory details.
 */
#include <asm/superio.h>

#define SUPERIO_IDE_MAX_RETRIES 25

/* Because of a defect in Super I/O, all reads of the PCI DMA status 
 * registers, IDE status register and the IDE select register need to be 
 * retried
 */
static u8 superio_ide_inb (unsigned long port)
{
	u8 tmp;
	int retries = SUPERIO_IDE_MAX_RETRIES;

	/* printk(" [ reading port 0x%x with retry ] ", port); */

	do {
		tmp = inb(port);
		if (tmp == 0)
			udelay(50);
	} while (tmp == 0 && retries-- > 0);

	return tmp;
}

static u8 superio_read_status(ide_hwif_t *hwif)
{
	return superio_ide_inb(hwif->io_ports.status_addr);
}

static u8 superio_read_sff_dma_status(ide_hwif_t *hwif)
{
	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
}

static void superio_tf_read(ide_drive_t *drive, ide_task_t *task)
{
	struct ide_io_ports *io_ports = &drive->hwif->io_ports;
	struct ide_taskfile *tf = &task->tf;

	if (task->tf_flags & IDE_TFLAG_IN_DATA) {
		u16 data = inw(io_ports->data_addr);

		tf->data = data & 0xff;
		tf->hob_data = (data >> 8) & 0xff;
	}

	/* be sure we're looking at the low order bits */
	outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);

	if (task->tf_flags & IDE_TFLAG_IN_FEATURE)
		tf->feature = inb(io_ports->feature_addr);
	if (task->tf_flags & IDE_TFLAG_IN_NSECT)
		tf->nsect  = inb(io_ports->nsect_addr);
	if (task->tf_flags & IDE_TFLAG_IN_LBAL)
		tf->lbal   = inb(io_ports->lbal_addr);
	if (task->tf_flags & IDE_TFLAG_IN_LBAM)
		tf->lbam   = inb(io_ports->lbam_addr);
	if (task->tf_flags & IDE_TFLAG_IN_LBAH)
		tf->lbah   = inb(io_ports->lbah_addr);
	if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
		tf->device = superio_ide_inb(io_ports->device_addr);

	if (task->tf_flags & IDE_TFLAG_LBA48) {
		outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);

		if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
			tf->hob_feature = inb(io_ports->feature_addr);
		if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
			tf->hob_nsect   = inb(io_ports->nsect_addr);
		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
			tf->hob_lbal    = inb(io_ports->lbal_addr);
		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
			tf->hob_lbam    = inb(io_ports->lbam_addr);
		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
			tf->hob_lbah    = inb(io_ports->lbah_addr);
	}
}

static const struct ide_tp_ops superio_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= superio_read_status,
	.read_altstatus		= ide_read_altstatus,
	.read_sff_dma_status	= superio_read_sff_dma_status,

	.set_irq		= ide_set_irq,

	.tf_load		= ide_tf_load,
	.tf_read		= superio_tf_read,

	.input_data		= ide_input_data,
	.output_data		= ide_output_data,
};

static void __devinit superio_init_iops(struct hwif_s *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	u32 dma_stat;
	u8 port = hwif->channel, tmp;

	dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);

	/* Clear error/interrupt, enable dma */
	tmp = superio_ide_inb(dma_stat);
	outb(tmp | 0x66, dma_stat);
}
#endif

static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };

/*
 * This routine either enables/disables (according to drive->present)
 * the IRQ associated with the port (HWIF(drive)),
 * and selects either PIO or DMA handshaking for the next I/O operation.
 */
static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
	unsigned long flags;

	local_irq_save(flags);
	new = *old;

	/* Adjust IRQ enable bit */
	bit = 1 << (8 + hwif->channel);
	new = drive->present ? (new & ~bit) : (new | bit);

	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
	bit   = 1 << (20 + drive->select.b.unit       + (hwif->channel << 1));
	other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1));
	new = use_dma ? ((new & ~other) | bit) : (new & ~bit);

	if (new != *old) {
		unsigned char stat;

		/*
		 * Don't change DMA engine settings while Write Buffers
		 * are busy.
		 */
		(void) pci_read_config_byte(dev, 0x43, &stat);
		while (stat & 0x03) {
			udelay(1);
			(void) pci_read_config_byte(dev, 0x43, &stat);
		}

		*old = new;
		(void) pci_write_config_dword(dev, 0x40, new);

		/*
		 * And let things settle...
		 */
		udelay(10);
	}

	local_irq_restore(flags);
}

static void ns87415_selectproc (ide_drive_t *drive)
{
	ns87415_prepare_drive (drive, drive->using_dma);
}

static int ns87415_dma_end(ide_drive_t *drive)
{
	ide_hwif_t      *hwif = HWIF(drive);
	u8 dma_stat = 0, dma_cmd = 0;

	drive->waiting_for_dma = 0;
	dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
	/* get DMA command mode */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	/* from ERRATA: clear the INTR & ERROR bits */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
	/* and free any DMA resources */
	ide_destroy_dmatable(drive);
	/* verify good DMA status */
	return (dma_stat & 7) != 4;
}

static int ns87415_dma_setup(ide_drive_t *drive)
{
	/* select DMA xfer */
	ns87415_prepare_drive(drive, 1);
	if (!ide_dma_setup(drive))
		return 0;
	/* DMA failed: select PIO xfer */
	ns87415_prepare_drive(drive, 0);
	return 1;
}

static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int ctrl, using_inta;
	u8 progif;
#ifdef __sparc_v9__
	int timeout;
	u8 stat;
#endif

	/*
	 * We cannot probe for IRQ: both ports share common IRQ on INTA.
	 * Also, leave IRQ masked during drive probing, to prevent infinite
	 * interrupts from a potentially floating INTA..
	 *
	 * IRQs get unmasked in selectproc when drive is first used.
	 */
	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	(void) pci_read_config_byte(dev, 0x09, &progif);
	/* is irq in "native" mode? */
	using_inta = progif & (1 << (hwif->channel << 1));
	if (!using_inta)
		using_inta = ctrl & (1 << (4 + hwif->channel));
	if (hwif->mate) {
		hwif->select_data = hwif->mate->select_data;
	} else {
		hwif->select_data = (unsigned long)
					&ns87415_control[ns87415_count++];
		ctrl |= (1 << 8) | (1 << 9);	/* mask both IRQs */
		if (using_inta)
			ctrl &= ~(1 << 6);	/* unmask INTA */
		*((unsigned int *)hwif->select_data) = ctrl;
		(void) pci_write_config_dword(dev, 0x40, ctrl);

		/*
		 * Set prefetch size to 512 bytes for both ports,
		 * but don't turn on/off prefetching here.
		 */
		pci_write_config_byte(dev, 0x55, 0xee);

#ifdef __sparc_v9__
		/*
		 * XXX: Reset the device, if we don't it will not respond to
		 *      SELECT_DRIVE() properly during first ide_probe_port().
		 */
		timeout = 10000;
		outb(12, hwif->io_ports.ctl_addr);
		udelay(10);
		outb(8, hwif->io_ports.ctl_addr);
		do {
			udelay(50);
			stat = hwif->tp_ops->read_status(hwif);
			if (stat == 0xff)
				break;
		} while ((stat & ATA_BUSY) && --timeout);
#endif
	}

	if (!using_inta)
		hwif->irq = __ide_default_irq(hwif->io_ports.data_addr);
	else if (!hwif->irq && hwif->mate && hwif->mate->irq)
		hwif->irq = hwif->mate->irq;	/* share IRQ with mate */

	if (!hwif->dma_base)
		return;

	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
}

static const struct ide_port_ops ns87415_port_ops = {
	.selectproc		= ns87415_selectproc,
};

static const struct ide_dma_ops ns87415_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ns87415_dma_setup,
	.dma_exec_cmd		= ide_dma_exec_cmd,
	.dma_start		= ide_dma_start,
	.dma_end		= ns87415_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timeout		= ide_dma_timeout,
};

static const struct ide_port_info ns87415_chipset __devinitdata = {
	.name		= DRV_NAME,
	.init_hwif	= init_hwif_ns87415,
	.port_ops	= &ns87415_port_ops,
	.dma_ops	= &ns87415_dma_ops,
	.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA |
			  IDE_HFLAG_NO_ATAPI_DMA,
};

static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d = ns87415_chipset;

#ifdef CONFIG_SUPERIO
	if (PCI_SLOT(dev->devfn) == 0xE) {
		/* Built-in - assume it's under superio. */
		d.init_iops = superio_init_iops;
		d.tp_ops = &superio_tp_ops;
	}
#endif
	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id ns87415_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);

static struct pci_driver driver = {
	.name		= "NS87415_IDE",
	.id_table	= ns87415_pci_tbl,
	.probe		= ns87415_init_one,
	.remove		= ide_pci_remove,
};

static int __init ns87415_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

static void __exit ns87415_ide_exit(void)
{
	pci_unregister_driver(&driver);
}

module_init(ns87415_ide_init);
module_exit(ns87415_ide_exit);

MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com>
	3	* Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be>
	4	* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
	5	* Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
	6	*
	7	* Inspired by an earlier effort from David S. Miller <davem@redhat.com>
	8	*/
	9
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/types.h>
	12	#include <linux/kernel.h>
1da177e4	13	#include <linux/interrupt.h>
1da177e4 LT	14	#include <linux/hdreg.h>
	15	#include <linux/pci.h>
	16	#include <linux/delay.h>
	17	#include <linux/ide.h>
	18	#include <linux/init.h>
	19
	20	#include <asm/io.h>
	21
ced3ec8a BZ	22	#define DRV_NAME "ns87415"
ced3ec8a BZ	23
1da177e4 LT	24	#ifdef CONFIG_SUPERIO
	25	/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
	26	* Unfortunately, it's built-in on all Astro-based PA-RISC workstations
	27	* which use the integrated NS87514 cell for CD-ROM support.
	28	* i.e we have to support for CD-ROM installs.
	29	* See drivers/parisc/superio.c for more gory details.
	30	*/
	31	#include <asm/superio.h>
	32
1da177e4 LT	33	#define SUPERIO_IDE_MAX_RETRIES 25
	34
	35	/* Because of a defect in Super I/O, all reads of the PCI DMA status
	36	* registers, IDE status register and the IDE select register need to be
	37	* retried
	38	*/
	39	static u8 superio_ide_inb (unsigned long port)
	40	{
761052e6 BZ	41	u8 tmp;
	42	int retries = SUPERIO_IDE_MAX_RETRIES;
	43
	44	/* printk(" [ reading port 0x%x with retry ] ", port); */
1da177e4	45
761052e6 BZ	46	do {
	47	tmp = inb(port);
	48	if (tmp == 0)
	49	udelay(50);
	50	} while (tmp == 0 && retries-- > 0);
	51
	52	return tmp;
1da177e4 LT	53	}
1da177e4 LT	54
b73c7ee2 BZ	55	static u8 superio_read_status(ide_hwif_t *hwif)
	56	{
	57	return superio_ide_inb(hwif->io_ports.status_addr);
	58	}
	59
b2f951aa BZ	60	static u8 superio_read_sff_dma_status(ide_hwif_t *hwif)
b2f951aa BZ	61	{
cab7f8ed	62	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
b2f951aa BZ	63	}
b2f951aa BZ	64
ea23b8ba BZ	65	static void superio_tf_read(ide_drive_t drive, ide_task_t task)
	66	{
	67	struct ide_io_ports *io_ports = &drive->hwif->io_ports;
	68	struct ide_taskfile *tf = &task->tf;
	69
	70	if (task->tf_flags & IDE_TFLAG_IN_DATA) {
	71	u16 data = inw(io_ports->data_addr);
	72
	73	tf->data = data & 0xff;
	74	tf->hob_data = (data >> 8) & 0xff;
	75	}
	76
	77	/* be sure we're looking at the low order bits */
ff074883	78	outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
ea23b8ba	79
92eb4380 BZ	80	if (task->tf_flags & IDE_TFLAG_IN_FEATURE)
92eb4380 BZ	81	tf->feature = inb(io_ports->feature_addr);
ea23b8ba BZ	82	if (task->tf_flags & IDE_TFLAG_IN_NSECT)
	83	tf->nsect = inb(io_ports->nsect_addr);
	84	if (task->tf_flags & IDE_TFLAG_IN_LBAL)
	85	tf->lbal = inb(io_ports->lbal_addr);
	86	if (task->tf_flags & IDE_TFLAG_IN_LBAM)
	87	tf->lbam = inb(io_ports->lbam_addr);
	88	if (task->tf_flags & IDE_TFLAG_IN_LBAH)
	89	tf->lbah = inb(io_ports->lbah_addr);
	90	if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
	91	tf->device = superio_ide_inb(io_ports->device_addr);
	92
	93	if (task->tf_flags & IDE_TFLAG_LBA48) {
ff074883	94	outb(ATA_DEVCTL_OBS \| 0x80, io_ports->ctl_addr);
ea23b8ba BZ	95
	96	if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
	97	tf->hob_feature = inb(io_ports->feature_addr);
	98	if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
	99	tf->hob_nsect = inb(io_ports->nsect_addr);
	100	if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
	101	tf->hob_lbal = inb(io_ports->lbal_addr);
	102	if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
	103	tf->hob_lbam = inb(io_ports->lbam_addr);
	104	if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
	105	tf->hob_lbah = inb(io_ports->lbah_addr);
	106	}
	107	}
	108
374e042c BZ	109	static const struct ide_tp_ops superio_tp_ops = {
	110	.exec_command = ide_exec_command,
	111	.read_status = superio_read_status,
	112	.read_altstatus = ide_read_altstatus,
	113	.read_sff_dma_status = superio_read_sff_dma_status,
	114
	115	.set_irq = ide_set_irq,
	116
	117	.tf_load = ide_tf_load,
	118	.tf_read = superio_tf_read,
	119
	120	.input_data = ide_input_data,
	121	.output_data = ide_output_data,
	122	};
	123
	124	static void __devinit superio_init_iops(struct hwif_s *hwif)
1da177e4	125	{
36501650	126	struct pci_dev *pdev = to_pci_dev(hwif->dev);
761052e6	127	u32 dma_stat;
36501650	128	u8 port = hwif->channel, tmp;
1da177e4	129
761052e6	130	dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
1da177e4 LT	131
1da177e4 LT	132	/* Clear error/interrupt, enable dma */
761052e6 BZ	133	tmp = superio_ide_inb(dma_stat);
761052e6 BZ	134	outb(tmp \| 0x66, dma_stat);
1da177e4 LT	135	}
	136	#endif
	137
	138	static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
	139
	140	/*
	141	* This routine either enables/disables (according to drive->present)
	142	* the IRQ associated with the port (HWIF(drive)),
	143	* and selects either PIO or DMA handshaking for the next I/O operation.
	144	*/
	145	static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
	146	{
	147	ide_hwif_t *hwif = HWIF(drive);
36501650	148	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	149	unsigned int bit, other, new, old = (unsigned int ) hwif->select_data;
1da177e4 LT	150	unsigned long flags;
	151
	152	local_irq_save(flags);
	153	new = *old;
	154
	155	/* Adjust IRQ enable bit */
	156	bit = 1 << (8 + hwif->channel);
	157	new = drive->present ? (new & ~bit) : (new \| bit);
	158
	159	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
	160	bit = 1 << (20 + drive->select.b.unit + (hwif->channel << 1));
	161	other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1));
	162	new = use_dma ? ((new & ~other) \| bit) : (new & ~bit);
	163
	164	if (new != *old) {
	165	unsigned char stat;
	166
	167	/*
	168	* Don't change DMA engine settings while Write Buffers
	169	* are busy.
	170	*/
	171	(void) pci_read_config_byte(dev, 0x43, &stat);
	172	while (stat & 0x03) {
	173	udelay(1);
	174	(void) pci_read_config_byte(dev, 0x43, &stat);
	175	}
	176
	177	*old = new;
	178	(void) pci_write_config_dword(dev, 0x40, new);
	179
	180	/*
	181	* And let things settle...
	182	*/
	183	udelay(10);
	184	}
	185
	186	local_irq_restore(flags);
	187	}
	188
	189	static void ns87415_selectproc (ide_drive_t *drive)
	190	{
	191	ns87415_prepare_drive (drive, drive->using_dma);
	192	}
	193
5e37bdc0	194	static int ns87415_dma_end(ide_drive_t *drive)
1da177e4 LT	195	{
	196	ide_hwif_t *hwif = HWIF(drive);
	197	u8 dma_stat = 0, dma_cmd = 0;
	198
	199	drive->waiting_for_dma = 0;
374e042c	200	dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
cab7f8ed BZ	201	/* get DMA command mode */
cab7f8ed BZ	202	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
1da177e4	203	/* stop DMA */
cab7f8ed	204	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
1da177e4	205	/* from ERRATA: clear the INTR & ERROR bits */
cab7f8ed BZ	206	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
cab7f8ed BZ	207	outb(dma_cmd \| 6, hwif->dma_base + ATA_DMA_CMD);
1da177e4 LT	208	/* and free any DMA resources */
	209	ide_destroy_dmatable(drive);
	210	/* verify good DMA status */
	211	return (dma_stat & 7) != 4;
	212	}
	213
5e37bdc0	214	static int ns87415_dma_setup(ide_drive_t *drive)
1da177e4 LT	215	{
	216	/* select DMA xfer */
	217	ns87415_prepare_drive(drive, 1);
	218	if (!ide_dma_setup(drive))
	219	return 0;
	220	/* DMA failed: select PIO xfer */
	221	ns87415_prepare_drive(drive, 0);
	222	return 1;
	223	}
	224
c20530ed	225	static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
1da177e4	226	{
36501650	227	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 LT	228	unsigned int ctrl, using_inta;
	229	u8 progif;
	230	#ifdef __sparc_v9__
	231	int timeout;
	232	u8 stat;
	233	#endif
	234
1da177e4 LT	235	/*
	236	* We cannot probe for IRQ: both ports share common IRQ on INTA.
	237	* Also, leave IRQ masked during drive probing, to prevent infinite
	238	* interrupts from a potentially floating INTA..
	239	*
	240	* IRQs get unmasked in selectproc when drive is first used.
	241	*/
	242	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	243	(void) pci_read_config_byte(dev, 0x09, &progif);
	244	/* is irq in "native" mode? */
	245	using_inta = progif & (1 << (hwif->channel << 1));
	246	if (!using_inta)
	247	using_inta = ctrl & (1 << (4 + hwif->channel));
	248	if (hwif->mate) {
	249	hwif->select_data = hwif->mate->select_data;
	250	} else {
	251	hwif->select_data = (unsigned long)
	252	&ns87415_control[ns87415_count++];
	253	ctrl \|= (1 << 8) \| (1 << 9); /* mask both IRQs */
	254	if (using_inta)
	255	ctrl &= ~(1 << 6); /* unmask INTA */
	256	((unsigned int )hwif->select_data) = ctrl;
	257	(void) pci_write_config_dword(dev, 0x40, ctrl);
	258
	259	/*
	260	* Set prefetch size to 512 bytes for both ports,
	261	* but don't turn on/off prefetching here.
	262	*/
	263	pci_write_config_byte(dev, 0x55, 0xee);
	264
	265	#ifdef __sparc_v9__
	266	/*
9d501529 BZ	267	* XXX: Reset the device, if we don't it will not respond to
9d501529 BZ	268	* SELECT_DRIVE() properly during first ide_probe_port().
1da177e4 LT	269	*/
1da177e4 LT	270	timeout = 10000;
4c3032d8	271	outb(12, hwif->io_ports.ctl_addr);
1da177e4	272	udelay(10);
4c3032d8	273	outb(8, hwif->io_ports.ctl_addr);
1da177e4 LT	274	do {
1da177e4 LT	275	udelay(50);
374e042c	276	stat = hwif->tp_ops->read_status(hwif);
3a7d2484 BZ	277	if (stat == 0xff)
	278	break;
	279	} while ((stat & ATA_BUSY) && --timeout);
1da177e4 LT	280	#endif
	281	}
	282
	283	if (!using_inta)
a861beb1	284	hwif->irq = __ide_default_irq(hwif->io_ports.data_addr);
1da177e4 LT	285	else if (!hwif->irq && hwif->mate && hwif->mate->irq)
	286	hwif->irq = hwif->mate->irq; /* share IRQ with mate */
	287
	288	if (!hwif->dma_base)
	289	return;
	290
cab7f8ed	291	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
1da177e4 LT	292	}
1da177e4 LT	293
ac95beed BZ	294	static const struct ide_port_ops ns87415_port_ops = {
	295	.selectproc = ns87415_selectproc,
	296	};
	297
f37afdac BZ	298	static const struct ide_dma_ops ns87415_dma_ops = {
f37afdac BZ	299	.dma_host_set = ide_dma_host_set,
5e37bdc0	300	.dma_setup = ns87415_dma_setup,
f37afdac BZ	301	.dma_exec_cmd = ide_dma_exec_cmd,
f37afdac BZ	302	.dma_start = ide_dma_start,
5e37bdc0	303	.dma_end = ns87415_dma_end,
f37afdac BZ	304	.dma_test_irq = ide_dma_test_irq,
	305	.dma_lost_irq = ide_dma_lost_irq,
	306	.dma_timeout = ide_dma_timeout,
5e37bdc0 BZ	307	};
5e37bdc0 BZ	308
85620436	309	static const struct ide_port_info ns87415_chipset __devinitdata = {
ced3ec8a	310	.name = DRV_NAME,
1da177e4	311	.init_hwif = init_hwif_ns87415,
ac95beed	312	.port_ops = &ns87415_port_ops,
5e37bdc0	313	.dma_ops = &ns87415_dma_ops,
33c1002e	314	.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA \|
5e71d9c5	315	IDE_HFLAG_NO_ATAPI_DMA,
1da177e4 LT	316	};
	317
	318	static int __devinit ns87415_init_one(struct pci_dev dev, const struct pci_device_id id)
	319	{
374e042c BZ	320	struct ide_port_info d = ns87415_chipset;
	321
	322	#ifdef CONFIG_SUPERIO
	323	if (PCI_SLOT(dev->devfn) == 0xE) {
	324	/* Built-in - assume it's under superio. */
	325	d.init_iops = superio_init_iops;
	326	d.tp_ops = &superio_tp_ops;
	327	}
	328	#endif
6cdf6eb3	329	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	330	}
1da177e4 LT	331
9cbcc5e3 BZ	332	static const struct pci_device_id ns87415_pci_tbl[] = {
9cbcc5e3 BZ	333	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
1da177e4 LT	334	{ 0, },
	335	};
	336	MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
	337
	338	static struct pci_driver driver = {
	339	.name = "NS87415_IDE",
	340	.id_table = ns87415_pci_tbl,
	341	.probe = ns87415_init_one,
aa6e518d	342	.remove = ide_pci_remove,
1da177e4 LT	343	};
1da177e4 LT	344
82ab1eec	345	static int __init ns87415_ide_init(void)
1da177e4 LT	346	{
	347	return ide_pci_register_driver(&driver);
	348	}
	349
aa6e518d BZ	350	static void __exit ns87415_ide_exit(void)
	351	{
	352	pci_unregister_driver(&driver);
	353	}
	354
1da177e4	355	module_init(ns87415_ide_init);
aa6e518d	356	module_exit(ns87415_ide_exit);
1da177e4 LT	357
	358	MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
	359	MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
	360	MODULE_LICENSE("GPL");