[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / it8213.c

/*
 * ITE 8213 IDE driver
 *
 * Copyright (C) 2006 Jack Lee
 * Copyright (C) 2006 Alan Cox
 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

/*
 *	it8213_ratemask	-	Compute available modes
 *	@drive: IDE drive
 *
 *	Compute the available speeds for the devices on the interface. This
 *	is all modes to ATA133 clipped by drive cable setup.
 */

static u8 it8213_ratemask (ide_drive_t *drive)
{
	u8 mode	= 4;
	if (!eighty_ninty_three(drive))
		mode = min_t(u8, mode, 1);
	return mode;
}

/**
 *	it8213_dma_2_pio		-	return the PIO mode matching DMA
 *	@xfer_rate: transfer speed
 *
 *	Returns the nearest equivalent PIO timing for the PIO or DMA
 *	mode requested by the controller.
 */

static u8 it8213_dma_2_pio (u8 xfer_rate) {
	switch(xfer_rate) {
		case XFER_UDMA_6:
		case XFER_UDMA_5:
		case XFER_UDMA_4:
		case XFER_UDMA_3:
		case XFER_UDMA_2:
		case XFER_UDMA_1:
		case XFER_UDMA_0:
		case XFER_MW_DMA_2:
		case XFER_PIO_4:
			return 4;
		case XFER_MW_DMA_1:
		case XFER_PIO_3:
			return 3;
		case XFER_SW_DMA_2:
		case XFER_PIO_2:
			return 2;
		case XFER_MW_DMA_0:
		case XFER_SW_DMA_1:
		case XFER_SW_DMA_0:
		case XFER_PIO_1:
		case XFER_PIO_0:
		case XFER_PIO_SLOW:
		default:
			return 0;
	}
}

/*
 *	it8213_tuneproc	-	tune a drive
 *	@drive: drive to tune
 *	@pio: desired PIO mode
 *
 *	Set the interface PIO mode.
 */

static void it8213_tuneproc (ide_drive_t *drive, u8 pio)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	int is_slave		= drive->dn & 1;
	int master_port		= 0x40;
	int slave_port		= 0x44;
	unsigned long flags;
	u16 master_data;
	u8 slave_data;
	static DEFINE_SPINLOCK(tune_lock);
	int control = 0;

	static const u8 timings[][2]= {
					{ 0, 0 },
					{ 0, 0 },
					{ 1, 0 },
					{ 2, 1 },
					{ 2, 3 }, };

	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);

	spin_lock_irqsave(&tune_lock, flags);
	pci_read_config_word(dev, master_port, &master_data);

	if (pio > 1)
		control |= 1;	/* Programmable timing on */
	if (drive->media != ide_disk)
		control |= 4;	/* ATAPI */
	if (pio > 2)
		control |= 2;	/* IORDY */
	if (is_slave) {
		master_data |=  0x4000;
		master_data &= ~0x0070;
		if (pio > 1)
			master_data = master_data | (control << 4);
		pci_read_config_byte(dev, slave_port, &slave_data);
		slave_data = slave_data & 0xf0;
		slave_data = slave_data | (timings[pio][0] << 2) | timings[pio][1];
	} else {
		master_data &= ~0x3307;
		if (pio > 1)
			master_data = master_data | control;
		master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
	}
	pci_write_config_word(dev, master_port, master_data);
	if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
	spin_unlock_irqrestore(&tune_lock, flags);
}

/**
 *	it8213_tune_chipset	-	set controller timings
 *	@drive: Drive to set up
 *	@xferspeed: speed we want to achieve
 *
 *	Tune the ITE chipset for the desired mode. If we can't achieve
 *	the desired mode then tune for a lower one, but ultimately
 *	make the thing work.
 */

static int it8213_tune_chipset (ide_drive_t *drive, u8 xferspeed)
{

	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 maslave		= 0x40;
	u8 speed		= ide_rate_filter(it8213_ratemask(drive), xferspeed);
	int a_speed		= 3 << (drive->dn * 4);
	int u_flag		= 1 << drive->dn;
	int v_flag		= 0x01 << drive->dn;
	int w_flag		= 0x10 << drive->dn;
	int u_speed		= 0;
	u16			reg4042, reg4a;
	u8			reg48, reg54, reg55;

	pci_read_config_word(dev, maslave, &reg4042);
	pci_read_config_byte(dev, 0x48, &reg48);
	pci_read_config_word(dev, 0x4a, &reg4a);
	pci_read_config_byte(dev, 0x54, &reg54);
	pci_read_config_byte(dev, 0x55, &reg55);

	switch(speed) {
		case XFER_UDMA_6:
		case XFER_UDMA_4:
		case XFER_UDMA_2:	u_speed = 2 << (drive->dn * 4); break;
		case XFER_UDMA_5:
		case XFER_UDMA_3:
		case XFER_UDMA_1:	u_speed = 1 << (drive->dn * 4); break;
		case XFER_UDMA_0:	u_speed = 0 << (drive->dn * 4); break;
			break;
		case XFER_MW_DMA_2:
		case XFER_MW_DMA_1:
		case XFER_SW_DMA_2:
			break;
		case XFER_PIO_4:
		case XFER_PIO_3:
		case XFER_PIO_2:
		case XFER_PIO_1:
		case XFER_PIO_0:
			break;
		default:
			return -1;
	}

	if (speed >= XFER_UDMA_0) {
		if (!(reg48 & u_flag))
			pci_write_config_byte(dev, 0x48, reg48 | u_flag);
		if (speed >= XFER_UDMA_5) {
			pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
		} else {
			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
		}

		if ((reg4a & a_speed) != u_speed)
			pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
		if (speed > XFER_UDMA_2) {
			if (!(reg54 & v_flag))
				pci_write_config_byte(dev, 0x54, reg54 | v_flag);
		} else
			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	} else {
		if (reg48 & u_flag)
			pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
		if (reg4a & a_speed)
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
		if (reg54 & v_flag)
			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
		if (reg55 & w_flag)
			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
	}
	it8213_tuneproc(drive, it8213_dma_2_pio(speed));
	return ide_config_drive_speed(drive, speed);
}

/*
 *	config_chipset_for_dma	-	configure for DMA
 *	@drive: drive to configure
 *
 *	Called by the IDE layer when it wants the timings set up.
 */

static int config_chipset_for_dma (ide_drive_t *drive)
{
	u8 speed = ide_dma_speed(drive, it8213_ratemask(drive));

	if (!speed)
		return 0;

	it8213_tune_chipset(drive, speed);

	return ide_dma_enable(drive);
}

/**
 *	it8213_configure_drive_for_dma	-	set up for DMA transfers
 *	@drive: drive we are going to set up
 *
 *	Set up the drive for DMA, tune the controller and drive as
 *	required. If the drive isn't suitable for DMA or we hit
 *	other problems then we will drop down to PIO and set up
 *	PIO appropriately
 */

static int it8213_config_drive_for_dma (ide_drive_t *drive)
{
	u8 pio;

	if (ide_use_dma(drive) && config_chipset_for_dma(drive))
		return 0;

	pio = ide_get_best_pio_mode(drive, 255, 4, NULL);
	it8213_tune_chipset(drive, XFER_PIO_0 + pio);

	return -1;
}

/**
 *	init_hwif_it8213	-	set up hwif structs
 *	@hwif: interface to set up
 *
 *	We do the basic set up of the interface structure. The IT8212
 *	requires several custom handlers so we override the default
 *	ide DMA handlers appropriately
 */

static void __devinit init_hwif_it8213(ide_hwif_t *hwif)
{
	u8 reg42h = 0, ata66 = 0;

	hwif->speedproc = &it8213_tune_chipset;
	hwif->tuneproc	= &it8213_tuneproc;

	hwif->autodma = 0;

	hwif->drives[0].autotune = 1;
	hwif->drives[1].autotune = 1;

	if (!hwif->dma_base)
		return;

	hwif->atapi_dma = 1;
	hwif->ultra_mask = 0x7f;
	hwif->mwdma_mask = 0x06;
	hwif->swdma_mask = 0x04;

	pci_read_config_byte(hwif->pci_dev, 0x42, &reg42h);
	ata66 = (reg42h & 0x02) ? 0 : 1;

	hwif->ide_dma_check = &it8213_config_drive_for_dma;
	if (!(hwif->udma_four))
		hwif->udma_four = ata66;

	/*
	 *	The BIOS often doesn't set up DMA on this controller
	 *	so we always do it.
	 */
	if (!noautodma)
		hwif->autodma = 1;

	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}


#define DECLARE_ITE_DEV(name_str)			\
	{						\
		.name		= name_str,		\
		.init_hwif	= init_hwif_it8213,	\
		.channels	= 1,			\
		.autodma	= AUTODMA,		\
		.enablebits	= {{0x41,0x80,0x80}}, \
		.bootable	= ON_BOARD,		\
	}

static ide_pci_device_t it8213_chipsets[] __devinitdata = {
	/* 0 */ DECLARE_ITE_DEV("IT8213"),
};


/**
 *	it8213_init_one	-	pci layer discovery entry
 *	@dev: PCI device
 *	@id: ident table entry
 *
 *	Called by the PCI code when it finds an ITE8213 controller. As
 *	this device follows the standard interfaces we can use the
 *	standard helper functions to do almost all the work for us.
 */

static int __devinit it8213_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_setup_pci_device(dev, &it8213_chipsets[id->driver_data]);
	return 0;
}


static struct pci_device_id it8213_pci_tbl[] = {
	{ PCI_VENDOR_ID_ITE, 0x8213, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ 0, },
};

MODULE_DEVICE_TABLE(pci, it8213_pci_tbl);

static struct pci_driver driver = {
	.name		= "ITE8213_IDE",
	.id_table	= it8213_pci_tbl,
	.probe		= it8213_init_one,
};

static int __init it8213_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(it8213_ide_init);

MODULE_AUTHOR("Jack Lee, Alan Cox");
MODULE_DESCRIPTION("PCI driver module for the ITE 8213");
MODULE_LICENSE("GPL");
Commit	Line	Data
67881826 BZ	1	/*
	2	* ITE 8213 IDE driver
	3	*
	4	* Copyright (C) 2006 Jack Lee
	5	* Copyright (C) 2006 Alan Cox
	6	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
	7	*/
	8
9c6712c0 JL	9	#include <linux/kernel.h>
	10	#include <linux/types.h>
	11	#include <linux/module.h>
	12	#include <linux/pci.h>
	13	#include <linux/delay.h>
	14	#include <linux/hdreg.h>
	15	#include <linux/ide.h>
	16	#include <linux/init.h>
	17
	18	#include <asm/io.h>
	19
	20	/*
	21	* it8213_ratemask - Compute available modes
	22	* @drive: IDE drive
	23	*
	24	* Compute the available speeds for the devices on the interface. This
67881826	25	* is all modes to ATA133 clipped by drive cable setup.
9c6712c0 JL	26	*/
	27
	28	static u8 it8213_ratemask (ide_drive_t *drive)
	29	{
	30	u8 mode = 4;
	31	if (!eighty_ninty_three(drive))
67881826	32	mode = min_t(u8, mode, 1);
9c6712c0 JL	33	return mode;
	34	}
	35
	36	/**
	37	* it8213_dma_2_pio - return the PIO mode matching DMA
	38	* @xfer_rate: transfer speed
	39	*
	40	* Returns the nearest equivalent PIO timing for the PIO or DMA
	41	* mode requested by the controller.
	42	*/
	43
	44	static u8 it8213_dma_2_pio (u8 xfer_rate) {
	45	switch(xfer_rate) {
	46	case XFER_UDMA_6:
	47	case XFER_UDMA_5:
	48	case XFER_UDMA_4:
	49	case XFER_UDMA_3:
	50	case XFER_UDMA_2:
	51	case XFER_UDMA_1:
	52	case XFER_UDMA_0:
	53	case XFER_MW_DMA_2:
	54	case XFER_PIO_4:
	55	return 4;
	56	case XFER_MW_DMA_1:
	57	case XFER_PIO_3:
	58	return 3;
	59	case XFER_SW_DMA_2:
	60	case XFER_PIO_2:
	61	return 2;
	62	case XFER_MW_DMA_0:
	63	case XFER_SW_DMA_1:
	64	case XFER_SW_DMA_0:
	65	case XFER_PIO_1:
	66	case XFER_PIO_0:
	67	case XFER_PIO_SLOW:
	68	default:
	69	return 0;
	70	}
	71	}
	72
9c6712c0 JL	73	/*
	74	* it8213_tuneproc - tune a drive
	75	* @drive: drive to tune
67881826	76	* @pio: desired PIO mode
9c6712c0	77	*
67881826	78	* Set the interface PIO mode.
9c6712c0 JL	79	*/
9c6712c0 JL	80
67881826	81	static void it8213_tuneproc (ide_drive_t *drive, u8 pio)
9c6712c0 JL	82	{
	83	ide_hwif_t *hwif = HWIF(drive);
	84	struct pci_dev *dev = hwif->pci_dev;
67881826	85	int is_slave = drive->dn & 1;
9c6712c0 JL	86	int master_port = 0x40;
	87	int slave_port = 0x44;
	88	unsigned long flags;
	89	u16 master_data;
	90	u8 slave_data;
67881826 BZ	91	static DEFINE_SPINLOCK(tune_lock);
67881826 BZ	92	int control = 0;
9c6712c0	93
67881826 BZ	94	static const u8 timings[][2]= {
	95	{ 0, 0 },
	96	{ 0, 0 },
	97	{ 1, 0 },
	98	{ 2, 1 },
	99	{ 2, 3 }, };
9c6712c0	100
67881826	101	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
9c6712c0 JL	102
	103	spin_lock_irqsave(&tune_lock, flags);
	104	pci_read_config_word(dev, master_port, &master_data);
67881826 BZ	105
	106	if (pio > 1)
	107	control \|= 1; /* Programmable timing on */
	108	if (drive->media != ide_disk)
	109	control \|= 4; /* ATAPI */
	110	if (pio > 2)
	111	control \|= 2; /* IORDY */
9c6712c0	112	if (is_slave) {
67881826 BZ	113	master_data \|= 0x4000;
67881826 BZ	114	master_data &= ~0x0070;
9c6712c0	115	if (pio > 1)
67881826	116	master_data = master_data \| (control << 4);
9c6712c0 JL	117	pci_read_config_byte(dev, slave_port, &slave_data);
9c6712c0 JL	118	slave_data = slave_data & 0xf0;
67881826	119	slave_data = slave_data \| (timings[pio][0] << 2) \| timings[pio][1];
9c6712c0	120	} else {
67881826	121	master_data &= ~0x3307;
9c6712c0	122	if (pio > 1)
67881826	123	master_data = master_data \| control;
9c6712c0 JL	124	master_data = master_data \| (timings[pio][0] << 12) \| (timings[pio][1] << 8);
	125	}
	126	pci_write_config_word(dev, master_port, master_data);
	127	if (is_slave)
	128	pci_write_config_byte(dev, slave_port, slave_data);
	129	spin_unlock_irqrestore(&tune_lock, flags);
	130	}
	131
9c6712c0 JL	132	/**
	133	* it8213_tune_chipset - set controller timings
	134	* @drive: Drive to set up
	135	* @xferspeed: speed we want to achieve
	136	*
	137	* Tune the ITE chipset for the desired mode. If we can't achieve
	138	* the desired mode then tune for a lower one, but ultimately
	139	* make the thing work.
	140	*/
	141
67881826	142	static int it8213_tune_chipset (ide_drive_t *drive, u8 xferspeed)
9c6712c0 JL	143	{
	144
	145	ide_hwif_t *hwif = HWIF(drive);
	146	struct pci_dev *dev = hwif->pci_dev;
	147	u8 maslave = 0x40;
	148	u8 speed = ide_rate_filter(it8213_ratemask(drive), xferspeed);
	149	int a_speed = 3 << (drive->dn * 4);
	150	int u_flag = 1 << drive->dn;
	151	int v_flag = 0x01 << drive->dn;
	152	int w_flag = 0x10 << drive->dn;
	153	int u_speed = 0;
	154	u16 reg4042, reg4a;
	155	u8 reg48, reg54, reg55;
	156
	157	pci_read_config_word(dev, maslave, &reg4042);
	158	pci_read_config_byte(dev, 0x48, &reg48);
	159	pci_read_config_word(dev, 0x4a, &reg4a);
	160	pci_read_config_byte(dev, 0x54, &reg54);
	161	pci_read_config_byte(dev, 0x55, &reg55);
	162
	163	switch(speed) {
	164	case XFER_UDMA_6:
	165	case XFER_UDMA_4:
67881826	166	case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
9c6712c0 JL	167	case XFER_UDMA_5:
9c6712c0 JL	168	case XFER_UDMA_3:
67881826 BZ	169	case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
67881826 BZ	170	case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
9c6712c0 JL	171	break;
	172	case XFER_MW_DMA_2:
	173	case XFER_MW_DMA_1:
67881826	174	case XFER_SW_DMA_2:
9c6712c0 JL	175	break;
	176	case XFER_PIO_4:
	177	case XFER_PIO_3:
	178	case XFER_PIO_2:
	179	case XFER_PIO_1:
	180	case XFER_PIO_0:
	181	break;
	182	default:
	183	return -1;
	184	}
	185
67881826	186	if (speed >= XFER_UDMA_0) {
9c6712c0 JL	187	if (!(reg48 & u_flag))
	188	pci_write_config_byte(dev, 0x48, reg48 \| u_flag);
	189	if (speed >= XFER_UDMA_5) {
	190	pci_write_config_byte(dev, 0x55, (u8) reg55\|w_flag);
	191	} else {
	192	pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
	193	}
	194
	195	if ((reg4a & a_speed) != u_speed)
	196	pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) \| u_speed);
67881826	197	if (speed > XFER_UDMA_2) {
9c6712c0 JL	198	if (!(reg54 & v_flag))
	199	pci_write_config_byte(dev, 0x54, reg54 \| v_flag);
	200	} else
	201	pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
67881826	202	} else {
9c6712c0 JL	203	if (reg48 & u_flag)
	204	pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
	205	if (reg4a & a_speed)
	206	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
	207	if (reg54 & v_flag)
	208	pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	209	if (reg55 & w_flag)
	210	pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
67881826	211	}
9c6712c0 JL	212	it8213_tuneproc(drive, it8213_dma_2_pio(speed));
9c6712c0 JL	213	return ide_config_drive_speed(drive, speed);
67881826	214	}
9c6712c0 JL	215
	216	/*
	217	* config_chipset_for_dma - configure for DMA
	218	* @drive: drive to configure
	219	*
	220	* Called by the IDE layer when it wants the timings set up.
	221	*/
	222
	223	static int config_chipset_for_dma (ide_drive_t *drive)
	224	{
67881826 BZ	225	u8 speed = ide_dma_speed(drive, it8213_ratemask(drive));
67881826 BZ	226
9c6712c0	227	if (!speed)
67881826 BZ	228	return 0;
67881826 BZ	229
9c6712c0	230	it8213_tune_chipset(drive, speed);
67881826	231
9c6712c0 JL	232	return ide_dma_enable(drive);
	233	}
	234
9c6712c0 JL	235	/**
	236	* it8213_configure_drive_for_dma - set up for DMA transfers
	237	* @drive: drive we are going to set up
	238	*
	239	* Set up the drive for DMA, tune the controller and drive as
	240	* required. If the drive isn't suitable for DMA or we hit
	241	* other problems then we will drop down to PIO and set up
	242	* PIO appropriately
	243	*/
	244
	245	static int it8213_config_drive_for_dma (ide_drive_t *drive)
	246	{
3608b5d7	247	u8 pio;
67881826	248
3608b5d7 BZ	249	if (ide_use_dma(drive) && config_chipset_for_dma(drive))
3608b5d7 BZ	250	return 0;
9c6712c0	251
3608b5d7 BZ	252	pio = ide_get_best_pio_mode(drive, 255, 4, NULL);
3608b5d7 BZ	253	it8213_tune_chipset(drive, XFER_PIO_0 + pio);
9c6712c0	254
3608b5d7	255	return -1;
9c6712c0 JL	256	}
9c6712c0 JL	257
9c6712c0 JL	258	/**
	259	* init_hwif_it8213 - set up hwif structs
	260	* @hwif: interface to set up
	261	*
	262	* We do the basic set up of the interface structure. The IT8212
	263	* requires several custom handlers so we override the default
	264	* ide DMA handlers appropriately
	265	*/
	266
	267	static void __devinit init_hwif_it8213(ide_hwif_t *hwif)
	268	{
	269	u8 reg42h = 0, ata66 = 0;
9c6712c0 JL	270
	271	hwif->speedproc = &it8213_tune_chipset;
	272	hwif->tuneproc = &it8213_tuneproc;
	273
	274	hwif->autodma = 0;
	275
	276	hwif->drives[0].autotune = 1;
	277	hwif->drives[1].autotune = 1;
	278
	279	if (!hwif->dma_base)
67881826 BZ	280	return;
67881826 BZ	281
9c6712c0 JL	282	hwif->atapi_dma = 1;
9c6712c0 JL	283	hwif->ultra_mask = 0x7f;
67881826 BZ	284	hwif->mwdma_mask = 0x06;
67881826 BZ	285	hwif->swdma_mask = 0x04;
9c6712c0 JL	286
9c6712c0 JL	287	pci_read_config_byte(hwif->pci_dev, 0x42, &reg42h);
67881826	288	ata66 = (reg42h & 0x02) ? 0 : 1;
9c6712c0 JL	289
	290	hwif->ide_dma_check = &it8213_config_drive_for_dma;
	291	if (!(hwif->udma_four))
	292	hwif->udma_four = ata66;
9c6712c0 JL	293
	294	/*
	295	* The BIOS often doesn't set up DMA on this controller
	296	* so we always do it.
	297	*/
	298	if (!noautodma)
	299	hwif->autodma = 1;
	300
	301	hwif->drives[0].autodma = hwif->autodma;
	302	hwif->drives[1].autodma = hwif->autodma;
9c6712c0 JL	303	}
	304
	305
	306	#define DECLARE_ITE_DEV(name_str) \
	307	{ \
	308	.name = name_str, \
9c6712c0 JL	309	.init_hwif = init_hwif_it8213, \
9c6712c0 JL	310	.channels = 1, \
67881826	311	.autodma = AUTODMA, \
9c6712c0 JL	312	.enablebits = {{0x41,0x80,0x80}}, \
	313	.bootable = ON_BOARD, \
	314	}
	315
	316	static ide_pci_device_t it8213_chipsets[] __devinitdata = {
	317	/* 0 */ DECLARE_ITE_DEV("IT8213"),
	318	};
	319
	320
	321	/**
	322	* it8213_init_one - pci layer discovery entry
	323	* @dev: PCI device
	324	* @id: ident table entry
	325	*
	326	* Called by the PCI code when it finds an ITE8213 controller. As
	327	* this device follows the standard interfaces we can use the
	328	* standard helper functions to do almost all the work for us.
	329	*/
	330
	331	static int __devinit it8213_init_one(struct pci_dev dev, const struct pci_device_id id)
	332	{
	333	ide_setup_pci_device(dev, &it8213_chipsets[id->driver_data]);
	334	return 0;
	335	}
	336
	337
	338	static struct pci_device_id it8213_pci_tbl[] = {
67881826	339	{ PCI_VENDOR_ID_ITE, 0x8213, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
9c6712c0 JL	340	{ 0, },
	341	};
	342
	343	MODULE_DEVICE_TABLE(pci, it8213_pci_tbl);
	344
	345	static struct pci_driver driver = {
	346	.name = "ITE8213_IDE",
	347	.id_table = it8213_pci_tbl,
	348	.probe = it8213_init_one,
	349	};
	350
	351	static int __init it8213_ide_init(void)
	352	{
67881826 BZ	353	return ide_pci_register_driver(&driver);
67881826 BZ	354	}
9c6712c0 JL	355
	356	module_init(it8213_ide_init);
	357
67881826	358	MODULE_AUTHOR("Jack Lee, Alan Cox");
9c6712c0 JL	359	MODULE_DESCRIPTION("PCI driver module for the ITE 8213");
9c6712c0 JL	360	MODULE_LICENSE("GPL");