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[PATCH] ide: fix the case of multiple HPT3xx chips present
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / hpt366.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
836c0063 7 * Portions Copyright (C) 2005-2006 MontaVista Software, Inc.
1da177e4
LT		 8 *
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
13 *
b39b01ff 14 *
836c0063
SS		 15 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
b39b01ff 20 *
1da177e4
LT		 21 * Note that final HPT370 support was done by force extraction of GPL.
22 *
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
37 *
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
43 *
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
46 *
47 * On hpt366:
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
51 *
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
55 * keeping me sane.
56 * Alan Cox <alan@redhat.com>
57 *
836c0063
SS		 58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - avoid calibrating PLL twice as the second time results in a wrong PCI
64 * frequency and thus in the wrong timings for the secondary channel
65 * - disable UltraATA/133 for HPT372 by default (50 MHz DPLL clock do not
66 * allow for this speed anyway)
67 * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
68 * - HPT371/N are single channel chips, so avoid touching the primary channel
69 * which exists only virtually (there's no pins for it)
471a0bda
SS		 70 * - fix/remove bad/unused timing tables and use one set of tables for the whole
71 * HPT37x chip family; save space by introducing the separate transfer mode
72 * table in which the mode lookup is done
33b18a60
SS		 73 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
74 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
73d1dd93
SS		 75 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
76 * they tamper with its fields
836c0063
SS		 77 * <source@mvista.com>
78 *
1da177e4
LT		 79 */
80
81
1da177e4
LT		 82#include <linux/types.h>
83#include <linux/module.h>
84#include <linux/kernel.h>
85#include <linux/delay.h>
86#include <linux/timer.h>
87#include <linux/mm.h>
88#include <linux/ioport.h>
89#include <linux/blkdev.h>
90#include <linux/hdreg.h>
91
92#include <linux/interrupt.h>
93#include <linux/pci.h>
94#include <linux/init.h>
95#include <linux/ide.h>
96
97#include <asm/uaccess.h>
98#include <asm/io.h>
99#include <asm/irq.h>
100
101/* various tuning parameters */
102#define HPT_RESET_STATE_ENGINE
836c0063
SS		 103#undef HPT_DELAY_INTERRUPT
104#define HPT_SERIALIZE_IO 0
1da177e4
LT		 105
106static const char *quirk_drives[] = {
107 "QUANTUM FIREBALLlct08 08",
108 "QUANTUM FIREBALLP KA6.4",
109 "QUANTUM FIREBALLP LM20.4",
110 "QUANTUM FIREBALLP LM20.5",
111 NULL
112};
113
114static const char *bad_ata100_5[] = {
115 "IBM-DTLA-307075",
116 "IBM-DTLA-307060",
117 "IBM-DTLA-307045",
118 "IBM-DTLA-307030",
119 "IBM-DTLA-307020",
120 "IBM-DTLA-307015",
121 "IBM-DTLA-305040",
122 "IBM-DTLA-305030",
123 "IBM-DTLA-305020",
124 "IC35L010AVER07-0",
125 "IC35L020AVER07-0",
126 "IC35L030AVER07-0",
127 "IC35L040AVER07-0",
128 "IC35L060AVER07-0",
129 "WDC AC310200R",
130 NULL
131};
132
133static const char *bad_ata66_4[] = {
134 "IBM-DTLA-307075",
135 "IBM-DTLA-307060",
136 "IBM-DTLA-307045",
137 "IBM-DTLA-307030",
138 "IBM-DTLA-307020",
139 "IBM-DTLA-307015",
140 "IBM-DTLA-305040",
141 "IBM-DTLA-305030",
142 "IBM-DTLA-305020",
143 "IC35L010AVER07-0",
144 "IC35L020AVER07-0",
145 "IC35L030AVER07-0",
146 "IC35L040AVER07-0",
147 "IC35L060AVER07-0",
148 "WDC AC310200R",
149 NULL
150};
151
152static const char *bad_ata66_3[] = {
153 "WDC AC310200R",
154 NULL
155};
156
157static const char *bad_ata33[] = {
158 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
159 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
160 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
161 "Maxtor 90510D4",
162 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
163 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
164 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
165 NULL
166};
167
471a0bda
SS		 168static u8 xfer_speeds[] = {
169 XFER_UDMA_6,
170 XFER_UDMA_5,
171 XFER_UDMA_4,
172 XFER_UDMA_3,
173 XFER_UDMA_2,
174 XFER_UDMA_1,
175 XFER_UDMA_0,
176
177 XFER_MW_DMA_2,
178 XFER_MW_DMA_1,
179 XFER_MW_DMA_0,
180
181 XFER_PIO_4,
182 XFER_PIO_3,
183 XFER_PIO_2,
184 XFER_PIO_1,
185 XFER_PIO_0
1da177e4
LT		 186};
187
471a0bda
SS		 188/* Key for bus clock timings
189 * 36x 37x
190 * bits bits
191 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
192 * cycles = value + 1
193 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
194 * cycles = value + 1
195 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
196 * register access.
197 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
198 * register access.
199 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
200 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
201 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
202 * MW DMA xfer.
203 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
204 * task file register access.
205 * 28 28 UDMA enable.
206 * 29 29 DMA enable.
207 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
208 * PIO xfer.
209 * 31 31 FIFO enable.
1da177e4 210 */
1da177e4 211
471a0bda
SS		 212static u32 forty_base_hpt36x[] = {
213 /* XFER_UDMA_6 */ 0x900fd943,
214 /* XFER_UDMA_5 */ 0x900fd943,
215 /* XFER_UDMA_4 */ 0x900fd943,
216 /* XFER_UDMA_3 */ 0x900ad943,
217 /* XFER_UDMA_2 */ 0x900bd943,
218 /* XFER_UDMA_1 */ 0x9008d943,
219 /* XFER_UDMA_0 */ 0x9008d943,
220
221 /* XFER_MW_DMA_2 */ 0xa008d943,
222 /* XFER_MW_DMA_1 */ 0xa010d955,
223 /* XFER_MW_DMA_0 */ 0xa010d9fc,
224
225 /* XFER_PIO_4 */ 0xc008d963,
226 /* XFER_PIO_3 */ 0xc010d974,
227 /* XFER_PIO_2 */ 0xc010d997,
228 /* XFER_PIO_1 */ 0xc010d9c7,
229 /* XFER_PIO_0 */ 0xc018d9d9
1da177e4
LT		 230};
231
471a0bda
SS		 232static u32 thirty_three_base_hpt36x[] = {
233 /* XFER_UDMA_6 */ 0x90c9a731,
234 /* XFER_UDMA_5 */ 0x90c9a731,
235 /* XFER_UDMA_4 */ 0x90c9a731,
236 /* XFER_UDMA_3 */ 0x90cfa731,
237 /* XFER_UDMA_2 */ 0x90caa731,
238 /* XFER_UDMA_1 */ 0x90cba731,
239 /* XFER_UDMA_0 */ 0x90c8a731,
240
241 /* XFER_MW_DMA_2 */ 0xa0c8a731,
242 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
243 /* XFER_MW_DMA_0 */ 0xa0c8a797,
244
245 /* XFER_PIO_4 */ 0xc0c8a731,
246 /* XFER_PIO_3 */ 0xc0c8a742,
247 /* XFER_PIO_2 */ 0xc0d0a753,
248 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
249 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
1da177e4
LT		 250};
251
471a0bda
SS		 252static u32 twenty_five_base_hpt36x[] = {
253 /* XFER_UDMA_6 */ 0x90c98521,
254 /* XFER_UDMA_5 */ 0x90c98521,
255 /* XFER_UDMA_4 */ 0x90c98521,
256 /* XFER_UDMA_3 */ 0x90cf8521,
257 /* XFER_UDMA_2 */ 0x90cf8521,
258 /* XFER_UDMA_1 */ 0x90cb8521,
259 /* XFER_UDMA_0 */ 0x90cb8521,
260
261 /* XFER_MW_DMA_2 */ 0xa0ca8521,
262 /* XFER_MW_DMA_1 */ 0xa0ca8532,
263 /* XFER_MW_DMA_0 */ 0xa0ca8575,
264
265 /* XFER_PIO_4 */ 0xc0ca8521,
266 /* XFER_PIO_3 */ 0xc0ca8532,
267 /* XFER_PIO_2 */ 0xc0ca8542,
268 /* XFER_PIO_1 */ 0xc0d08572,
269 /* XFER_PIO_0 */ 0xc0d08585
1da177e4
LT		 270};
271
471a0bda
SS		 272static u32 thirty_three_base_hpt37x[] = {
273 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
274 /* XFER_UDMA_5 */ 0x12446231,
275 /* XFER_UDMA_4 */ 0x12446231,
276 /* XFER_UDMA_3 */ 0x126c6231,
277 /* XFER_UDMA_2 */ 0x12486231,
278 /* XFER_UDMA_1 */ 0x124c6233,
279 /* XFER_UDMA_0 */ 0x12506297,
280
281 /* XFER_MW_DMA_2 */ 0x22406c31,
282 /* XFER_MW_DMA_1 */ 0x22406c33,
283 /* XFER_MW_DMA_0 */ 0x22406c97,
284
285 /* XFER_PIO_4 */ 0x06414e31,
286 /* XFER_PIO_3 */ 0x06414e42,
287 /* XFER_PIO_2 */ 0x06414e53,
288 /* XFER_PIO_1 */ 0x06814e93,
289 /* XFER_PIO_0 */ 0x06814ea7
1da177e4
LT		 290};
291
471a0bda
SS		 292static u32 fifty_base_hpt37x[] = {
293 /* XFER_UDMA_6 */ 0x12848242,
294 /* XFER_UDMA_5 */ 0x12848242,
295 /* XFER_UDMA_4 */ 0x12ac8242,
296 /* XFER_UDMA_3 */ 0x128c8242,
297 /* XFER_UDMA_2 */ 0x120c8242,
298 /* XFER_UDMA_1 */ 0x12148254,
299 /* XFER_UDMA_0 */ 0x121882ea,
300
301 /* XFER_MW_DMA_2 */ 0x22808242,
302 /* XFER_MW_DMA_1 */ 0x22808254,
303 /* XFER_MW_DMA_0 */ 0x228082ea,
304
305 /* XFER_PIO_4 */ 0x0a81f442,
306 /* XFER_PIO_3 */ 0x0a81f443,
307 /* XFER_PIO_2 */ 0x0a81f454,
308 /* XFER_PIO_1 */ 0x0ac1f465,
309 /* XFER_PIO_0 */ 0x0ac1f48a
1da177e4
LT		 310};
311
471a0bda
SS		 312static u32 sixty_six_base_hpt37x[] = {
313 /* XFER_UDMA_6 */ 0x1c869c62,
314 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
315 /* XFER_UDMA_4 */ 0x1c8a9c62,
316 /* XFER_UDMA_3 */ 0x1c8e9c62,
317 /* XFER_UDMA_2 */ 0x1c929c62,
318 /* XFER_UDMA_1 */ 0x1c9a9c62,
319 /* XFER_UDMA_0 */ 0x1c829c62,
320
321 /* XFER_MW_DMA_2 */ 0x2c829c62,
322 /* XFER_MW_DMA_1 */ 0x2c829c66,
323 /* XFER_MW_DMA_0 */ 0x2c829d2e,
324
325 /* XFER_PIO_4 */ 0x0c829c62,
326 /* XFER_PIO_3 */ 0x0c829c84,
327 /* XFER_PIO_2 */ 0x0c829ca6,
328 /* XFER_PIO_1 */ 0x0d029d26,
329 /* XFER_PIO_0 */ 0x0d029d5e
1da177e4
LT		 330};
331
1da177e4
LT		 332#define HPT366_DEBUG_DRIVE_INFO 0
333#define HPT374_ALLOW_ATA133_6 0
334#define HPT371_ALLOW_ATA133_6 0
335#define HPT302_ALLOW_ATA133_6 0
836c0063 336#define HPT372_ALLOW_ATA133_6 0
1da177e4
LT		 337#define HPT370_ALLOW_ATA100_5 1
338#define HPT366_ALLOW_ATA66_4 1
339#define HPT366_ALLOW_ATA66_3 1
340#define HPT366_MAX_DEVS 8
341
342#define F_LOW_PCI_33 0x23
343#define F_LOW_PCI_40 0x29
344#define F_LOW_PCI_50 0x2d
345#define F_LOW_PCI_66 0x42
346
b39b01ff
AC		 347/*
348 * Hold all the highpoint quirks and revision information in one
349 * place.
350 */
1da177e4 351
b39b01ff
AC		 352struct hpt_info
353{
354 u8 max_mode; /* Speeds allowed */
355 int revision; /* Chipset revision */
356 int flags; /* Chipset properties */
357#define PLL_MODE 1
836c0063
SS		 358#define IS_3xxN 2
359#define PCI_66MHZ 4
b39b01ff 360 /* Speed table */
471a0bda 361 u32 *speed;
b39b01ff
AC		 362};
363
364/*
365 * This wants fixing so that we do everything not by classrev
366 * (which breaks on the newest chips) but by creating an
367 * enumeration of chip variants and using that
368 */
369
370static __devinit u32 hpt_revision (struct pci_dev *dev)
1da177e4
LT		 371{
372 u32 class_rev;
373 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
374 class_rev &= 0xff;
375
376 switch(dev->device) {
377 /* Remap new 372N onto 372 */
378 case PCI_DEVICE_ID_TTI_HPT372N:
379 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
380 case PCI_DEVICE_ID_TTI_HPT374:
381 class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
382 case PCI_DEVICE_ID_TTI_HPT371:
383 class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
384 case PCI_DEVICE_ID_TTI_HPT302:
385 class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
386 case PCI_DEVICE_ID_TTI_HPT372:
387 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
388 default:
389 break;
390 }
391 return class_rev;
392}
393
1da177e4
LT		 394static int check_in_drive_lists(ide_drive_t *drive, const char **list);
395
396static u8 hpt3xx_ratemask (ide_drive_t *drive)
397{
b39b01ff
AC		 398 ide_hwif_t *hwif = drive->hwif;
399 struct hpt_info *info = ide_get_hwifdata(hwif);
1da177e4
LT		 400 u8 mode = 0;
401
b39b01ff
AC		 402 /* FIXME: TODO - move this to set info->mode once at boot */
403
404 if (info->revision >= 8) { /* HPT374 */
1da177e4 405 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
b39b01ff 406 } else if (info->revision >= 7) { /* HPT371 */
1da177e4 407 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
b39b01ff 408 } else if (info->revision >= 6) { /* HPT302 */
1da177e4 409 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
b39b01ff 410 } else if (info->revision >= 5) { /* HPT372 */
1da177e4 411 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
b39b01ff 412 } else if (info->revision >= 4) { /* HPT370A */
1da177e4 413 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
b39b01ff 414 } else if (info->revision >= 3) { /* HPT370 */
1da177e4
LT		 415 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
416 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
417 } else { /* HPT366 and HPT368 */
418 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
419 }
b39b01ff 420 if (!eighty_ninty_three(drive) && mode)
1da177e4
LT		 421 mode = min(mode, (u8)1);
422 return mode;
423}
424
425/*
426 * Note for the future; the SATA hpt37x we must set
427 * either PIO or UDMA modes 0,4,5
428 */
429
430static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
431{
b39b01ff
AC		 432 ide_hwif_t *hwif = drive->hwif;
433 struct hpt_info *info = ide_get_hwifdata(hwif);
1da177e4
LT		 434 u8 mode = hpt3xx_ratemask(drive);
435
436 if (drive->media != ide_disk)
437 return min(speed, (u8)XFER_PIO_4);
438
439 switch(mode) {
440 case 0x04:
441 speed = min(speed, (u8)XFER_UDMA_6);
442 break;
443 case 0x03:
444 speed = min(speed, (u8)XFER_UDMA_5);
b39b01ff 445 if (info->revision >= 5)
1da177e4
LT		 446 break;
447 if (check_in_drive_lists(drive, bad_ata100_5))
448 speed = min(speed, (u8)XFER_UDMA_4);
449 break;
450 case 0x02:
451 speed = min(speed, (u8)XFER_UDMA_4);
452 /*
453 * CHECK ME, Does this need to be set to 5 ??
454 */
b39b01ff 455 if (info->revision >= 3)
1da177e4
LT		 456 break;
457 if ((check_in_drive_lists(drive, bad_ata66_4)) ||
458 (!(HPT366_ALLOW_ATA66_4)))
459 speed = min(speed, (u8)XFER_UDMA_3);
460 if ((check_in_drive_lists(drive, bad_ata66_3)) ||
461 (!(HPT366_ALLOW_ATA66_3)))
462 speed = min(speed, (u8)XFER_UDMA_2);
463 break;
464 case 0x01:
465 speed = min(speed, (u8)XFER_UDMA_2);
466 /*
467 * CHECK ME, Does this need to be set to 5 ??
468 */
b39b01ff 469 if (info->revision >= 3)
1da177e4
LT		 470 break;
471 if (check_in_drive_lists(drive, bad_ata33))
472 speed = min(speed, (u8)XFER_MW_DMA_2);
473 break;
474 case 0x00:
475 default:
476 speed = min(speed, (u8)XFER_MW_DMA_2);
477 break;
478 }
479 return speed;
480}
481
482static int check_in_drive_lists (ide_drive_t *drive, const char **list)
483{
484 struct hd_driveid *id = drive->id;
485
486 if (quirk_drives == list) {
487 while (*list)
488 if (strstr(id->model, *list++))
489 return 1;
490 } else {
491 while (*list)
492 if (!strcmp(*list++,id->model))
493 return 1;
494 }
495 return 0;
496}
497
471a0bda 498static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
1da177e4 499{
471a0bda
SS		 500 int i;
501
502 /*
503 * Lookup the transfer mode table to get the index into
504 * the timing table.
505 *
506 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
507 */
508 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
509 if (xfer_speeds[i] == speed)
510 break;
511 return chipset_table[i];
1da177e4
LT		 512}
513
514static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
515{
b39b01ff
AC		 516 ide_hwif_t *hwif = drive->hwif;
517 struct pci_dev *dev = hwif->pci_dev;
518 struct hpt_info *info = ide_get_hwifdata(hwif);
1da177e4 519 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
1da177e4 520 u8 regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
b39b01ff 521 u8 regfast = (hwif->channel) ? 0x55 : 0x51;
1da177e4
LT		 522 u8 drive_fast = 0;
523 u32 reg1 = 0, reg2 = 0;
524
525 /*
526 * Disable the "fast interrupt" prediction.
527 */
528 pci_read_config_byte(dev, regfast, &drive_fast);
1da177e4
LT		 529 if (drive_fast & 0x80)
530 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
1da177e4 531
b39b01ff
AC		 532 reg2 = pci_bus_clock_list(speed, info->speed);
533
1da177e4
LT		 534 /*
535 * Disable on-chip PIO FIFO/buffer
536 * (to avoid problems handling I/O errors later)
537 */
538 pci_read_config_dword(dev, regtime, &reg1);
539 if (speed >= XFER_MW_DMA_0) {
540 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
541 } else {
542 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
543 }
544 reg2 &= ~0x80000000;
545
546 pci_write_config_dword(dev, regtime, reg2);
547
548 return ide_config_drive_speed(drive, speed);
549}
550
551static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
552{
b39b01ff
AC		 553 ide_hwif_t *hwif = drive->hwif;
554 struct pci_dev *dev = hwif->pci_dev;
555 struct hpt_info *info = ide_get_hwifdata(hwif);
1da177e4 556 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
b39b01ff 557 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51;
1da177e4
LT		 558 u8 drive_pci = 0x40 + (drive->dn * 4);
559 u8 new_fast = 0, drive_fast = 0;
560 u32 list_conf = 0, drive_conf = 0;
561 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
562
563 /*
564 * Disable the "fast interrupt" prediction.
565 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
566 */
567 pci_read_config_byte(dev, regfast, &drive_fast);
568 new_fast = drive_fast;
569 if (new_fast & 0x02)
570 new_fast &= ~0x02;
571
572#ifdef HPT_DELAY_INTERRUPT
573 if (new_fast & 0x01)
574 new_fast &= ~0x01;
575#else
576 if ((new_fast & 0x01) == 0)
577 new_fast |= 0x01;
578#endif
579 if (new_fast != drive_fast)
580 pci_write_config_byte(dev, regfast, new_fast);
581
b39b01ff 582 list_conf = pci_bus_clock_list(speed, info->speed);
1da177e4
LT		 583
584 pci_read_config_dword(dev, drive_pci, &drive_conf);
585 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
586
b39b01ff 587 if (speed < XFER_MW_DMA_0)
1da177e4 588 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
1da177e4
LT		 589 pci_write_config_dword(dev, drive_pci, list_conf);
590
591 return ide_config_drive_speed(drive, speed);
592}
593
594static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
595{
b39b01ff
AC		 596 ide_hwif_t *hwif = drive->hwif;
597 struct pci_dev *dev = hwif->pci_dev;
598 struct hpt_info *info = ide_get_hwifdata(hwif);
1da177e4 599 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
b39b01ff 600 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51;
1da177e4
LT		 601 u8 drive_fast = 0, drive_pci = 0x40 + (drive->dn * 4);
602 u32 list_conf = 0, drive_conf = 0;
603 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
604
605 /*
606 * Disable the "fast interrupt" prediction.
607 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
608 */
609 pci_read_config_byte(dev, regfast, &drive_fast);
610 drive_fast &= ~0x07;
611 pci_write_config_byte(dev, regfast, drive_fast);
b39b01ff
AC		 612
613 list_conf = pci_bus_clock_list(speed, info->speed);
1da177e4
LT		 614 pci_read_config_dword(dev, drive_pci, &drive_conf);
615 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
616 if (speed < XFER_MW_DMA_0)
617 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
618 pci_write_config_dword(dev, drive_pci, list_conf);
619
620 return ide_config_drive_speed(drive, speed);
621}
622
623static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
624{
b39b01ff
AC		 625 ide_hwif_t *hwif = drive->hwif;
626 struct hpt_info *info = ide_get_hwifdata(hwif);
1da177e4 627
b39b01ff 628 if (info->revision >= 8)
1da177e4 629 return hpt372_tune_chipset(drive, speed); /* not a typo */
b39b01ff 630 else if (info->revision >= 5)
1da177e4 631 return hpt372_tune_chipset(drive, speed);
b39b01ff 632 else if (info->revision >= 3)
1da177e4
LT		 633 return hpt370_tune_chipset(drive, speed);
634 else /* hpt368: hpt_minimum_revision(dev, 2) */
635 return hpt36x_tune_chipset(drive, speed);
636}
637
638static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
639{
640 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
641 (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
642}
643
644/*
645 * This allows the configuration of ide_pci chipset registers
646 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
647 * after the drive is reported by the OS. Initially for designed for
648 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
649 *
650 * check_in_drive_lists(drive, bad_ata66_4)
651 * check_in_drive_lists(drive, bad_ata66_3)
652 * check_in_drive_lists(drive, bad_ata33)
653 *
654 */
655static int config_chipset_for_dma (ide_drive_t *drive)
656{
657 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
b39b01ff
AC		 658 ide_hwif_t *hwif = drive->hwif;
659 struct hpt_info *info = ide_get_hwifdata(hwif);
1da177e4 660
b39b01ff
AC		 661 if (!speed)
662 return 0;
663
664 /* If we don't have any timings we can't do a lot */
665 if (info->speed == NULL)
1da177e4
LT		 666 return 0;
667
668 (void) hpt3xx_tune_chipset(drive, speed);
669 return ide_dma_enable(drive);
670}
671
672static int hpt3xx_quirkproc (ide_drive_t *drive)
673{
674 return ((int) check_in_drive_lists(drive, quirk_drives));
675}
676
677static void hpt3xx_intrproc (ide_drive_t *drive)
678{
b39b01ff 679 ide_hwif_t *hwif = drive->hwif;
1da177e4
LT		 680
681 if (drive->quirk_list)
682 return;
683 /* drives in the quirk_list may not like intr setups/cleanups */
684 hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
685}
686
687static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
688{
b39b01ff
AC		 689 ide_hwif_t *hwif = drive->hwif;
690 struct hpt_info *info = ide_get_hwifdata(hwif);
691 struct pci_dev *dev = hwif->pci_dev;
1da177e4
LT		 692
693 if (drive->quirk_list) {
b39b01ff 694 if (info->revision >= 3) {
1da177e4
LT		 695 u8 reg5a = 0;
696 pci_read_config_byte(dev, 0x5a, &reg5a);
697 if (((reg5a & 0x10) >> 4) != mask)
698 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
699 } else {
700 if (mask) {
b39b01ff 701 disable_irq(hwif->irq);
1da177e4 702 } else {
b39b01ff 703 enable_irq(hwif->irq);
1da177e4
LT		 704 }
705 }
706 } else {
707 if (IDE_CONTROL_REG)
b39b01ff 708 hwif->OUTB(mask ? (drive->ctl | 2) :
1da177e4
LT		 709 (drive->ctl & ~2),
710 IDE_CONTROL_REG);
711 }
712}
713
714static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
715{
b39b01ff 716 ide_hwif_t *hwif = drive->hwif;
1da177e4
LT		 717 struct hd_driveid *id = drive->id;
718
719 drive->init_speed = 0;
720
b39b01ff 721 if ((id->capability & 1) && drive->autodma) {
1da177e4
LT		 722
723 if (ide_use_dma(drive)) {
724 if (config_chipset_for_dma(drive))
725 return hwif->ide_dma_on(drive);
726 }
727
728 goto fast_ata_pio;
729
730 } else if ((id->capability & 8) || (id->field_valid & 2)) {
731fast_ata_pio:
732 hpt3xx_tune_drive(drive, 5);
733 return hwif->ide_dma_off_quietly(drive);
734 }
735 /* IORDY not supported */
736 return 0;
737}
738
739/*
740 * This is specific to the HPT366 UDMA bios chipset
741 * by HighPoint|Triones Technologies, Inc.
742 */
743static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
744{
745 struct pci_dev *dev = HWIF(drive)->pci_dev;
746 u8 reg50h = 0, reg52h = 0, reg5ah = 0;
747
748 pci_read_config_byte(dev, 0x50, &reg50h);
749 pci_read_config_byte(dev, 0x52, &reg52h);
750 pci_read_config_byte(dev, 0x5a, &reg5ah);
751 printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
752 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
753 if (reg5ah & 0x10)
754 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1da177e4
LT		 755 return __ide_dma_lostirq(drive);
756}
757
758static void hpt370_clear_engine (ide_drive_t *drive)
759{
760 u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
761 pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
762 udelay(10);
763}
764
765static void hpt370_ide_dma_start(ide_drive_t *drive)
766{
767#ifdef HPT_RESET_STATE_ENGINE
768 hpt370_clear_engine(drive);
769#endif
770 ide_dma_start(drive);
771}
772
773static int hpt370_ide_dma_end (ide_drive_t *drive)
774{
775 ide_hwif_t *hwif = HWIF(drive);
776 u8 dma_stat = hwif->INB(hwif->dma_status);
777
778 if (dma_stat & 0x01) {
779 /* wait a little */
780 udelay(20);
781 dma_stat = hwif->INB(hwif->dma_status);
782 }
783 if ((dma_stat & 0x01) != 0)
784 /* fallthrough */
785 (void) HWIF(drive)->ide_dma_timeout(drive);
786
787 return __ide_dma_end(drive);
788}
789
790static void hpt370_lostirq_timeout (ide_drive_t *drive)
791{
792 ide_hwif_t *hwif = HWIF(drive);
793 u8 bfifo = 0, reginfo = hwif->channel ? 0x56 : 0x52;
794 u8 dma_stat = 0, dma_cmd = 0;
795
796 pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
b39b01ff 797 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
1da177e4
LT		 798 hpt370_clear_engine(drive);
799 /* get dma command mode */
800 dma_cmd = hwif->INB(hwif->dma_command);
801 /* stop dma */
802 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
803 dma_stat = hwif->INB(hwif->dma_status);
804 /* clear errors */
805 hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
806}
807
808static int hpt370_ide_dma_timeout (ide_drive_t *drive)
809{
810 hpt370_lostirq_timeout(drive);
811 hpt370_clear_engine(drive);
812 return __ide_dma_timeout(drive);
813}
814
815static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
816{
817 hpt370_lostirq_timeout(drive);
818 hpt370_clear_engine(drive);
819 return __ide_dma_lostirq(drive);
820}
821
822/* returns 1 if DMA IRQ issued, 0 otherwise */
823static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
824{
825 ide_hwif_t *hwif = HWIF(drive);
826 u16 bfifo = 0;
827 u8 reginfo = hwif->channel ? 0x56 : 0x52;
828 u8 dma_stat;
829
830 pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
831 if (bfifo & 0x1FF) {
832// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
833 return 0;
834 }
835
836 dma_stat = hwif->INB(hwif->dma_status);
837 /* return 1 if INTR asserted */
838 if ((dma_stat & 4) == 4)
839 return 1;
840
841 if (!drive->waiting_for_dma)
842 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
843 drive->name, __FUNCTION__);
844 return 0;
845}
846
847static int hpt374_ide_dma_end (ide_drive_t *drive)
848{
849 struct pci_dev *dev = HWIF(drive)->pci_dev;
850 ide_hwif_t *hwif = HWIF(drive);
851 u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
852 u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
853
854 pci_read_config_byte(dev, 0x6a, &bwsr_stat);
855 pci_read_config_byte(dev, mscreg, &msc_stat);
856 if ((bwsr_stat & bwsr_mask) == bwsr_mask)
857 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
858 return __ide_dma_end(drive);
859}
860
861/**
836c0063
SS		 862 * hpt3xxn_set_clock - perform clock switching dance
863 * @hwif: hwif to switch
864 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
1da177e4 865 *
836c0063
SS		 866 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
867 * NOTE: avoid touching the disabled primary channel on HPT371N -- it
868 * doesn't physically exist anyway...
1da177e4 869 */
836c0063
SS		 870
871static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
1da177e4 872{
836c0063
SS		 873 u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);
874
875 if ((scr2 & 0x7f) == mode)
876 return;
877
878 /* MISC. control register 1 has the channel enable bit... */
879 mcr1 = hwif->INB(hwif->dma_master + 0x70);
880
1da177e4 881 /* Tristate the bus */
836c0063
SS		 882 if (mcr1 & 0x04)
883 hwif->OUTB(0x80, hwif->dma_master + 0x73);
884 hwif->OUTB(0x80, hwif->dma_master + 0x77);
885
1da177e4 886 /* Switch clock and reset channels */
836c0063
SS		 887 hwif->OUTB(mode, hwif->dma_master + 0x7b);
888 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
889
1da177e4 890 /* Reset state machines */
836c0063
SS		 891 if (mcr1 & 0x04)
892 hwif->OUTB(0x37, hwif->dma_master + 0x70);
893 hwif->OUTB(0x37, hwif->dma_master + 0x74);
894
1da177e4 895 /* Complete reset */
836c0063
SS		 896 hwif->OUTB(0x00, hwif->dma_master + 0x79);
897
1da177e4 898 /* Reconnect channels to bus */
836c0063
SS		 899 if (mcr1 & 0x04)
900 hwif->OUTB(0x00, hwif->dma_master + 0x73);
901 hwif->OUTB(0x00, hwif->dma_master + 0x77);
1da177e4
LT		 902}
903
904/**
836c0063 905 * hpt3xxn_rw_disk - prepare for I/O
1da177e4
LT		 906 * @drive: drive for command
907 * @rq: block request structure
908 *
836c0063 909 * This is called when a disk I/O is issued to HPT3xxN.
1da177e4
LT		 910 * We need it because of the clock switching.
911 */
912
836c0063 913static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
1da177e4 914{
836c0063
SS		 915 ide_hwif_t *hwif = HWIF(drive);
916 u8 wantclock = rq_data_dir(rq) ? 0x23 : 0x21;
1da177e4 917
836c0063 918 hpt3xxn_set_clock(hwif, wantclock);
1da177e4
LT		 919}
920
1da177e4 921/*
33b18a60 922 * Set/get power state for a drive.
1da177e4 923 *
33b18a60 924 * When we turn the power back on, we need to re-initialize things.
1da177e4
LT		 925 */
926#define TRISTATE_BIT 0x8000
33b18a60
SS		 927
928static int hpt3xx_busproc(ide_drive_t *drive, int state)
1da177e4 929{
b39b01ff 930 ide_hwif_t *hwif = drive->hwif;
1da177e4 931 struct pci_dev *dev = hwif->pci_dev;
33b18a60
SS		 932 u8 tristate, resetmask, bus_reg = 0;
933 u16 tri_reg = 0;
1da177e4
LT		 934
935 hwif->bus_state = state;
936
937 if (hwif->channel) {
938 /* secondary channel */
33b18a60
SS		 939 tristate = 0x56;
940 resetmask = 0x80;
1da177e4
LT		 941 } else {
942 /* primary channel */
33b18a60 943 tristate = 0x52;
1da177e4
LT		 944 resetmask = 0x40;
945 }
946
33b18a60 947 /* Grab the status. */
1da177e4
LT		 948 pci_read_config_word(dev, tristate, &tri_reg);
949 pci_read_config_byte(dev, 0x59, &bus_reg);
950
33b18a60
SS		 951 /*
952 * Set the state. We don't set it if we don't need to do so.
953 * Make sure that the drive knows that it has failed if it's off.
954 */
1da177e4
LT		 955 switch (state) {
956 case BUSSTATE_ON:
33b18a60 957 if (!(bus_reg & resetmask))
1da177e4 958 return 0;
33b18a60
SS		 959 hwif->drives[0].failures = hwif->drives[1].failures = 0;
960
961 pci_write_config_byte(dev, 0x59, bus_reg & ~resetmask);
962 pci_write_config_word(dev, tristate, tri_reg & ~TRISTATE_BIT);
963 return 0;
1da177e4 964 case BUSSTATE_OFF:
33b18a60 965 if ((bus_reg & resetmask) && !(tri_reg & TRISTATE_BIT))
1da177e4
LT		 966 return 0;
967 tri_reg &= ~TRISTATE_BIT;
1da177e4
LT		 968 break;
969 case BUSSTATE_TRISTATE:
33b18a60 970 if ((bus_reg & resetmask) && (tri_reg & TRISTATE_BIT))
1da177e4
LT		 971 return 0;
972 tri_reg |= TRISTATE_BIT;
1da177e4 973 break;
33b18a60
SS		 974 default:
975 return -EINVAL;
1da177e4 976 }
1da177e4 977
33b18a60
SS		 978 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
979 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
980
981 pci_write_config_word(dev, tristate, tri_reg);
982 pci_write_config_byte(dev, 0x59, bus_reg | resetmask);
1da177e4
LT		 983 return 0;
984}
985
b39b01ff 986static void __devinit hpt366_clocking(ide_hwif_t *hwif)
1da177e4 987{
b39b01ff
AC		 988 u32 reg1 = 0;
989 struct hpt_info *info = ide_get_hwifdata(hwif);
990
991 pci_read_config_dword(hwif->pci_dev, 0x40, &reg1);
992
993 /* detect bus speed by looking at control reg timing: */
994 switch((reg1 >> 8) & 7) {
995 case 5:
471a0bda 996 info->speed = forty_base_hpt36x;
b39b01ff
AC		 997 break;
998 case 9:
471a0bda 999 info->speed = twenty_five_base_hpt36x;
b39b01ff
AC		 1000 break;
1001 case 7:
1002 default:
471a0bda 1003 info->speed = thirty_three_base_hpt36x;
b39b01ff
AC		 1004 break;
1005 }
1006}
1007
1008static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1009{
1010 struct hpt_info *info = ide_get_hwifdata(hwif);
1011 struct pci_dev *dev = hwif->pci_dev;
1da177e4
LT		 1012 int adjust, i;
1013 u16 freq;
1014 u32 pll;
836c0063 1015 u8 reg5bh = 0, mcr1 = 0;
1da177e4 1016
1da177e4
LT		 1017 /*
1018 * default to pci clock. make sure MA15/16 are set to output
b39b01ff
AC		 1019 * to prevent drives having problems with 40-pin cables. Needed
1020 * for some drives such as IBM-DTLA which will not enter ready
1021 * state on reset when PDIAG is a input.
1022 *
1023 * ToDo: should we set 0x21 when using PLL mode ?
1da177e4
LT		 1024 */
1025 pci_write_config_byte(dev, 0x5b, 0x23);
1026
1027 /*
1028 * set up the PLL. we need to adjust it so that it's stable.
1029 * freq = Tpll * 192 / Tpci
1030 *
1031 * Todo. For non x86 should probably check the dword is
1032 * set to 0xABCDExxx indicating the BIOS saved f_CNT
1033 */
1034 pci_read_config_word(dev, 0x78, &freq);
1035 freq &= 0x1FF;
1036
1037 /*
836c0063
SS		 1038 * HPT3xxN chips use different PCI clock information.
1039 * Currently we always set up the PLL for them.
1da177e4 1040 */
836c0063
SS		 1041
1042 if (info->flags & IS_3xxN) {
1da177e4
LT		 1043 if(freq < 0x55)
1044 pll = F_LOW_PCI_33;
1045 else if(freq < 0x70)
1046 pll = F_LOW_PCI_40;
1047 else if(freq < 0x7F)
1048 pll = F_LOW_PCI_50;
1049 else
1050 pll = F_LOW_PCI_66;
836c0063
SS		 1051
1052 printk(KERN_INFO "HPT3xxN detected, FREQ: %d, PLL: %d\n", freq, pll);
1da177e4
LT		 1053 }
1054 else
1055 {
1056 if(freq < 0x9C)
1057 pll = F_LOW_PCI_33;
1058 else if(freq < 0xb0)
1059 pll = F_LOW_PCI_40;
1060 else if(freq <0xc8)
1061 pll = F_LOW_PCI_50;
1062 else
1063 pll = F_LOW_PCI_66;
1064
1065 if (pll == F_LOW_PCI_33) {
471a0bda 1066 info->speed = thirty_three_base_hpt37x;
b39b01ff 1067 printk(KERN_DEBUG "HPT37X: using 33MHz PCI clock\n");
1da177e4
LT		 1068 } else if (pll == F_LOW_PCI_40) {
1069 /* Unsupported */
1070 } else if (pll == F_LOW_PCI_50) {
471a0bda 1071 info->speed = fifty_base_hpt37x;
b39b01ff 1072 printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n");
1da177e4 1073 } else {
471a0bda
SS		 1074 info->speed = sixty_six_base_hpt37x;
1075 printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1da177e4
LT		 1076 }
1077 }
836c0063
SS		 1078
1079 if (pll == F_LOW_PCI_66)
1080 info->flags |= PCI_66MHZ;
1081
1da177e4
LT		 1082 /*
1083 * only try the pll if we don't have a table for the clock
1084 * speed that we're running at. NOTE: the internal PLL will
1085 * result in slow reads when using a 33MHz PCI clock. we also
1086 * don't like to use the PLL because it will cause glitches
1087 * on PRST/SRST when the HPT state engine gets reset.
b39b01ff
AC		 1088 *
1089 * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1090 * 372 device so we can get ATA133 support
1da177e4 1091 */
b39b01ff 1092 if (info->speed)
1da177e4 1093 goto init_hpt37X_done;
b39b01ff
AC		 1094
1095 info->flags |= PLL_MODE;
1da177e4
LT		 1096
1097 /*
b39b01ff
AC		 1098 * FIXME: make this work correctly, esp with 372N as per
1099 * reference driver code.
1100 *
1da177e4
LT		 1101 * adjust PLL based upon PCI clock, enable it, and wait for
1102 * stabilization.
1103 */
1104 adjust = 0;
1105 freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1106 while (adjust++ < 6) {
1107 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1108 pll | 0x100);
1109
1110 /* wait for clock stabilization */
1111 for (i = 0; i < 0x50000; i++) {
1112 pci_read_config_byte(dev, 0x5b, &reg5bh);
1113 if (reg5bh & 0x80) {
1114 /* spin looking for the clock to destabilize */
1115 for (i = 0; i < 0x1000; ++i) {
1116 pci_read_config_byte(dev, 0x5b,
1117 &reg5bh);
1118 if ((reg5bh & 0x80) == 0)
1119 goto pll_recal;
1120 }
1121 pci_read_config_dword(dev, 0x5c, &pll);
1122 pci_write_config_dword(dev, 0x5c,
1123 pll & ~0x100);
1124 pci_write_config_byte(dev, 0x5b, 0x21);
471a0bda
SS		 1125
1126 info->speed = fifty_base_hpt37x;
1da177e4
LT		 1127 printk("HPT37X: using 50MHz internal PLL\n");
1128 goto init_hpt37X_done;
1129 }
1130 }
1131pll_recal:
1132 if (adjust & 1)
1133 pll -= (adjust >> 1);
1134 else
1135 pll += (adjust >> 1);
1136 }
1137
1138init_hpt37X_done:
b39b01ff 1139 if (!info->speed)
836c0063
SS		 1140 printk(KERN_ERR "HPT37x%s: unknown bus timing [%d %d].\n",
1141 (info->flags & IS_3xxN) ? "N" : "", pll, freq);
1142 /*
1143 * Reset the state engines.
1144 * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1145 */
1146 pci_read_config_byte(dev, 0x50, &mcr1);
1147 if (mcr1 & 0x04)
1148 pci_write_config_byte(dev, 0x50, 0x37);
1149 pci_write_config_byte(dev, 0x54, 0x37);
1da177e4 1150 udelay(100);
b39b01ff
AC		 1151}
1152
1153static int __devinit init_hpt37x(struct pci_dev *dev)
1154{
1155 u8 reg5ah;
1156
1157 pci_read_config_byte(dev, 0x5a, &reg5ah);
1158 /* interrupt force enable */
1159 pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1da177e4
LT		 1160 return 0;
1161}
1162
1163static int __devinit init_hpt366(struct pci_dev *dev)
1164{
1165 u32 reg1 = 0;
1166 u8 drive_fast = 0;
1167
1168 /*
1169 * Disable the "fast interrupt" prediction.
1170 */
1171 pci_read_config_byte(dev, 0x51, &drive_fast);
1172 if (drive_fast & 0x80)
1173 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1174 pci_read_config_dword(dev, 0x40, &reg1);
1175
1da177e4
LT		 1176 return 0;
1177}
1178
1179static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1180{
1181 int ret = 0;
9ec4ff42
LT		 1182
1183 /*
1184 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1185 * We don't seem to be using it.
1186 */
1da177e4 1187 if (dev->resource[PCI_ROM_RESOURCE].start)
9ec4ff42 1188 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1da177e4
LT		 1189 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1190
b39b01ff
AC		 1191 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1192 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1193 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1194 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1da177e4 1195
b39b01ff 1196 if (hpt_revision(dev) >= 3)
1da177e4 1197 ret = init_hpt37x(dev);
b39b01ff
AC		 1198 else
1199 ret = init_hpt366(dev);
1200
1da177e4
LT		 1201 if (ret)
1202 return ret;
1203
1204 return dev->irq;
1205}
1206
1207static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1208{
1209 struct pci_dev *dev = hwif->pci_dev;
b39b01ff 1210 struct hpt_info *info = ide_get_hwifdata(hwif);
1da177e4 1211 u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02;
836c0063 1212 int serialize = HPT_SERIALIZE_IO;
1da177e4 1213
1da177e4
LT		 1214 hwif->tuneproc = &hpt3xx_tune_drive;
1215 hwif->speedproc = &hpt3xx_tune_chipset;
1216 hwif->quirkproc = &hpt3xx_quirkproc;
1217 hwif->intrproc = &hpt3xx_intrproc;
1218 hwif->maskproc = &hpt3xx_maskproc;
1219
836c0063
SS		 1220 /*
1221 * HPT3xxN chips have some complications:
1222 *
1223 * - on 33 MHz PCI we must clock switch
1224 * - on 66 MHz PCI we must NOT use the PCI clock
1225 */
1226 if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
1227 /*
1228 * Clock is shared between the channels,
1229 * so we'll have to serialize them... :-(
1230 */
1231 serialize = 1;
1232 hwif->rw_disk = &hpt3xxn_rw_disk;
1233 }
1da177e4
LT		 1234
1235 /*
1236 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1237 * address lines to access an external eeprom. To read valid
1238 * cable detect state the pins must be enabled as inputs.
1239 */
b39b01ff 1240 if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1da177e4
LT		 1241 /*
1242 * HPT374 PCI function 1
1243 * - set bit 15 of reg 0x52 to enable TCBLID as input
1244 * - set bit 15 of reg 0x56 to enable FCBLID as input
1245 */
1246 u16 mcr3, mcr6;
1247 pci_read_config_word(dev, 0x52, &mcr3);
1248 pci_read_config_word(dev, 0x56, &mcr6);
1249 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1250 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1251 /* now read cable id register */
1252 pci_read_config_byte(dev, 0x5a, &ata66);
1253 pci_write_config_word(dev, 0x52, mcr3);
1254 pci_write_config_word(dev, 0x56, mcr6);
b39b01ff 1255 } else if (info->revision >= 3) {
1da177e4
LT		 1256 /*
1257 * HPT370/372 and 374 pcifn 0
1258 * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1259 */
1260 u8 scr2;
1261 pci_read_config_byte(dev, 0x5b, &scr2);
1262 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1263 /* now read cable id register */
1264 pci_read_config_byte(dev, 0x5a, &ata66);
1265 pci_write_config_byte(dev, 0x5b, scr2);
1266 } else {
1267 pci_read_config_byte(dev, 0x5a, &ata66);
1268 }
1269
1270#ifdef DEBUG
1271 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1272 ata66, (ata66 & regmask) ? "33" : "66",
1273 PCI_FUNC(hwif->pci_dev->devfn));
1274#endif /* DEBUG */
1275
836c0063
SS		 1276 /* Serialize access to this device */
1277 if (serialize && hwif->mate)
1da177e4 1278 hwif->serialized = hwif->mate->serialized = 1;
1da177e4 1279
33b18a60
SS		 1280 /*
1281 * Set up ioctl for power status.
1282 * NOTE: power affects both drives on each channel.
1283 */
1284 hwif->busproc = &hpt3xx_busproc;
1da177e4
LT		 1285
1286 if (!hwif->dma_base) {
1287 hwif->drives[0].autotune = 1;
1288 hwif->drives[1].autotune = 1;
1289 return;
1290 }
1291
1292 hwif->ultra_mask = 0x7f;
1293 hwif->mwdma_mask = 0x07;
1294
1295 if (!(hwif->udma_four))
1296 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1297 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1298
b39b01ff 1299 if (info->revision >= 8) {
1da177e4
LT		 1300 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1301 hwif->ide_dma_end = &hpt374_ide_dma_end;
b39b01ff 1302 } else if (info->revision >= 5) {
1da177e4
LT		 1303 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1304 hwif->ide_dma_end = &hpt374_ide_dma_end;
b39b01ff 1305 } else if (info->revision >= 3) {
1da177e4
LT		 1306 hwif->dma_start = &hpt370_ide_dma_start;
1307 hwif->ide_dma_end = &hpt370_ide_dma_end;
1308 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1309 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
b39b01ff 1310 } else if (info->revision >= 2)
1da177e4
LT		 1311 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1312 else
1313 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1314
1315 if (!noautodma)
1316 hwif->autodma = 1;
1317 hwif->drives[0].autodma = hwif->autodma;
1318 hwif->drives[1].autodma = hwif->autodma;
1319}
1320
1321static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1322{
b39b01ff 1323 struct hpt_info *info = ide_get_hwifdata(hwif);
1da177e4
LT		 1324 u8 masterdma = 0, slavedma = 0;
1325 u8 dma_new = 0, dma_old = 0;
1326 u8 primary = hwif->channel ? 0x4b : 0x43;
1327 u8 secondary = hwif->channel ? 0x4f : 0x47;
1328 unsigned long flags;
1329
1330 if (!dmabase)
1331 return;
1332
b39b01ff 1333 if(info->speed == NULL) {
836c0063 1334 printk(KERN_WARNING "hpt366: no known IDE timings, disabling DMA.\n");
1da177e4
LT		 1335 return;
1336 }
1337
1338 dma_old = hwif->INB(dmabase+2);
1339
1340 local_irq_save(flags);
1341
1342 dma_new = dma_old;
1343 pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1344 pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1345
1346 if (masterdma & 0x30) dma_new |= 0x20;
1347 if (slavedma & 0x30) dma_new |= 0x40;
1348 if (dma_new != dma_old)
1349 hwif->OUTB(dma_new, dmabase+2);
1350
1351 local_irq_restore(flags);
1352
1353 ide_setup_dma(hwif, dmabase, 8);
1354}
1355
b39b01ff
AC		 1356/*
1357 * We "borrow" this hook in order to set the data structures
1358 * up early enough before dma or init_hwif calls are made.
1359 */
1360
1361static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1362{
836c0063
SS		 1363 struct hpt_info *info = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1364 struct pci_dev *dev = hwif->pci_dev;
1365 u16 did = dev->device;
1366 u8 rid = 0;
b39b01ff
AC		 1367
1368 if(info == NULL) {
1369 printk(KERN_WARNING "hpt366: out of memory.\n");
1370 return;
1371 }
b39b01ff
AC		 1372 ide_set_hwifdata(hwif, info);
1373
836c0063
SS		 1374 /* Avoid doing the same thing twice. */
1375 if (hwif->channel && hwif->mate) {
1376 memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
1377 return;
b39b01ff
AC		 1378 }
1379
836c0063
SS		 1380 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rid);
1381
1382 if (( did == PCI_DEVICE_ID_TTI_HPT366 && rid == 6) ||
1383 ((did == PCI_DEVICE_ID_TTI_HPT372 ||
1384 did == PCI_DEVICE_ID_TTI_HPT302 ||
1385 did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
1386 did == PCI_DEVICE_ID_TTI_HPT372N)
1387 info->flags |= IS_3xxN;
1388
1389 info->revision = hpt_revision(dev);
b39b01ff
AC		 1390
1391 if (info->revision >= 3)
1392 hpt37x_clocking(hwif);
1393 else
1394 hpt366_clocking(hwif);
1395}
1396
1da177e4
LT		 1397static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1398{
1399 struct pci_dev *findev = NULL;
1400
1401 if (PCI_FUNC(dev->devfn) & 1)
1402 return -ENODEV;
1403
1404 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1405 if ((findev->vendor == dev->vendor) &&
1406 (findev->device == dev->device) &&
1407 ((findev->devfn - dev->devfn) == 1) &&
1408 (PCI_FUNC(findev->devfn) & 1)) {
1409 if (findev->irq != dev->irq) {
1410 /* FIXME: we need a core pci_set_interrupt() */
1411 findev->irq = dev->irq;
1412 printk(KERN_WARNING "%s: pci-config space interrupt "
1413 "fixed.\n", d->name);
1414 }
1415 return ide_setup_pci_devices(dev, findev, d);
1416 }
1417 }
1418 return ide_setup_pci_device(dev, d);
1419}
1420
1421static int __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1422{
1423 return ide_setup_pci_device(dev, d);
1424}
1425
836c0063
SS		 1426static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1427{
1428 u8 mcr1 = 0;
1429
1430 /*
1431 * HPT371 chips physically have only one channel, the secondary one,
1432 * but the primary channel registers do exist! Go figure...
1433 * So, we manually disable the non-existing channel here
1434 * (if the BIOS hasn't done this already).
1435 */
1436 pci_read_config_byte(dev, 0x50, &mcr1);
1437 if (mcr1 & 0x04)
1438 pci_write_config_byte(dev, 0x50, (mcr1 & ~0x04));
1439
1440 return ide_setup_pci_device(dev, d);
1441}
1442
1da177e4
LT		 1443static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1444{
1445 struct pci_dev *findev = NULL;
1446 u8 pin1 = 0, pin2 = 0;
1447 unsigned int class_rev;
1448 char *chipset_names[] = {"HPT366", "HPT366", "HPT368",
1449 "HPT370", "HPT370A", "HPT372",
1450 "HPT372N" };
1451
1452 if (PCI_FUNC(dev->devfn) & 1)
1453 return -ENODEV;
1454
1455 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1456 class_rev &= 0xff;
1457
1458 if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1459 class_rev = 6;
1460
1461 if(class_rev <= 6)
1462 d->name = chipset_names[class_rev];
1463
1464 switch(class_rev) {
1465 case 6:
1466 case 5:
1467 case 4:
1468 case 3:
1469 goto init_single;
1470 default:
1471 break;
1472 }
1473
1474 d->channels = 1;
1475
1476 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1477 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1478 if ((findev->vendor == dev->vendor) &&
1479 (findev->device == dev->device) &&
1480 ((findev->devfn - dev->devfn) == 1) &&
1481 (PCI_FUNC(findev->devfn) & 1)) {
1482 pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1483 if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1484 d->bootable = ON_BOARD;
1485 printk("%s: onboard version of chipset, "
1486 "pin1=%d pin2=%d\n", d->name,
1487 pin1, pin2);
1488 }
1489 return ide_setup_pci_devices(dev, findev, d);
1490 }
1491 }
1492init_single:
1493 return ide_setup_pci_device(dev, d);
1494}
1495
1496static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1497 { /* 0 */
1498 .name = "HPT366",
1499 .init_setup = init_setup_hpt366,
1500 .init_chipset = init_chipset_hpt366,
b39b01ff 1501 .init_iops = init_iops_hpt366,
1da177e4
LT		 1502 .init_hwif = init_hwif_hpt366,
1503 .init_dma = init_dma_hpt366,
1504 .channels = 2,
1505 .autodma = AUTODMA,
1506 .bootable = OFF_BOARD,
1507 .extra = 240
1508 },{ /* 1 */
1509 .name = "HPT372A",
1510 .init_setup = init_setup_hpt37x,
1511 .init_chipset = init_chipset_hpt366,
b39b01ff 1512 .init_iops = init_iops_hpt366,
1da177e4
LT		 1513 .init_hwif = init_hwif_hpt366,
1514 .init_dma = init_dma_hpt366,
1515 .channels = 2,
1516 .autodma = AUTODMA,
1517 .bootable = OFF_BOARD,
1518 },{ /* 2 */
1519 .name = "HPT302",
1520 .init_setup = init_setup_hpt37x,
1521 .init_chipset = init_chipset_hpt366,
b39b01ff 1522 .init_iops = init_iops_hpt366,
1da177e4
LT		 1523 .init_hwif = init_hwif_hpt366,
1524 .init_dma = init_dma_hpt366,
1525 .channels = 2,
1526 .autodma = AUTODMA,
1527 .bootable = OFF_BOARD,
1528 },{ /* 3 */
1529 .name = "HPT371",
836c0063 1530 .init_setup = init_setup_hpt371,
1da177e4 1531 .init_chipset = init_chipset_hpt366,
b39b01ff 1532 .init_iops = init_iops_hpt366,
1da177e4
LT		 1533 .init_hwif = init_hwif_hpt366,
1534 .init_dma = init_dma_hpt366,
1535 .channels = 2,
1536 .autodma = AUTODMA,
836c0063 1537 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1da177e4
LT		 1538 .bootable = OFF_BOARD,
1539 },{ /* 4 */
1540 .name = "HPT374",
1541 .init_setup = init_setup_hpt374,
1542 .init_chipset = init_chipset_hpt366,
b39b01ff 1543 .init_iops = init_iops_hpt366,
1da177e4
LT		 1544 .init_hwif = init_hwif_hpt366,
1545 .init_dma = init_dma_hpt366,
1546 .channels = 2, /* 4 */
1547 .autodma = AUTODMA,
1548 .bootable = OFF_BOARD,
1549 },{ /* 5 */
1550 .name = "HPT372N",
1551 .init_setup = init_setup_hpt37x,
1552 .init_chipset = init_chipset_hpt366,
b39b01ff 1553 .init_iops = init_iops_hpt366,
1da177e4
LT		 1554 .init_hwif = init_hwif_hpt366,
1555 .init_dma = init_dma_hpt366,
1556 .channels = 2, /* 4 */
1557 .autodma = AUTODMA,
1558 .bootable = OFF_BOARD,
1559 }
1560};
1561
1562/**
1563 * hpt366_init_one - called when an HPT366 is found
1564 * @dev: the hpt366 device
1565 * @id: the matching pci id
1566 *
1567 * Called when the PCI registration layer (or the IDE initialization)
1568 * finds a device matching our IDE device tables.
73d1dd93
SS		 1569 *
1570 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1571 * structure depending on the chip's revision, we'd better pass a local
1572 * copy down the call chain...
1da177e4 1573 */
1da177e4
LT		 1574static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1575{
73d1dd93 1576 ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1da177e4 1577
73d1dd93 1578 return d.init_setup(dev, &d);
1da177e4
LT		 1579}
1580
1581static struct pci_device_id hpt366_pci_tbl[] = {
1582 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1583 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1584 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1585 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1586 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1587 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1588 { 0, },
1589};
1590MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1591
1592static struct pci_driver driver = {
1593 .name = "HPT366_IDE",
1594 .id_table = hpt366_pci_tbl,
1595 .probe = hpt366_init_one,
1596};
1597
1598static int hpt366_ide_init(void)
1599{
1600 return ide_pci_register_driver(&driver);
1601}
1602
1603module_init(hpt366_ide_init);
1604
1605MODULE_AUTHOR("Andre Hedrick");
1606MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1607MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)