Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
866664d7 | 2 | * linux/drivers/ide/pci/hpt366.c Version 1.30 Dec 12, 2007 |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
5 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
6 | * Portions Copyright (C) 2003 Red Hat Inc | |
fbf47840 | 7 | * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
38b66f84 | 8 | * Portions Copyright (C) 2005-2007 MontaVista Software, Inc. |
1da177e4 LT |
9 | * |
10 | * Thanks to HighPoint Technologies for their assistance, and hardware. | |
11 | * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his | |
12 | * donation of an ABit BP6 mainboard, processor, and memory acellerated | |
13 | * development and support. | |
14 | * | |
b39b01ff | 15 | * |
836c0063 SS |
16 | * HighPoint has its own drivers (open source except for the RAID part) |
17 | * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/. | |
18 | * This may be useful to anyone wanting to work on this driver, however do not | |
19 | * trust them too much since the code tends to become less and less meaningful | |
20 | * as the time passes... :-/ | |
b39b01ff | 21 | * |
1da177e4 LT |
22 | * Note that final HPT370 support was done by force extraction of GPL. |
23 | * | |
24 | * - add function for getting/setting power status of drive | |
25 | * - the HPT370's state machine can get confused. reset it before each dma | |
26 | * xfer to prevent that from happening. | |
27 | * - reset state engine whenever we get an error. | |
28 | * - check for busmaster state at end of dma. | |
29 | * - use new highpoint timings. | |
30 | * - detect bus speed using highpoint register. | |
31 | * - use pll if we don't have a clock table. added a 66MHz table that's | |
32 | * just 2x the 33MHz table. | |
33 | * - removed turnaround. NOTE: we never want to switch between pll and | |
34 | * pci clocks as the chip can glitch in those cases. the highpoint | |
35 | * approved workaround slows everything down too much to be useful. in | |
36 | * addition, we would have to serialize access to each chip. | |
37 | * Adrian Sun <a.sun@sun.com> | |
38 | * | |
39 | * add drive timings for 66MHz PCI bus, | |
40 | * fix ATA Cable signal detection, fix incorrect /proc info | |
41 | * add /proc display for per-drive PIO/DMA/UDMA mode and | |
42 | * per-channel ATA-33/66 Cable detect. | |
43 | * Duncan Laurie <void@sun.com> | |
44 | * | |
45 | * fixup /proc output for multiple controllers | |
46 | * Tim Hockin <thockin@sun.com> | |
47 | * | |
48 | * On hpt366: | |
49 | * Reset the hpt366 on error, reset on dma | |
50 | * Fix disabling Fast Interrupt hpt366. | |
51 | * Mike Waychison <crlf@sun.com> | |
52 | * | |
53 | * Added support for 372N clocking and clock switching. The 372N needs | |
54 | * different clocks on read/write. This requires overloading rw_disk and | |
55 | * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for | |
56 | * keeping me sane. | |
57 | * Alan Cox <alan@redhat.com> | |
58 | * | |
836c0063 SS |
59 | * - fix the clock turnaround code: it was writing to the wrong ports when |
60 | * called for the secondary channel, caching the current clock mode per- | |
61 | * channel caused the cached register value to get out of sync with the | |
62 | * actual one, the channels weren't serialized, the turnaround shouldn't | |
63 | * be done on 66 MHz PCI bus | |
7b73ee05 SS |
64 | * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used |
65 | * does not allow for this speed anyway | |
66 | * - avoid touching disabled channels (e.g. HPT371/N are single channel chips, | |
67 | * their primary channel is kind of virtual, it isn't tied to any pins) | |
471a0bda SS |
68 | * - fix/remove bad/unused timing tables and use one set of tables for the whole |
69 | * HPT37x chip family; save space by introducing the separate transfer mode | |
70 | * table in which the mode lookup is done | |
26c068da | 71 | * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives |
72931368 SS |
72 | * the wrong PCI frequency since DPLL has already been calibrated by BIOS; |
73 | * read it only from the function 0 of HPT374 chips | |
33b18a60 SS |
74 | * - fix the hotswap code: it caused RESET- to glitch when tristating the bus, |
75 | * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead | |
73d1dd93 SS |
76 | * - pass to init_chipset() handlers a copy of the IDE PCI device structure as |
77 | * they tamper with its fields | |
7b73ee05 SS |
78 | * - pass to the init_setup handlers a copy of the ide_pci_device_t structure |
79 | * since they may tamper with its fields | |
90778574 SS |
80 | * - prefix the driver startup messages with the real chip name |
81 | * - claim the extra 240 bytes of I/O space for all chips | |
2648e5d9 | 82 | * - optimize the UltraDMA filtering and the drive list lookup code |
b4586715 | 83 | * - use pci_get_slot() to get to the function 1 of HPT36x/374 |
7b73ee05 SS |
84 | * - cache offset of the channel's misc. control registers (MCRs) being used |
85 | * throughout the driver | |
86 | * - only touch the relevant MCR when detecting the cable type on HPT374's | |
87 | * function 1 | |
abc4ad4c | 88 | * - rename all the register related variables consistently |
7b73ee05 SS |
89 | * - move all the interrupt twiddling code from the speedproc handlers into |
90 | * init_hwif_hpt366(), also grouping all the DMA related code together there | |
866664d7 | 91 | * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and |
7b73ee05 SS |
92 | * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings |
93 | * when setting an UltraDMA mode | |
94 | * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select | |
95 | * the best possible one | |
4bf63de2 | 96 | * - clean up DMA timeout handling for HPT370 |
7b73ee05 SS |
97 | * - switch to using the enumeration type to differ between the numerous chip |
98 | * variants, matching PCI device/revision ID with the chip type early, at the | |
99 | * init_setup stage | |
100 | * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies, | |
101 | * stop duplicating it for each channel by storing the pointer in the pci_dev | |
102 | * structure: first, at the init_setup stage, point it to a static "template" | |
103 | * with only the chip type and its specific base DPLL frequency, the highest | |
2648e5d9 SS |
104 | * UltraDMA mode, and the chip settings table pointer filled, then, at the |
105 | * init_chipset stage, allocate per-chip instance and fill it with the rest | |
106 | * of the necessary information | |
7b73ee05 SS |
107 | * - get rid of the constant thresholds in the HPT37x PCI clock detection code, |
108 | * switch to calculating PCI clock frequency based on the chip's base DPLL | |
109 | * frequency | |
110 | * - switch to using the DPLL clock and enable UltraATA/133 mode by default on | |
278978e9 SS |
111 | * anything newer than HPT370/A (except HPT374 that is not capable of this |
112 | * mode according to the manual) | |
6273d26a SS |
113 | * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(), |
114 | * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips; | |
7b73ee05 SS |
115 | * unify HPT36x/37x timing setup code and the speedproc handlers by joining |
116 | * the register setting lists into the table indexed by the clock selected | |
2648e5d9 | 117 | * - set the correct hwif->ultra_mask for each individual chip |
b4e44369 | 118 | * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards |
7b73ee05 | 119 | * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com> |
1da177e4 LT |
120 | */ |
121 | ||
1da177e4 LT |
122 | #include <linux/types.h> |
123 | #include <linux/module.h> | |
124 | #include <linux/kernel.h> | |
125 | #include <linux/delay.h> | |
126 | #include <linux/timer.h> | |
127 | #include <linux/mm.h> | |
128 | #include <linux/ioport.h> | |
129 | #include <linux/blkdev.h> | |
130 | #include <linux/hdreg.h> | |
131 | ||
132 | #include <linux/interrupt.h> | |
133 | #include <linux/pci.h> | |
134 | #include <linux/init.h> | |
135 | #include <linux/ide.h> | |
136 | ||
137 | #include <asm/uaccess.h> | |
138 | #include <asm/io.h> | |
139 | #include <asm/irq.h> | |
140 | ||
141 | /* various tuning parameters */ | |
142 | #define HPT_RESET_STATE_ENGINE | |
836c0063 SS |
143 | #undef HPT_DELAY_INTERRUPT |
144 | #define HPT_SERIALIZE_IO 0 | |
1da177e4 LT |
145 | |
146 | static const char *quirk_drives[] = { | |
147 | "QUANTUM FIREBALLlct08 08", | |
148 | "QUANTUM FIREBALLP KA6.4", | |
149 | "QUANTUM FIREBALLP LM20.4", | |
150 | "QUANTUM FIREBALLP LM20.5", | |
151 | NULL | |
152 | }; | |
153 | ||
154 | static const char *bad_ata100_5[] = { | |
155 | "IBM-DTLA-307075", | |
156 | "IBM-DTLA-307060", | |
157 | "IBM-DTLA-307045", | |
158 | "IBM-DTLA-307030", | |
159 | "IBM-DTLA-307020", | |
160 | "IBM-DTLA-307015", | |
161 | "IBM-DTLA-305040", | |
162 | "IBM-DTLA-305030", | |
163 | "IBM-DTLA-305020", | |
164 | "IC35L010AVER07-0", | |
165 | "IC35L020AVER07-0", | |
166 | "IC35L030AVER07-0", | |
167 | "IC35L040AVER07-0", | |
168 | "IC35L060AVER07-0", | |
169 | "WDC AC310200R", | |
170 | NULL | |
171 | }; | |
172 | ||
173 | static const char *bad_ata66_4[] = { | |
174 | "IBM-DTLA-307075", | |
175 | "IBM-DTLA-307060", | |
176 | "IBM-DTLA-307045", | |
177 | "IBM-DTLA-307030", | |
178 | "IBM-DTLA-307020", | |
179 | "IBM-DTLA-307015", | |
180 | "IBM-DTLA-305040", | |
181 | "IBM-DTLA-305030", | |
182 | "IBM-DTLA-305020", | |
183 | "IC35L010AVER07-0", | |
184 | "IC35L020AVER07-0", | |
185 | "IC35L030AVER07-0", | |
186 | "IC35L040AVER07-0", | |
187 | "IC35L060AVER07-0", | |
188 | "WDC AC310200R", | |
783353b1 | 189 | "MAXTOR STM3320620A", |
1da177e4 LT |
190 | NULL |
191 | }; | |
192 | ||
193 | static const char *bad_ata66_3[] = { | |
194 | "WDC AC310200R", | |
195 | NULL | |
196 | }; | |
197 | ||
198 | static const char *bad_ata33[] = { | |
199 | "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", | |
200 | "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", | |
201 | "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", | |
202 | "Maxtor 90510D4", | |
203 | "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", | |
204 | "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", | |
205 | "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", | |
206 | NULL | |
207 | }; | |
208 | ||
471a0bda SS |
209 | static u8 xfer_speeds[] = { |
210 | XFER_UDMA_6, | |
211 | XFER_UDMA_5, | |
212 | XFER_UDMA_4, | |
213 | XFER_UDMA_3, | |
214 | XFER_UDMA_2, | |
215 | XFER_UDMA_1, | |
216 | XFER_UDMA_0, | |
217 | ||
218 | XFER_MW_DMA_2, | |
219 | XFER_MW_DMA_1, | |
220 | XFER_MW_DMA_0, | |
221 | ||
222 | XFER_PIO_4, | |
223 | XFER_PIO_3, | |
224 | XFER_PIO_2, | |
225 | XFER_PIO_1, | |
226 | XFER_PIO_0 | |
1da177e4 LT |
227 | }; |
228 | ||
471a0bda SS |
229 | /* Key for bus clock timings |
230 | * 36x 37x | |
231 | * bits bits | |
232 | * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. | |
233 | * cycles = value + 1 | |
234 | * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. | |
235 | * cycles = value + 1 | |
236 | * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file | |
237 | * register access. | |
238 | * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file | |
239 | * register access. | |
240 | * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer. | |
241 | * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock. | |
242 | * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and | |
243 | * MW DMA xfer. | |
244 | * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for | |
245 | * task file register access. | |
246 | * 28 28 UDMA enable. | |
247 | * 29 29 DMA enable. | |
248 | * 30 30 PIO MST enable. If set, the chip is in bus master mode during | |
249 | * PIO xfer. | |
250 | * 31 31 FIFO enable. | |
1da177e4 | 251 | */ |
1da177e4 | 252 | |
471a0bda SS |
253 | static u32 forty_base_hpt36x[] = { |
254 | /* XFER_UDMA_6 */ 0x900fd943, | |
255 | /* XFER_UDMA_5 */ 0x900fd943, | |
256 | /* XFER_UDMA_4 */ 0x900fd943, | |
257 | /* XFER_UDMA_3 */ 0x900ad943, | |
258 | /* XFER_UDMA_2 */ 0x900bd943, | |
259 | /* XFER_UDMA_1 */ 0x9008d943, | |
260 | /* XFER_UDMA_0 */ 0x9008d943, | |
261 | ||
262 | /* XFER_MW_DMA_2 */ 0xa008d943, | |
263 | /* XFER_MW_DMA_1 */ 0xa010d955, | |
264 | /* XFER_MW_DMA_0 */ 0xa010d9fc, | |
265 | ||
266 | /* XFER_PIO_4 */ 0xc008d963, | |
267 | /* XFER_PIO_3 */ 0xc010d974, | |
268 | /* XFER_PIO_2 */ 0xc010d997, | |
269 | /* XFER_PIO_1 */ 0xc010d9c7, | |
270 | /* XFER_PIO_0 */ 0xc018d9d9 | |
1da177e4 LT |
271 | }; |
272 | ||
471a0bda SS |
273 | static u32 thirty_three_base_hpt36x[] = { |
274 | /* XFER_UDMA_6 */ 0x90c9a731, | |
275 | /* XFER_UDMA_5 */ 0x90c9a731, | |
276 | /* XFER_UDMA_4 */ 0x90c9a731, | |
277 | /* XFER_UDMA_3 */ 0x90cfa731, | |
278 | /* XFER_UDMA_2 */ 0x90caa731, | |
279 | /* XFER_UDMA_1 */ 0x90cba731, | |
280 | /* XFER_UDMA_0 */ 0x90c8a731, | |
281 | ||
282 | /* XFER_MW_DMA_2 */ 0xa0c8a731, | |
283 | /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */ | |
284 | /* XFER_MW_DMA_0 */ 0xa0c8a797, | |
285 | ||
286 | /* XFER_PIO_4 */ 0xc0c8a731, | |
287 | /* XFER_PIO_3 */ 0xc0c8a742, | |
288 | /* XFER_PIO_2 */ 0xc0d0a753, | |
289 | /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */ | |
290 | /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */ | |
1da177e4 LT |
291 | }; |
292 | ||
471a0bda SS |
293 | static u32 twenty_five_base_hpt36x[] = { |
294 | /* XFER_UDMA_6 */ 0x90c98521, | |
295 | /* XFER_UDMA_5 */ 0x90c98521, | |
296 | /* XFER_UDMA_4 */ 0x90c98521, | |
297 | /* XFER_UDMA_3 */ 0x90cf8521, | |
298 | /* XFER_UDMA_2 */ 0x90cf8521, | |
299 | /* XFER_UDMA_1 */ 0x90cb8521, | |
300 | /* XFER_UDMA_0 */ 0x90cb8521, | |
301 | ||
302 | /* XFER_MW_DMA_2 */ 0xa0ca8521, | |
303 | /* XFER_MW_DMA_1 */ 0xa0ca8532, | |
304 | /* XFER_MW_DMA_0 */ 0xa0ca8575, | |
305 | ||
306 | /* XFER_PIO_4 */ 0xc0ca8521, | |
307 | /* XFER_PIO_3 */ 0xc0ca8532, | |
308 | /* XFER_PIO_2 */ 0xc0ca8542, | |
309 | /* XFER_PIO_1 */ 0xc0d08572, | |
310 | /* XFER_PIO_0 */ 0xc0d08585 | |
1da177e4 LT |
311 | }; |
312 | ||
809b53c4 SS |
313 | #if 0 |
314 | /* These are the timing tables from the HighPoint open source drivers... */ | |
471a0bda SS |
315 | static u32 thirty_three_base_hpt37x[] = { |
316 | /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */ | |
317 | /* XFER_UDMA_5 */ 0x12446231, | |
318 | /* XFER_UDMA_4 */ 0x12446231, | |
319 | /* XFER_UDMA_3 */ 0x126c6231, | |
320 | /* XFER_UDMA_2 */ 0x12486231, | |
321 | /* XFER_UDMA_1 */ 0x124c6233, | |
322 | /* XFER_UDMA_0 */ 0x12506297, | |
323 | ||
324 | /* XFER_MW_DMA_2 */ 0x22406c31, | |
325 | /* XFER_MW_DMA_1 */ 0x22406c33, | |
326 | /* XFER_MW_DMA_0 */ 0x22406c97, | |
327 | ||
328 | /* XFER_PIO_4 */ 0x06414e31, | |
329 | /* XFER_PIO_3 */ 0x06414e42, | |
330 | /* XFER_PIO_2 */ 0x06414e53, | |
331 | /* XFER_PIO_1 */ 0x06814e93, | |
332 | /* XFER_PIO_0 */ 0x06814ea7 | |
1da177e4 LT |
333 | }; |
334 | ||
471a0bda SS |
335 | static u32 fifty_base_hpt37x[] = { |
336 | /* XFER_UDMA_6 */ 0x12848242, | |
337 | /* XFER_UDMA_5 */ 0x12848242, | |
338 | /* XFER_UDMA_4 */ 0x12ac8242, | |
339 | /* XFER_UDMA_3 */ 0x128c8242, | |
340 | /* XFER_UDMA_2 */ 0x120c8242, | |
341 | /* XFER_UDMA_1 */ 0x12148254, | |
342 | /* XFER_UDMA_0 */ 0x121882ea, | |
343 | ||
344 | /* XFER_MW_DMA_2 */ 0x22808242, | |
345 | /* XFER_MW_DMA_1 */ 0x22808254, | |
346 | /* XFER_MW_DMA_0 */ 0x228082ea, | |
347 | ||
348 | /* XFER_PIO_4 */ 0x0a81f442, | |
349 | /* XFER_PIO_3 */ 0x0a81f443, | |
350 | /* XFER_PIO_2 */ 0x0a81f454, | |
351 | /* XFER_PIO_1 */ 0x0ac1f465, | |
352 | /* XFER_PIO_0 */ 0x0ac1f48a | |
1da177e4 LT |
353 | }; |
354 | ||
471a0bda SS |
355 | static u32 sixty_six_base_hpt37x[] = { |
356 | /* XFER_UDMA_6 */ 0x1c869c62, | |
357 | /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */ | |
358 | /* XFER_UDMA_4 */ 0x1c8a9c62, | |
359 | /* XFER_UDMA_3 */ 0x1c8e9c62, | |
360 | /* XFER_UDMA_2 */ 0x1c929c62, | |
361 | /* XFER_UDMA_1 */ 0x1c9a9c62, | |
362 | /* XFER_UDMA_0 */ 0x1c829c62, | |
363 | ||
364 | /* XFER_MW_DMA_2 */ 0x2c829c62, | |
365 | /* XFER_MW_DMA_1 */ 0x2c829c66, | |
366 | /* XFER_MW_DMA_0 */ 0x2c829d2e, | |
367 | ||
368 | /* XFER_PIO_4 */ 0x0c829c62, | |
369 | /* XFER_PIO_3 */ 0x0c829c84, | |
370 | /* XFER_PIO_2 */ 0x0c829ca6, | |
371 | /* XFER_PIO_1 */ 0x0d029d26, | |
372 | /* XFER_PIO_0 */ 0x0d029d5e | |
1da177e4 | 373 | }; |
809b53c4 SS |
374 | #else |
375 | /* | |
376 | * The following are the new timing tables with PIO mode data/taskfile transfer | |
377 | * overclocking fixed... | |
378 | */ | |
379 | ||
380 | /* This table is taken from the HPT370 data manual rev. 1.02 */ | |
381 | static u32 thirty_three_base_hpt37x[] = { | |
382 | /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */ | |
383 | /* XFER_UDMA_5 */ 0x16455031, | |
384 | /* XFER_UDMA_4 */ 0x16455031, | |
385 | /* XFER_UDMA_3 */ 0x166d5031, | |
386 | /* XFER_UDMA_2 */ 0x16495031, | |
387 | /* XFER_UDMA_1 */ 0x164d5033, | |
388 | /* XFER_UDMA_0 */ 0x16515097, | |
389 | ||
390 | /* XFER_MW_DMA_2 */ 0x26515031, | |
391 | /* XFER_MW_DMA_1 */ 0x26515033, | |
392 | /* XFER_MW_DMA_0 */ 0x26515097, | |
393 | ||
394 | /* XFER_PIO_4 */ 0x06515021, | |
395 | /* XFER_PIO_3 */ 0x06515022, | |
396 | /* XFER_PIO_2 */ 0x06515033, | |
397 | /* XFER_PIO_1 */ 0x06915065, | |
398 | /* XFER_PIO_0 */ 0x06d1508a | |
399 | }; | |
400 | ||
401 | static u32 fifty_base_hpt37x[] = { | |
402 | /* XFER_UDMA_6 */ 0x1a861842, | |
403 | /* XFER_UDMA_5 */ 0x1a861842, | |
404 | /* XFER_UDMA_4 */ 0x1aae1842, | |
405 | /* XFER_UDMA_3 */ 0x1a8e1842, | |
406 | /* XFER_UDMA_2 */ 0x1a0e1842, | |
407 | /* XFER_UDMA_1 */ 0x1a161854, | |
408 | /* XFER_UDMA_0 */ 0x1a1a18ea, | |
409 | ||
410 | /* XFER_MW_DMA_2 */ 0x2a821842, | |
411 | /* XFER_MW_DMA_1 */ 0x2a821854, | |
412 | /* XFER_MW_DMA_0 */ 0x2a8218ea, | |
413 | ||
414 | /* XFER_PIO_4 */ 0x0a821842, | |
415 | /* XFER_PIO_3 */ 0x0a821843, | |
416 | /* XFER_PIO_2 */ 0x0a821855, | |
417 | /* XFER_PIO_1 */ 0x0ac218a8, | |
418 | /* XFER_PIO_0 */ 0x0b02190c | |
419 | }; | |
420 | ||
421 | static u32 sixty_six_base_hpt37x[] = { | |
422 | /* XFER_UDMA_6 */ 0x1c86fe62, | |
423 | /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */ | |
424 | /* XFER_UDMA_4 */ 0x1c8afe62, | |
425 | /* XFER_UDMA_3 */ 0x1c8efe62, | |
426 | /* XFER_UDMA_2 */ 0x1c92fe62, | |
427 | /* XFER_UDMA_1 */ 0x1c9afe62, | |
428 | /* XFER_UDMA_0 */ 0x1c82fe62, | |
429 | ||
430 | /* XFER_MW_DMA_2 */ 0x2c82fe62, | |
431 | /* XFER_MW_DMA_1 */ 0x2c82fe66, | |
432 | /* XFER_MW_DMA_0 */ 0x2c82ff2e, | |
433 | ||
434 | /* XFER_PIO_4 */ 0x0c82fe62, | |
435 | /* XFER_PIO_3 */ 0x0c82fe84, | |
436 | /* XFER_PIO_2 */ 0x0c82fea6, | |
437 | /* XFER_PIO_1 */ 0x0d02ff26, | |
438 | /* XFER_PIO_0 */ 0x0d42ff7f | |
439 | }; | |
440 | #endif | |
1da177e4 | 441 | |
1da177e4 | 442 | #define HPT366_DEBUG_DRIVE_INFO 0 |
7b73ee05 SS |
443 | #define HPT371_ALLOW_ATA133_6 1 |
444 | #define HPT302_ALLOW_ATA133_6 1 | |
445 | #define HPT372_ALLOW_ATA133_6 1 | |
e139b0b0 | 446 | #define HPT370_ALLOW_ATA100_5 0 |
1da177e4 LT |
447 | #define HPT366_ALLOW_ATA66_4 1 |
448 | #define HPT366_ALLOW_ATA66_3 1 | |
449 | #define HPT366_MAX_DEVS 8 | |
450 | ||
7b73ee05 SS |
451 | /* Supported ATA clock frequencies */ |
452 | enum ata_clock { | |
453 | ATA_CLOCK_25MHZ, | |
454 | ATA_CLOCK_33MHZ, | |
455 | ATA_CLOCK_40MHZ, | |
456 | ATA_CLOCK_50MHZ, | |
457 | ATA_CLOCK_66MHZ, | |
458 | NUM_ATA_CLOCKS | |
459 | }; | |
1da177e4 | 460 | |
866664d7 SS |
461 | struct hpt_timings { |
462 | u32 pio_mask; | |
463 | u32 dma_mask; | |
464 | u32 ultra_mask; | |
465 | u32 *clock_table[NUM_ATA_CLOCKS]; | |
466 | }; | |
467 | ||
b39b01ff | 468 | /* |
7b73ee05 | 469 | * Hold all the HighPoint chip information in one place. |
b39b01ff | 470 | */ |
1da177e4 | 471 | |
7b73ee05 | 472 | struct hpt_info { |
fbf47840 | 473 | char *chip_name; /* Chip name */ |
7b73ee05 | 474 | u8 chip_type; /* Chip type */ |
fbf47840 | 475 | u8 udma_mask; /* Allowed UltraDMA modes mask. */ |
7b73ee05 SS |
476 | u8 dpll_clk; /* DPLL clock in MHz */ |
477 | u8 pci_clk; /* PCI clock in MHz */ | |
866664d7 SS |
478 | struct hpt_timings *timings; /* Chipset timing data */ |
479 | u8 clock; /* ATA clock selected */ | |
b39b01ff AC |
480 | }; |
481 | ||
7b73ee05 SS |
482 | /* Supported HighPoint chips */ |
483 | enum { | |
484 | HPT36x, | |
485 | HPT370, | |
486 | HPT370A, | |
487 | HPT374, | |
488 | HPT372, | |
489 | HPT372A, | |
490 | HPT302, | |
491 | HPT371, | |
492 | HPT372N, | |
493 | HPT302N, | |
494 | HPT371N | |
495 | }; | |
b39b01ff | 496 | |
866664d7 SS |
497 | static struct hpt_timings hpt36x_timings = { |
498 | .pio_mask = 0xc1f8ffff, | |
499 | .dma_mask = 0x303800ff, | |
500 | .ultra_mask = 0x30070000, | |
501 | .clock_table = { | |
502 | [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x, | |
503 | [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x, | |
504 | [ATA_CLOCK_40MHZ] = forty_base_hpt36x, | |
505 | [ATA_CLOCK_50MHZ] = NULL, | |
506 | [ATA_CLOCK_66MHZ] = NULL | |
507 | } | |
7b73ee05 | 508 | }; |
e139b0b0 | 509 | |
866664d7 SS |
510 | static struct hpt_timings hpt37x_timings = { |
511 | .pio_mask = 0xcfc3ffff, | |
512 | .dma_mask = 0x31c001ff, | |
513 | .ultra_mask = 0x303c0000, | |
514 | .clock_table = { | |
515 | [ATA_CLOCK_25MHZ] = NULL, | |
516 | [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x, | |
517 | [ATA_CLOCK_40MHZ] = NULL, | |
518 | [ATA_CLOCK_50MHZ] = fifty_base_hpt37x, | |
519 | [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x | |
520 | } | |
7b73ee05 | 521 | }; |
1da177e4 | 522 | |
282037f1 | 523 | static const struct hpt_info hpt36x __devinitdata = { |
fbf47840 | 524 | .chip_name = "HPT36x", |
7b73ee05 | 525 | .chip_type = HPT36x, |
fbf47840 | 526 | .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2, |
7b73ee05 | 527 | .dpll_clk = 0, /* no DPLL */ |
866664d7 | 528 | .timings = &hpt36x_timings |
7b73ee05 SS |
529 | }; |
530 | ||
282037f1 | 531 | static const struct hpt_info hpt370 __devinitdata = { |
fbf47840 | 532 | .chip_name = "HPT370", |
7b73ee05 | 533 | .chip_type = HPT370, |
fbf47840 | 534 | .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, |
7b73ee05 | 535 | .dpll_clk = 48, |
866664d7 | 536 | .timings = &hpt37x_timings |
7b73ee05 SS |
537 | }; |
538 | ||
282037f1 | 539 | static const struct hpt_info hpt370a __devinitdata = { |
fbf47840 | 540 | .chip_name = "HPT370A", |
7b73ee05 | 541 | .chip_type = HPT370A, |
fbf47840 | 542 | .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4, |
7b73ee05 | 543 | .dpll_clk = 48, |
866664d7 | 544 | .timings = &hpt37x_timings |
7b73ee05 SS |
545 | }; |
546 | ||
282037f1 | 547 | static const struct hpt_info hpt374 __devinitdata = { |
fbf47840 | 548 | .chip_name = "HPT374", |
7b73ee05 | 549 | .chip_type = HPT374, |
fbf47840 | 550 | .udma_mask = ATA_UDMA5, |
7b73ee05 | 551 | .dpll_clk = 48, |
866664d7 | 552 | .timings = &hpt37x_timings |
7b73ee05 SS |
553 | }; |
554 | ||
282037f1 | 555 | static const struct hpt_info hpt372 __devinitdata = { |
fbf47840 | 556 | .chip_name = "HPT372", |
7b73ee05 | 557 | .chip_type = HPT372, |
fbf47840 | 558 | .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 559 | .dpll_clk = 55, |
866664d7 | 560 | .timings = &hpt37x_timings |
7b73ee05 SS |
561 | }; |
562 | ||
282037f1 | 563 | static const struct hpt_info hpt372a __devinitdata = { |
fbf47840 | 564 | .chip_name = "HPT372A", |
7b73ee05 | 565 | .chip_type = HPT372A, |
fbf47840 | 566 | .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 567 | .dpll_clk = 66, |
866664d7 | 568 | .timings = &hpt37x_timings |
7b73ee05 SS |
569 | }; |
570 | ||
282037f1 | 571 | static const struct hpt_info hpt302 __devinitdata = { |
fbf47840 | 572 | .chip_name = "HPT302", |
7b73ee05 | 573 | .chip_type = HPT302, |
fbf47840 | 574 | .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 575 | .dpll_clk = 66, |
866664d7 | 576 | .timings = &hpt37x_timings |
7b73ee05 SS |
577 | }; |
578 | ||
282037f1 | 579 | static const struct hpt_info hpt371 __devinitdata = { |
fbf47840 | 580 | .chip_name = "HPT371", |
7b73ee05 | 581 | .chip_type = HPT371, |
fbf47840 | 582 | .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 583 | .dpll_clk = 66, |
866664d7 | 584 | .timings = &hpt37x_timings |
7b73ee05 SS |
585 | }; |
586 | ||
282037f1 | 587 | static const struct hpt_info hpt372n __devinitdata = { |
fbf47840 | 588 | .chip_name = "HPT372N", |
7b73ee05 | 589 | .chip_type = HPT372N, |
fbf47840 | 590 | .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 591 | .dpll_clk = 77, |
866664d7 | 592 | .timings = &hpt37x_timings |
7b73ee05 SS |
593 | }; |
594 | ||
282037f1 | 595 | static const struct hpt_info hpt302n __devinitdata = { |
fbf47840 | 596 | .chip_name = "HPT302N", |
7b73ee05 | 597 | .chip_type = HPT302N, |
fbf47840 | 598 | .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 599 | .dpll_clk = 77, |
866664d7 | 600 | .timings = &hpt37x_timings |
7b73ee05 SS |
601 | }; |
602 | ||
282037f1 | 603 | static const struct hpt_info hpt371n __devinitdata = { |
fbf47840 | 604 | .chip_name = "HPT371N", |
7b73ee05 | 605 | .chip_type = HPT371N, |
fbf47840 | 606 | .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5, |
7b73ee05 | 607 | .dpll_clk = 77, |
866664d7 | 608 | .timings = &hpt37x_timings |
7b73ee05 | 609 | }; |
1da177e4 | 610 | |
e139b0b0 SS |
611 | static int check_in_drive_list(ide_drive_t *drive, const char **list) |
612 | { | |
613 | struct hd_driveid *id = drive->id; | |
614 | ||
615 | while (*list) | |
616 | if (!strcmp(*list++,id->model)) | |
617 | return 1; | |
618 | return 0; | |
619 | } | |
1da177e4 | 620 | |
1da177e4 | 621 | /* |
2808b0a9 SS |
622 | * The Marvell bridge chips used on the HighPoint SATA cards do not seem |
623 | * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... | |
1da177e4 | 624 | */ |
2d5eaa6d BZ |
625 | |
626 | static u8 hpt3xx_udma_filter(ide_drive_t *drive) | |
1da177e4 | 627 | { |
2808b0a9 SS |
628 | ide_hwif_t *hwif = HWIF(drive); |
629 | struct hpt_info *info = pci_get_drvdata(hwif->pci_dev); | |
630 | u8 mask = hwif->ultra_mask; | |
1da177e4 | 631 | |
2648e5d9 | 632 | switch (info->chip_type) { |
2648e5d9 SS |
633 | case HPT36x: |
634 | if (!HPT366_ALLOW_ATA66_4 || | |
635 | check_in_drive_list(drive, bad_ata66_4)) | |
2808b0a9 | 636 | mask = ATA_UDMA3; |
7b73ee05 | 637 | |
2648e5d9 SS |
638 | if (!HPT366_ALLOW_ATA66_3 || |
639 | check_in_drive_list(drive, bad_ata66_3)) | |
2808b0a9 | 640 | mask = ATA_UDMA2; |
2648e5d9 | 641 | break; |
2808b0a9 SS |
642 | case HPT370: |
643 | if (!HPT370_ALLOW_ATA100_5 || | |
644 | check_in_drive_list(drive, bad_ata100_5)) | |
645 | mask = ATA_UDMA4; | |
646 | break; | |
647 | case HPT370A: | |
648 | if (!HPT370_ALLOW_ATA100_5 || | |
649 | check_in_drive_list(drive, bad_ata100_5)) | |
650 | return ATA_UDMA4; | |
651 | case HPT372 : | |
652 | case HPT372A: | |
653 | case HPT372N: | |
654 | case HPT374 : | |
655 | if (ide_dev_is_sata(drive->id)) | |
656 | mask &= ~0x0e; | |
657 | /* Fall thru */ | |
2648e5d9 | 658 | default: |
2808b0a9 | 659 | return mask; |
1da177e4 | 660 | } |
2648e5d9 SS |
661 | |
662 | return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask; | |
1da177e4 LT |
663 | } |
664 | ||
b4e44369 SS |
665 | static u8 hpt3xx_mdma_filter(ide_drive_t *drive) |
666 | { | |
667 | ide_hwif_t *hwif = HWIF(drive); | |
668 | struct hpt_info *info = pci_get_drvdata(hwif->pci_dev); | |
669 | ||
670 | switch (info->chip_type) { | |
671 | case HPT372 : | |
672 | case HPT372A: | |
673 | case HPT372N: | |
674 | case HPT374 : | |
675 | if (ide_dev_is_sata(drive->id)) | |
676 | return 0x00; | |
677 | /* Fall thru */ | |
678 | default: | |
679 | return 0x07; | |
680 | } | |
681 | } | |
682 | ||
7b73ee05 | 683 | static u32 get_speed_setting(u8 speed, struct hpt_info *info) |
1da177e4 | 684 | { |
471a0bda SS |
685 | int i; |
686 | ||
687 | /* | |
688 | * Lookup the transfer mode table to get the index into | |
689 | * the timing table. | |
690 | * | |
691 | * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used. | |
692 | */ | |
693 | for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++) | |
694 | if (xfer_speeds[i] == speed) | |
695 | break; | |
866664d7 SS |
696 | |
697 | return info->timings->clock_table[info->clock][i]; | |
1da177e4 LT |
698 | } |
699 | ||
866664d7 | 700 | static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 701 | { |
866664d7 | 702 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
7b73ee05 | 703 | struct hpt_info *info = pci_get_drvdata(dev); |
866664d7 SS |
704 | struct hpt_timings *t = info->timings; |
705 | u8 itr_addr = 0x40 + (drive->dn * 4); | |
26ccb802 | 706 | u32 old_itr = 0; |
ceb1b2c5 | 707 | u32 new_itr = get_speed_setting(speed, info); |
866664d7 SS |
708 | u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask : |
709 | (speed < XFER_UDMA_0 ? t->dma_mask : | |
710 | t->ultra_mask); | |
b39b01ff | 711 | |
ceb1b2c5 SS |
712 | pci_read_config_dword(dev, itr_addr, &old_itr); |
713 | new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask); | |
1da177e4 | 714 | /* |
abc4ad4c SS |
715 | * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well) |
716 | * to avoid problems handling I/O errors later | |
1da177e4 | 717 | */ |
abc4ad4c | 718 | new_itr &= ~0xc0000000; |
1da177e4 | 719 | |
abc4ad4c | 720 | pci_write_config_dword(dev, itr_addr, new_itr); |
1da177e4 LT |
721 | } |
722 | ||
26bcb879 | 723 | static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 724 | { |
866664d7 | 725 | hpt3xx_set_mode(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
726 | } |
727 | ||
f01393e4 | 728 | static void hpt3xx_quirkproc(ide_drive_t *drive) |
1da177e4 | 729 | { |
e139b0b0 SS |
730 | struct hd_driveid *id = drive->id; |
731 | const char **list = quirk_drives; | |
732 | ||
733 | while (*list) | |
f01393e4 BZ |
734 | if (strstr(id->model, *list++)) { |
735 | drive->quirk_list = 1; | |
736 | return; | |
737 | } | |
738 | ||
739 | drive->quirk_list = 0; | |
1da177e4 LT |
740 | } |
741 | ||
26ccb802 | 742 | static void hpt3xx_maskproc(ide_drive_t *drive, int mask) |
1da177e4 | 743 | { |
abc4ad4c SS |
744 | ide_hwif_t *hwif = HWIF(drive); |
745 | struct pci_dev *dev = hwif->pci_dev; | |
7b73ee05 | 746 | struct hpt_info *info = pci_get_drvdata(dev); |
1da177e4 LT |
747 | |
748 | if (drive->quirk_list) { | |
7b73ee05 | 749 | if (info->chip_type >= HPT370) { |
abc4ad4c SS |
750 | u8 scr1 = 0; |
751 | ||
752 | pci_read_config_byte(dev, 0x5a, &scr1); | |
753 | if (((scr1 & 0x10) >> 4) != mask) { | |
754 | if (mask) | |
755 | scr1 |= 0x10; | |
756 | else | |
757 | scr1 &= ~0x10; | |
758 | pci_write_config_byte(dev, 0x5a, scr1); | |
759 | } | |
1da177e4 | 760 | } else { |
abc4ad4c | 761 | if (mask) |
b39b01ff | 762 | disable_irq(hwif->irq); |
abc4ad4c SS |
763 | else |
764 | enable_irq (hwif->irq); | |
1da177e4 | 765 | } |
abc4ad4c | 766 | } else |
31e8a465 BZ |
767 | outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2), |
768 | IDE_CONTROL_REG); | |
1da177e4 LT |
769 | } |
770 | ||
1da177e4 | 771 | /* |
abc4ad4c | 772 | * This is specific to the HPT366 UDMA chipset |
1da177e4 LT |
773 | * by HighPoint|Triones Technologies, Inc. |
774 | */ | |
841d2a9b | 775 | static void hpt366_dma_lost_irq(ide_drive_t *drive) |
1da177e4 | 776 | { |
abc4ad4c SS |
777 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
778 | u8 mcr1 = 0, mcr3 = 0, scr1 = 0; | |
779 | ||
780 | pci_read_config_byte(dev, 0x50, &mcr1); | |
781 | pci_read_config_byte(dev, 0x52, &mcr3); | |
782 | pci_read_config_byte(dev, 0x5a, &scr1); | |
783 | printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n", | |
784 | drive->name, __FUNCTION__, mcr1, mcr3, scr1); | |
785 | if (scr1 & 0x10) | |
786 | pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); | |
841d2a9b | 787 | ide_dma_lost_irq(drive); |
1da177e4 LT |
788 | } |
789 | ||
4bf63de2 | 790 | static void hpt370_clear_engine(ide_drive_t *drive) |
1da177e4 | 791 | { |
abc4ad4c SS |
792 | ide_hwif_t *hwif = HWIF(drive); |
793 | ||
794 | pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37); | |
1da177e4 LT |
795 | udelay(10); |
796 | } | |
797 | ||
4bf63de2 SS |
798 | static void hpt370_irq_timeout(ide_drive_t *drive) |
799 | { | |
800 | ide_hwif_t *hwif = HWIF(drive); | |
801 | u16 bfifo = 0; | |
802 | u8 dma_cmd; | |
803 | ||
804 | pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo); | |
805 | printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff); | |
806 | ||
807 | /* get DMA command mode */ | |
31e8a465 | 808 | dma_cmd = inb(hwif->dma_command); |
4bf63de2 | 809 | /* stop DMA */ |
31e8a465 | 810 | outb(dma_cmd & ~0x1, hwif->dma_command); |
4bf63de2 SS |
811 | hpt370_clear_engine(drive); |
812 | } | |
813 | ||
1da177e4 LT |
814 | static void hpt370_ide_dma_start(ide_drive_t *drive) |
815 | { | |
816 | #ifdef HPT_RESET_STATE_ENGINE | |
817 | hpt370_clear_engine(drive); | |
818 | #endif | |
819 | ide_dma_start(drive); | |
820 | } | |
821 | ||
4bf63de2 | 822 | static int hpt370_ide_dma_end(ide_drive_t *drive) |
1da177e4 LT |
823 | { |
824 | ide_hwif_t *hwif = HWIF(drive); | |
31e8a465 | 825 | u8 dma_stat = inb(hwif->dma_status); |
1da177e4 LT |
826 | |
827 | if (dma_stat & 0x01) { | |
828 | /* wait a little */ | |
829 | udelay(20); | |
31e8a465 | 830 | dma_stat = inb(hwif->dma_status); |
4bf63de2 SS |
831 | if (dma_stat & 0x01) |
832 | hpt370_irq_timeout(drive); | |
1da177e4 | 833 | } |
1da177e4 LT |
834 | return __ide_dma_end(drive); |
835 | } | |
836 | ||
c283f5db | 837 | static void hpt370_dma_timeout(ide_drive_t *drive) |
1da177e4 | 838 | { |
4bf63de2 | 839 | hpt370_irq_timeout(drive); |
c283f5db | 840 | ide_dma_timeout(drive); |
1da177e4 LT |
841 | } |
842 | ||
1da177e4 LT |
843 | /* returns 1 if DMA IRQ issued, 0 otherwise */ |
844 | static int hpt374_ide_dma_test_irq(ide_drive_t *drive) | |
845 | { | |
846 | ide_hwif_t *hwif = HWIF(drive); | |
847 | u16 bfifo = 0; | |
abc4ad4c | 848 | u8 dma_stat; |
1da177e4 | 849 | |
abc4ad4c | 850 | pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo); |
1da177e4 LT |
851 | if (bfifo & 0x1FF) { |
852 | // printk("%s: %d bytes in FIFO\n", drive->name, bfifo); | |
853 | return 0; | |
854 | } | |
855 | ||
0ecdca26 | 856 | dma_stat = inb(hwif->dma_status); |
1da177e4 | 857 | /* return 1 if INTR asserted */ |
abc4ad4c | 858 | if (dma_stat & 4) |
1da177e4 LT |
859 | return 1; |
860 | ||
861 | if (!drive->waiting_for_dma) | |
862 | printk(KERN_WARNING "%s: (%s) called while not waiting\n", | |
863 | drive->name, __FUNCTION__); | |
864 | return 0; | |
865 | } | |
866 | ||
abc4ad4c | 867 | static int hpt374_ide_dma_end(ide_drive_t *drive) |
1da177e4 | 868 | { |
1da177e4 | 869 | ide_hwif_t *hwif = HWIF(drive); |
abc4ad4c SS |
870 | struct pci_dev *dev = hwif->pci_dev; |
871 | u8 mcr = 0, mcr_addr = hwif->select_data; | |
872 | u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01; | |
873 | ||
874 | pci_read_config_byte(dev, 0x6a, &bwsr); | |
875 | pci_read_config_byte(dev, mcr_addr, &mcr); | |
876 | if (bwsr & mask) | |
877 | pci_write_config_byte(dev, mcr_addr, mcr | 0x30); | |
1da177e4 LT |
878 | return __ide_dma_end(drive); |
879 | } | |
880 | ||
881 | /** | |
836c0063 SS |
882 | * hpt3xxn_set_clock - perform clock switching dance |
883 | * @hwif: hwif to switch | |
884 | * @mode: clocking mode (0x21 for write, 0x23 otherwise) | |
1da177e4 | 885 | * |
836c0063 | 886 | * Switch the DPLL clock on the HPT3xxN devices. This is a right mess. |
1da177e4 | 887 | */ |
836c0063 SS |
888 | |
889 | static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode) | |
1da177e4 | 890 | { |
1c029fd6 BZ |
891 | unsigned long base = hwif->extra_base; |
892 | u8 scr2 = inb(base + 0x6b); | |
836c0063 SS |
893 | |
894 | if ((scr2 & 0x7f) == mode) | |
895 | return; | |
896 | ||
1da177e4 | 897 | /* Tristate the bus */ |
1c029fd6 BZ |
898 | outb(0x80, base + 0x63); |
899 | outb(0x80, base + 0x67); | |
836c0063 | 900 | |
1da177e4 | 901 | /* Switch clock and reset channels */ |
1c029fd6 BZ |
902 | outb(mode, base + 0x6b); |
903 | outb(0xc0, base + 0x69); | |
836c0063 | 904 | |
7b73ee05 SS |
905 | /* |
906 | * Reset the state machines. | |
907 | * NOTE: avoid accidentally enabling the disabled channels. | |
908 | */ | |
1c029fd6 BZ |
909 | outb(inb(base + 0x60) | 0x32, base + 0x60); |
910 | outb(inb(base + 0x64) | 0x32, base + 0x64); | |
836c0063 | 911 | |
1da177e4 | 912 | /* Complete reset */ |
1c029fd6 | 913 | outb(0x00, base + 0x69); |
836c0063 | 914 | |
1da177e4 | 915 | /* Reconnect channels to bus */ |
1c029fd6 BZ |
916 | outb(0x00, base + 0x63); |
917 | outb(0x00, base + 0x67); | |
1da177e4 LT |
918 | } |
919 | ||
920 | /** | |
836c0063 | 921 | * hpt3xxn_rw_disk - prepare for I/O |
1da177e4 LT |
922 | * @drive: drive for command |
923 | * @rq: block request structure | |
924 | * | |
836c0063 | 925 | * This is called when a disk I/O is issued to HPT3xxN. |
1da177e4 LT |
926 | * We need it because of the clock switching. |
927 | */ | |
928 | ||
836c0063 | 929 | static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq) |
1da177e4 | 930 | { |
7b73ee05 | 931 | hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21); |
1da177e4 LT |
932 | } |
933 | ||
1da177e4 | 934 | /* |
33b18a60 | 935 | * Set/get power state for a drive. |
abc4ad4c | 936 | * NOTE: affects both drives on each channel. |
1da177e4 | 937 | * |
33b18a60 | 938 | * When we turn the power back on, we need to re-initialize things. |
1da177e4 LT |
939 | */ |
940 | #define TRISTATE_BIT 0x8000 | |
33b18a60 SS |
941 | |
942 | static int hpt3xx_busproc(ide_drive_t *drive, int state) | |
1da177e4 | 943 | { |
abc4ad4c | 944 | ide_hwif_t *hwif = HWIF(drive); |
1da177e4 | 945 | struct pci_dev *dev = hwif->pci_dev; |
abc4ad4c SS |
946 | u8 mcr_addr = hwif->select_data + 2; |
947 | u8 resetmask = hwif->channel ? 0x80 : 0x40; | |
948 | u8 bsr2 = 0; | |
949 | u16 mcr = 0; | |
1da177e4 LT |
950 | |
951 | hwif->bus_state = state; | |
952 | ||
33b18a60 | 953 | /* Grab the status. */ |
abc4ad4c SS |
954 | pci_read_config_word(dev, mcr_addr, &mcr); |
955 | pci_read_config_byte(dev, 0x59, &bsr2); | |
1da177e4 | 956 | |
33b18a60 SS |
957 | /* |
958 | * Set the state. We don't set it if we don't need to do so. | |
959 | * Make sure that the drive knows that it has failed if it's off. | |
960 | */ | |
1da177e4 LT |
961 | switch (state) { |
962 | case BUSSTATE_ON: | |
abc4ad4c | 963 | if (!(bsr2 & resetmask)) |
1da177e4 | 964 | return 0; |
33b18a60 SS |
965 | hwif->drives[0].failures = hwif->drives[1].failures = 0; |
966 | ||
abc4ad4c SS |
967 | pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask); |
968 | pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT); | |
33b18a60 | 969 | return 0; |
1da177e4 | 970 | case BUSSTATE_OFF: |
abc4ad4c | 971 | if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT)) |
1da177e4 | 972 | return 0; |
abc4ad4c | 973 | mcr &= ~TRISTATE_BIT; |
1da177e4 LT |
974 | break; |
975 | case BUSSTATE_TRISTATE: | |
abc4ad4c | 976 | if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT)) |
1da177e4 | 977 | return 0; |
abc4ad4c | 978 | mcr |= TRISTATE_BIT; |
1da177e4 | 979 | break; |
33b18a60 SS |
980 | default: |
981 | return -EINVAL; | |
1da177e4 | 982 | } |
1da177e4 | 983 | |
33b18a60 SS |
984 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; |
985 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | |
986 | ||
abc4ad4c SS |
987 | pci_write_config_word(dev, mcr_addr, mcr); |
988 | pci_write_config_byte(dev, 0x59, bsr2 | resetmask); | |
1da177e4 LT |
989 | return 0; |
990 | } | |
991 | ||
7b73ee05 SS |
992 | /** |
993 | * hpt37x_calibrate_dpll - calibrate the DPLL | |
994 | * @dev: PCI device | |
995 | * | |
996 | * Perform a calibration cycle on the DPLL. | |
997 | * Returns 1 if this succeeds | |
998 | */ | |
999 | static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high) | |
1da177e4 | 1000 | { |
7b73ee05 SS |
1001 | u32 dpll = (f_high << 16) | f_low | 0x100; |
1002 | u8 scr2; | |
1003 | int i; | |
b39b01ff | 1004 | |
7b73ee05 | 1005 | pci_write_config_dword(dev, 0x5c, dpll); |
b39b01ff | 1006 | |
7b73ee05 SS |
1007 | /* Wait for oscillator ready */ |
1008 | for(i = 0; i < 0x5000; ++i) { | |
1009 | udelay(50); | |
1010 | pci_read_config_byte(dev, 0x5b, &scr2); | |
1011 | if (scr2 & 0x80) | |
b39b01ff AC |
1012 | break; |
1013 | } | |
7b73ee05 SS |
1014 | /* See if it stays ready (we'll just bail out if it's not yet) */ |
1015 | for(i = 0; i < 0x1000; ++i) { | |
1016 | pci_read_config_byte(dev, 0x5b, &scr2); | |
1017 | /* DPLL destabilized? */ | |
1018 | if(!(scr2 & 0x80)) | |
1019 | return 0; | |
1020 | } | |
1021 | /* Turn off tuning, we have the DPLL set */ | |
1022 | pci_read_config_dword (dev, 0x5c, &dpll); | |
1023 | pci_write_config_dword(dev, 0x5c, (dpll & ~0x100)); | |
1024 | return 1; | |
b39b01ff AC |
1025 | } |
1026 | ||
7b73ee05 | 1027 | static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name) |
b39b01ff | 1028 | { |
7b73ee05 SS |
1029 | struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL); |
1030 | unsigned long io_base = pci_resource_start(dev, 4); | |
1031 | u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */ | |
72931368 | 1032 | u8 chip_type; |
7b73ee05 SS |
1033 | enum ata_clock clock; |
1034 | ||
1035 | if (info == NULL) { | |
1036 | printk(KERN_ERR "%s: out of memory!\n", name); | |
1037 | return -ENOMEM; | |
1038 | } | |
1039 | ||
1da177e4 | 1040 | /* |
7b73ee05 SS |
1041 | * Copy everything from a static "template" structure |
1042 | * to just allocated per-chip hpt_info structure. | |
1da177e4 | 1043 | */ |
72931368 SS |
1044 | memcpy(info, pci_get_drvdata(dev), sizeof(struct hpt_info)); |
1045 | chip_type = info->chip_type; | |
1da177e4 | 1046 | |
7b73ee05 SS |
1047 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); |
1048 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
1049 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
1050 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
26c068da | 1051 | |
1da177e4 | 1052 | /* |
7b73ee05 | 1053 | * First, try to estimate the PCI clock frequency... |
1da177e4 | 1054 | */ |
72931368 | 1055 | if (chip_type >= HPT370) { |
7b73ee05 SS |
1056 | u8 scr1 = 0; |
1057 | u16 f_cnt = 0; | |
1058 | u32 temp = 0; | |
1059 | ||
1060 | /* Interrupt force enable. */ | |
1061 | pci_read_config_byte(dev, 0x5a, &scr1); | |
1062 | if (scr1 & 0x10) | |
1063 | pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); | |
1064 | ||
1065 | /* | |
1066 | * HighPoint does this for HPT372A. | |
1067 | * NOTE: This register is only writeable via I/O space. | |
1068 | */ | |
72931368 | 1069 | if (chip_type == HPT372A) |
7b73ee05 SS |
1070 | outb(0x0e, io_base + 0x9c); |
1071 | ||
1072 | /* | |
1073 | * Default to PCI clock. Make sure MA15/16 are set to output | |
1074 | * to prevent drives having problems with 40-pin cables. | |
1075 | */ | |
1076 | pci_write_config_byte(dev, 0x5b, 0x23); | |
836c0063 | 1077 | |
7b73ee05 SS |
1078 | /* |
1079 | * We'll have to read f_CNT value in order to determine | |
1080 | * the PCI clock frequency according to the following ratio: | |
1081 | * | |
1082 | * f_CNT = Fpci * 192 / Fdpll | |
1083 | * | |
1084 | * First try reading the register in which the HighPoint BIOS | |
1085 | * saves f_CNT value before reprogramming the DPLL from its | |
1086 | * default setting (which differs for the various chips). | |
7b73ee05 | 1087 | * |
72931368 SS |
1088 | * NOTE: This register is only accessible via I/O space; |
1089 | * HPT374 BIOS only saves it for the function 0, so we have to | |
1090 | * always read it from there -- no need to check the result of | |
1091 | * pci_get_slot() for the function 0 as the whole device has | |
1092 | * been already "pinned" (via function 1) in init_setup_hpt374() | |
1093 | */ | |
1094 | if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { | |
1095 | struct pci_dev *dev1 = pci_get_slot(dev->bus, | |
1096 | dev->devfn - 1); | |
1097 | unsigned long io_base = pci_resource_start(dev1, 4); | |
1098 | ||
1099 | temp = inl(io_base + 0x90); | |
1100 | pci_dev_put(dev1); | |
1101 | } else | |
1102 | temp = inl(io_base + 0x90); | |
1103 | ||
1104 | /* | |
1105 | * In case the signature check fails, we'll have to | |
1106 | * resort to reading the f_CNT register itself in hopes | |
1107 | * that nobody has touched the DPLL yet... | |
7b73ee05 | 1108 | */ |
7b73ee05 SS |
1109 | if ((temp & 0xFFFFF000) != 0xABCDE000) { |
1110 | int i; | |
1111 | ||
1112 | printk(KERN_WARNING "%s: no clock data saved by BIOS\n", | |
1113 | name); | |
1114 | ||
1115 | /* Calculate the average value of f_CNT. */ | |
1116 | for (temp = i = 0; i < 128; i++) { | |
1117 | pci_read_config_word(dev, 0x78, &f_cnt); | |
1118 | temp += f_cnt & 0x1ff; | |
1119 | mdelay(1); | |
1120 | } | |
1121 | f_cnt = temp / 128; | |
1122 | } else | |
1123 | f_cnt = temp & 0x1ff; | |
1124 | ||
1125 | dpll_clk = info->dpll_clk; | |
1126 | pci_clk = (f_cnt * dpll_clk) / 192; | |
1127 | ||
1128 | /* Clamp PCI clock to bands. */ | |
1129 | if (pci_clk < 40) | |
1130 | pci_clk = 33; | |
1131 | else if(pci_clk < 45) | |
1132 | pci_clk = 40; | |
1133 | else if(pci_clk < 55) | |
1134 | pci_clk = 50; | |
1da177e4 | 1135 | else |
7b73ee05 | 1136 | pci_clk = 66; |
836c0063 | 1137 | |
7b73ee05 SS |
1138 | printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, " |
1139 | "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk); | |
90778574 | 1140 | } else { |
7b73ee05 SS |
1141 | u32 itr1 = 0; |
1142 | ||
1143 | pci_read_config_dword(dev, 0x40, &itr1); | |
1144 | ||
1145 | /* Detect PCI clock by looking at cmd_high_time. */ | |
1146 | switch((itr1 >> 8) & 0x07) { | |
1147 | case 0x09: | |
1148 | pci_clk = 40; | |
6273d26a | 1149 | break; |
7b73ee05 SS |
1150 | case 0x05: |
1151 | pci_clk = 25; | |
6273d26a | 1152 | break; |
7b73ee05 SS |
1153 | case 0x07: |
1154 | default: | |
1155 | pci_clk = 33; | |
6273d26a | 1156 | break; |
1da177e4 LT |
1157 | } |
1158 | } | |
836c0063 | 1159 | |
7b73ee05 SS |
1160 | /* Let's assume we'll use PCI clock for the ATA clock... */ |
1161 | switch (pci_clk) { | |
1162 | case 25: | |
1163 | clock = ATA_CLOCK_25MHZ; | |
1164 | break; | |
1165 | case 33: | |
1166 | default: | |
1167 | clock = ATA_CLOCK_33MHZ; | |
1168 | break; | |
1169 | case 40: | |
1170 | clock = ATA_CLOCK_40MHZ; | |
1171 | break; | |
1172 | case 50: | |
1173 | clock = ATA_CLOCK_50MHZ; | |
1174 | break; | |
1175 | case 66: | |
1176 | clock = ATA_CLOCK_66MHZ; | |
1177 | break; | |
1178 | } | |
836c0063 | 1179 | |
1da177e4 | 1180 | /* |
7b73ee05 SS |
1181 | * Only try the DPLL if we don't have a table for the PCI clock that |
1182 | * we are running at for HPT370/A, always use it for anything newer... | |
b39b01ff | 1183 | * |
7b73ee05 SS |
1184 | * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI. |
1185 | * We also don't like using the DPLL because this causes glitches | |
1186 | * on PRST-/SRST- when the state engine gets reset... | |
1da177e4 | 1187 | */ |
866664d7 | 1188 | if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) { |
7b73ee05 SS |
1189 | u16 f_low, delta = pci_clk < 50 ? 2 : 4; |
1190 | int adjust; | |
1191 | ||
1192 | /* | |
1193 | * Select 66 MHz DPLL clock only if UltraATA/133 mode is | |
1194 | * supported/enabled, use 50 MHz DPLL clock otherwise... | |
1195 | */ | |
fbf47840 | 1196 | if (info->udma_mask == ATA_UDMA6) { |
7b73ee05 SS |
1197 | dpll_clk = 66; |
1198 | clock = ATA_CLOCK_66MHZ; | |
1199 | } else if (dpll_clk) { /* HPT36x chips don't have DPLL */ | |
1200 | dpll_clk = 50; | |
1201 | clock = ATA_CLOCK_50MHZ; | |
1202 | } | |
b39b01ff | 1203 | |
866664d7 | 1204 | if (info->timings->clock_table[clock] == NULL) { |
7b73ee05 SS |
1205 | printk(KERN_ERR "%s: unknown bus timing!\n", name); |
1206 | kfree(info); | |
1207 | return -EIO; | |
1da177e4 | 1208 | } |
1da177e4 | 1209 | |
7b73ee05 SS |
1210 | /* Select the DPLL clock. */ |
1211 | pci_write_config_byte(dev, 0x5b, 0x21); | |
1212 | ||
1213 | /* | |
1214 | * Adjust the DPLL based upon PCI clock, enable it, | |
1215 | * and wait for stabilization... | |
1216 | */ | |
1217 | f_low = (pci_clk * 48) / dpll_clk; | |
1218 | ||
1219 | for (adjust = 0; adjust < 8; adjust++) { | |
1220 | if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta)) | |
1221 | break; | |
1222 | ||
1223 | /* | |
1224 | * See if it'll settle at a fractionally different clock | |
1225 | */ | |
1226 | if (adjust & 1) | |
1227 | f_low -= adjust >> 1; | |
1228 | else | |
1229 | f_low += adjust >> 1; | |
1230 | } | |
1231 | if (adjust == 8) { | |
1232 | printk(KERN_ERR "%s: DPLL did not stabilize!\n", name); | |
1233 | kfree(info); | |
1234 | return -EIO; | |
1235 | } | |
1236 | ||
1237 | printk("%s: using %d MHz DPLL clock\n", name, dpll_clk); | |
1238 | } else { | |
1239 | /* Mark the fact that we're not using the DPLL. */ | |
1240 | dpll_clk = 0; | |
1241 | ||
1242 | printk("%s: using %d MHz PCI clock\n", name, pci_clk); | |
1243 | } | |
b39b01ff | 1244 | |
7b73ee05 SS |
1245 | /* Store the clock frequencies. */ |
1246 | info->dpll_clk = dpll_clk; | |
1247 | info->pci_clk = pci_clk; | |
866664d7 | 1248 | info->clock = clock; |
1da177e4 | 1249 | |
7b73ee05 SS |
1250 | /* Point to this chip's own instance of the hpt_info structure. */ |
1251 | pci_set_drvdata(dev, info); | |
b39b01ff | 1252 | |
72931368 | 1253 | if (chip_type >= HPT370) { |
7b73ee05 SS |
1254 | u8 mcr1, mcr4; |
1255 | ||
1256 | /* | |
1257 | * Reset the state engines. | |
1258 | * NOTE: Avoid accidentally enabling the disabled channels. | |
1259 | */ | |
1260 | pci_read_config_byte (dev, 0x50, &mcr1); | |
1261 | pci_read_config_byte (dev, 0x54, &mcr4); | |
1262 | pci_write_config_byte(dev, 0x50, (mcr1 | 0x32)); | |
1263 | pci_write_config_byte(dev, 0x54, (mcr4 | 0x32)); | |
1264 | udelay(100); | |
26ccb802 | 1265 | } |
1da177e4 | 1266 | |
7b73ee05 SS |
1267 | /* |
1268 | * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in | |
1269 | * the MISC. register to stretch the UltraDMA Tss timing. | |
1270 | * NOTE: This register is only writeable via I/O space. | |
1271 | */ | |
72931368 | 1272 | if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ) |
7b73ee05 SS |
1273 | |
1274 | outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c); | |
1275 | ||
1da177e4 LT |
1276 | return dev->irq; |
1277 | } | |
1278 | ||
1279 | static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) | |
1280 | { | |
2808b0a9 SS |
1281 | struct pci_dev *dev = hwif->pci_dev; |
1282 | struct hpt_info *info = pci_get_drvdata(dev); | |
1283 | int serialize = HPT_SERIALIZE_IO; | |
1284 | u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02; | |
1285 | u8 chip_type = info->chip_type; | |
1286 | u8 new_mcr, old_mcr = 0; | |
abc4ad4c SS |
1287 | |
1288 | /* Cache the channel's MISC. control registers' offset */ | |
2808b0a9 | 1289 | hwif->select_data = hwif->channel ? 0x54 : 0x50; |
abc4ad4c | 1290 | |
26bcb879 | 1291 | hwif->set_pio_mode = &hpt3xx_set_pio_mode; |
866664d7 | 1292 | hwif->set_dma_mode = &hpt3xx_set_mode; |
a488f34e | 1293 | |
2808b0a9 | 1294 | hwif->quirkproc = &hpt3xx_quirkproc; |
2808b0a9 SS |
1295 | hwif->maskproc = &hpt3xx_maskproc; |
1296 | hwif->busproc = &hpt3xx_busproc; | |
2648e5d9 | 1297 | |
2808b0a9 | 1298 | hwif->udma_filter = &hpt3xx_udma_filter; |
b4e44369 | 1299 | hwif->mdma_filter = &hpt3xx_mdma_filter; |
abc4ad4c | 1300 | |
836c0063 SS |
1301 | /* |
1302 | * HPT3xxN chips have some complications: | |
1303 | * | |
1304 | * - on 33 MHz PCI we must clock switch | |
1305 | * - on 66 MHz PCI we must NOT use the PCI clock | |
1306 | */ | |
7b73ee05 | 1307 | if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) { |
836c0063 SS |
1308 | /* |
1309 | * Clock is shared between the channels, | |
1310 | * so we'll have to serialize them... :-( | |
1311 | */ | |
1312 | serialize = 1; | |
1313 | hwif->rw_disk = &hpt3xxn_rw_disk; | |
1314 | } | |
1da177e4 | 1315 | |
26ccb802 SS |
1316 | /* Serialize access to this device if needed */ |
1317 | if (serialize && hwif->mate) | |
1318 | hwif->serialized = hwif->mate->serialized = 1; | |
1319 | ||
1320 | /* | |
1321 | * Disable the "fast interrupt" prediction. Don't hold off | |
1322 | * on interrupts. (== 0x01 despite what the docs say) | |
1323 | */ | |
1324 | pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr); | |
1325 | ||
7b73ee05 | 1326 | if (info->chip_type >= HPT374) |
26ccb802 | 1327 | new_mcr = old_mcr & ~0x07; |
7b73ee05 | 1328 | else if (info->chip_type >= HPT370) { |
26ccb802 SS |
1329 | new_mcr = old_mcr; |
1330 | new_mcr &= ~0x02; | |
1331 | ||
1332 | #ifdef HPT_DELAY_INTERRUPT | |
1333 | new_mcr &= ~0x01; | |
1334 | #else | |
1335 | new_mcr |= 0x01; | |
1336 | #endif | |
1337 | } else /* HPT366 and HPT368 */ | |
1338 | new_mcr = old_mcr & ~0x80; | |
1339 | ||
1340 | if (new_mcr != old_mcr) | |
1341 | pci_write_config_byte(dev, hwif->select_data + 1, new_mcr); | |
1342 | ||
a29ec3b2 | 1343 | if (hwif->dma_base == 0) |
26ccb802 | 1344 | return; |
26ccb802 | 1345 | |
1da177e4 LT |
1346 | /* |
1347 | * The HPT37x uses the CBLID pins as outputs for MA15/MA16 | |
abc4ad4c | 1348 | * address lines to access an external EEPROM. To read valid |
1da177e4 LT |
1349 | * cable detect state the pins must be enabled as inputs. |
1350 | */ | |
7b73ee05 | 1351 | if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { |
1da177e4 LT |
1352 | /* |
1353 | * HPT374 PCI function 1 | |
1354 | * - set bit 15 of reg 0x52 to enable TCBLID as input | |
1355 | * - set bit 15 of reg 0x56 to enable FCBLID as input | |
1356 | */ | |
abc4ad4c SS |
1357 | u8 mcr_addr = hwif->select_data + 2; |
1358 | u16 mcr; | |
1359 | ||
1360 | pci_read_config_word (dev, mcr_addr, &mcr); | |
1361 | pci_write_config_word(dev, mcr_addr, (mcr | 0x8000)); | |
1da177e4 | 1362 | /* now read cable id register */ |
abc4ad4c SS |
1363 | pci_read_config_byte (dev, 0x5a, &scr1); |
1364 | pci_write_config_word(dev, mcr_addr, mcr); | |
7b73ee05 | 1365 | } else if (chip_type >= HPT370) { |
1da177e4 LT |
1366 | /* |
1367 | * HPT370/372 and 374 pcifn 0 | |
abc4ad4c | 1368 | * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs |
1da177e4 | 1369 | */ |
abc4ad4c | 1370 | u8 scr2 = 0; |
1da177e4 | 1371 | |
abc4ad4c SS |
1372 | pci_read_config_byte (dev, 0x5b, &scr2); |
1373 | pci_write_config_byte(dev, 0x5b, (scr2 & ~1)); | |
1374 | /* now read cable id register */ | |
1375 | pci_read_config_byte (dev, 0x5a, &scr1); | |
1376 | pci_write_config_byte(dev, 0x5b, scr2); | |
1377 | } else | |
1378 | pci_read_config_byte (dev, 0x5a, &scr1); | |
1da177e4 | 1379 | |
49521f97 BZ |
1380 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) |
1381 | hwif->cbl = (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; | |
1da177e4 | 1382 | |
7b73ee05 | 1383 | if (chip_type >= HPT374) { |
26ccb802 SS |
1384 | hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq; |
1385 | hwif->ide_dma_end = &hpt374_ide_dma_end; | |
7b73ee05 | 1386 | } else if (chip_type >= HPT370) { |
26ccb802 SS |
1387 | hwif->dma_start = &hpt370_ide_dma_start; |
1388 | hwif->ide_dma_end = &hpt370_ide_dma_end; | |
c283f5db | 1389 | hwif->dma_timeout = &hpt370_dma_timeout; |
26ccb802 | 1390 | } else |
841d2a9b | 1391 | hwif->dma_lost_irq = &hpt366_dma_lost_irq; |
1da177e4 LT |
1392 | } |
1393 | ||
1394 | static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase) | |
1395 | { | |
26ccb802 | 1396 | struct pci_dev *dev = hwif->pci_dev; |
abc4ad4c SS |
1397 | u8 masterdma = 0, slavedma = 0; |
1398 | u8 dma_new = 0, dma_old = 0; | |
1da177e4 LT |
1399 | unsigned long flags; |
1400 | ||
31e8a465 | 1401 | dma_old = inb(dmabase + 2); |
1da177e4 LT |
1402 | |
1403 | local_irq_save(flags); | |
1404 | ||
1405 | dma_new = dma_old; | |
abc4ad4c SS |
1406 | pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma); |
1407 | pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma); | |
1da177e4 LT |
1408 | |
1409 | if (masterdma & 0x30) dma_new |= 0x20; | |
abc4ad4c | 1410 | if ( slavedma & 0x30) dma_new |= 0x40; |
1da177e4 | 1411 | if (dma_new != dma_old) |
31e8a465 | 1412 | outb(dma_new, dmabase + 2); |
1da177e4 LT |
1413 | |
1414 | local_irq_restore(flags); | |
1415 | ||
1416 | ide_setup_dma(hwif, dmabase, 8); | |
1417 | } | |
1418 | ||
fbf47840 | 1419 | static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2) |
1da177e4 | 1420 | { |
fbf47840 BZ |
1421 | if (dev2->irq != dev->irq) { |
1422 | /* FIXME: we need a core pci_set_interrupt() */ | |
1423 | dev2->irq = dev->irq; | |
1424 | printk(KERN_INFO "HPT374: PCI config space interrupt fixed\n"); | |
1da177e4 | 1425 | } |
1da177e4 LT |
1426 | } |
1427 | ||
fbf47840 | 1428 | static void __devinit hpt371_init(struct pci_dev *dev) |
836c0063 | 1429 | { |
44c10138 | 1430 | u8 mcr1 = 0; |
90778574 | 1431 | |
836c0063 SS |
1432 | /* |
1433 | * HPT371 chips physically have only one channel, the secondary one, | |
1434 | * but the primary channel registers do exist! Go figure... | |
1435 | * So, we manually disable the non-existing channel here | |
1436 | * (if the BIOS hasn't done this already). | |
1437 | */ | |
1438 | pci_read_config_byte(dev, 0x50, &mcr1); | |
1439 | if (mcr1 & 0x04) | |
90778574 | 1440 | pci_write_config_byte(dev, 0x50, mcr1 & ~0x04); |
90778574 SS |
1441 | } |
1442 | ||
fbf47840 | 1443 | static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2) |
90778574 | 1444 | { |
fbf47840 | 1445 | u8 mcr1 = 0, pin1 = 0, pin2 = 0; |
7b73ee05 | 1446 | |
fbf47840 BZ |
1447 | /* |
1448 | * Now we'll have to force both channels enabled if | |
1449 | * at least one of them has been enabled by BIOS... | |
1450 | */ | |
1451 | pci_read_config_byte(dev, 0x50, &mcr1); | |
1452 | if (mcr1 & 0x30) | |
1453 | pci_write_config_byte(dev, 0x50, mcr1 | 0x30); | |
836c0063 | 1454 | |
fbf47840 BZ |
1455 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1); |
1456 | pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2); | |
1da177e4 | 1457 | |
fbf47840 BZ |
1458 | if (pin1 != pin2 && dev->irq == dev2->irq) { |
1459 | printk(KERN_INFO "HPT36x: onboard version of chipset, " | |
1460 | "pin1=%d pin2=%d\n", pin1, pin2); | |
1461 | return 1; | |
2648e5d9 SS |
1462 | } |
1463 | ||
fbf47840 | 1464 | return 0; |
1da177e4 LT |
1465 | } |
1466 | ||
4db90a14 BZ |
1467 | #define IDE_HFLAGS_HPT3XX \ |
1468 | (IDE_HFLAG_NO_ATAPI_DMA | \ | |
1469 | IDE_HFLAG_ABUSE_SET_DMA_MODE | \ | |
1470 | IDE_HFLAG_OFF_BOARD) | |
1471 | ||
85620436 | 1472 | static const struct ide_port_info hpt366_chipsets[] __devinitdata = { |
1da177e4 | 1473 | { /* 0 */ |
fbf47840 | 1474 | .name = "HPT36x", |
1da177e4 LT |
1475 | .init_chipset = init_chipset_hpt366, |
1476 | .init_hwif = init_hwif_hpt366, | |
1477 | .init_dma = init_dma_hpt366, | |
fbf47840 BZ |
1478 | /* |
1479 | * HPT36x chips have one channel per function and have | |
1480 | * both channel enable bits located differently and visible | |
1481 | * to both functions -- really stupid design decision... :-( | |
1482 | * Bit 4 is for the primary channel, bit 5 for the secondary. | |
1483 | */ | |
1484 | .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}}, | |
4099d143 | 1485 | .extra = 240, |
4db90a14 | 1486 | .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE, |
4099d143 | 1487 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1488 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1489 | },{ /* 1 */ |
1490 | .name = "HPT372A", | |
1da177e4 LT |
1491 | .init_chipset = init_chipset_hpt366, |
1492 | .init_hwif = init_hwif_hpt366, | |
1493 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1494 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
4099d143 | 1495 | .extra = 240, |
4db90a14 | 1496 | .host_flags = IDE_HFLAGS_HPT3XX, |
4099d143 | 1497 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1498 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1499 | },{ /* 2 */ |
1500 | .name = "HPT302", | |
1da177e4 LT |
1501 | .init_chipset = init_chipset_hpt366, |
1502 | .init_hwif = init_hwif_hpt366, | |
1503 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1504 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
4099d143 | 1505 | .extra = 240, |
4db90a14 | 1506 | .host_flags = IDE_HFLAGS_HPT3XX, |
4099d143 | 1507 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1508 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1509 | },{ /* 3 */ |
1510 | .name = "HPT371", | |
1da177e4 LT |
1511 | .init_chipset = init_chipset_hpt366, |
1512 | .init_hwif = init_hwif_hpt366, | |
1513 | .init_dma = init_dma_hpt366, | |
836c0063 | 1514 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
4099d143 | 1515 | .extra = 240, |
4db90a14 | 1516 | .host_flags = IDE_HFLAGS_HPT3XX, |
4099d143 | 1517 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1518 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1519 | },{ /* 4 */ |
1520 | .name = "HPT374", | |
1da177e4 LT |
1521 | .init_chipset = init_chipset_hpt366, |
1522 | .init_hwif = init_hwif_hpt366, | |
1523 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1524 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
2808b0a9 | 1525 | .udma_mask = ATA_UDMA5, |
4099d143 | 1526 | .extra = 240, |
4db90a14 | 1527 | .host_flags = IDE_HFLAGS_HPT3XX, |
4099d143 | 1528 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1529 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1530 | },{ /* 5 */ |
1531 | .name = "HPT372N", | |
1da177e4 LT |
1532 | .init_chipset = init_chipset_hpt366, |
1533 | .init_hwif = init_hwif_hpt366, | |
1534 | .init_dma = init_dma_hpt366, | |
7b73ee05 | 1535 | .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, |
4099d143 | 1536 | .extra = 240, |
4db90a14 | 1537 | .host_flags = IDE_HFLAGS_HPT3XX, |
4099d143 | 1538 | .pio_mask = ATA_PIO4, |
5f8b6c34 | 1539 | .mwdma_mask = ATA_MWDMA2, |
1da177e4 LT |
1540 | } |
1541 | }; | |
1542 | ||
1543 | /** | |
1544 | * hpt366_init_one - called when an HPT366 is found | |
1545 | * @dev: the hpt366 device | |
1546 | * @id: the matching pci id | |
1547 | * | |
1548 | * Called when the PCI registration layer (or the IDE initialization) | |
1549 | * finds a device matching our IDE device tables. | |
1550 | */ | |
1da177e4 LT |
1551 | static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
1552 | { | |
282037f1 | 1553 | const struct hpt_info *info = NULL; |
fbf47840 | 1554 | struct pci_dev *dev2 = NULL; |
039788e1 | 1555 | struct ide_port_info d; |
fbf47840 BZ |
1556 | u8 idx = id->driver_data; |
1557 | u8 rev = dev->revision; | |
1558 | ||
1559 | if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1)) | |
1560 | return -ENODEV; | |
1561 | ||
1562 | switch (idx) { | |
1563 | case 0: | |
1564 | if (rev < 3) | |
1565 | info = &hpt36x; | |
1566 | else { | |
282037f1 | 1567 | static const struct hpt_info *hpt37x_info[] = |
fbf47840 BZ |
1568 | { &hpt370, &hpt370a, &hpt372, &hpt372n }; |
1569 | ||
1570 | info = hpt37x_info[min_t(u8, rev, 6) - 3]; | |
1571 | idx++; | |
1572 | } | |
1573 | break; | |
1574 | case 1: | |
1575 | info = (rev > 1) ? &hpt372n : &hpt372a; | |
1576 | break; | |
1577 | case 2: | |
1578 | info = (rev > 1) ? &hpt302n : &hpt302; | |
1579 | break; | |
1580 | case 3: | |
1581 | hpt371_init(dev); | |
1582 | info = (rev > 1) ? &hpt371n : &hpt371; | |
1583 | break; | |
1584 | case 4: | |
1585 | info = &hpt374; | |
1586 | break; | |
1587 | case 5: | |
1588 | info = &hpt372n; | |
1589 | break; | |
1590 | } | |
1591 | ||
1592 | d = hpt366_chipsets[idx]; | |
1593 | ||
1594 | d.name = info->chip_name; | |
1595 | d.udma_mask = info->udma_mask; | |
1596 | ||
282037f1 | 1597 | pci_set_drvdata(dev, (void *)info); |
fbf47840 BZ |
1598 | |
1599 | if (info == &hpt36x || info == &hpt374) | |
1600 | dev2 = pci_get_slot(dev->bus, dev->devfn + 1); | |
1601 | ||
1602 | if (dev2) { | |
1603 | int ret; | |
1604 | ||
282037f1 | 1605 | pci_set_drvdata(dev2, (void *)info); |
fbf47840 BZ |
1606 | |
1607 | if (info == &hpt374) | |
1608 | hpt374_init(dev, dev2); | |
1609 | else { | |
1610 | if (hpt36x_init(dev, dev2)) | |
1611 | d.host_flags |= IDE_HFLAG_BOOTABLE; | |
1612 | } | |
1613 | ||
1614 | ret = ide_setup_pci_devices(dev, dev2, &d); | |
1615 | if (ret < 0) | |
1616 | pci_dev_put(dev2); | |
1617 | return ret; | |
1618 | } | |
1da177e4 | 1619 | |
fbf47840 | 1620 | return ide_setup_pci_device(dev, &d); |
1da177e4 LT |
1621 | } |
1622 | ||
9cbcc5e3 BZ |
1623 | static const struct pci_device_id hpt366_pci_tbl[] = { |
1624 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 }, | |
1625 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 }, | |
1626 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 }, | |
1627 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 }, | |
1628 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 }, | |
1629 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 }, | |
1da177e4 LT |
1630 | { 0, }, |
1631 | }; | |
1632 | MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl); | |
1633 | ||
1634 | static struct pci_driver driver = { | |
1635 | .name = "HPT366_IDE", | |
1636 | .id_table = hpt366_pci_tbl, | |
1637 | .probe = hpt366_init_one, | |
1638 | }; | |
1639 | ||
82ab1eec | 1640 | static int __init hpt366_ide_init(void) |
1da177e4 LT |
1641 | { |
1642 | return ide_pci_register_driver(&driver); | |
1643 | } | |
1644 | ||
1645 | module_init(hpt366_ide_init); | |
1646 | ||
1647 | MODULE_AUTHOR("Andre Hedrick"); | |
1648 | MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE"); | |
1649 | MODULE_LICENSE("GPL"); |