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f5b2d8b4 JK |
1 | /* |
2 | * linux/drivers/ide/pci/cs5535.c | |
3 | * | |
4 | * Copyright (C) 2004-2005 Advanced Micro Devices, Inc. | |
bc0b0b5c | 5 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
f5b2d8b4 JK |
6 | * |
7 | * History: | |
8 | * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com> | |
9 | * - Reworked tuneproc, set_drive, misc mods to prep for mainline | |
10 | * - Work was sponsored by CIS (M) Sdn Bhd. | |
11 | * Ported to Kernel 2.6.11 on June 26, 2005 by | |
12 | * Wolfgang Zuleger <wolfgang.zuleger@gmx.de> | |
13 | * Alexander Kiausch <alex.kiausch@t-online.de> | |
14 | * Originally developed by AMD for 2.4/2.6 | |
15 | * | |
16 | * Development of this chipset driver was funded | |
17 | * by the nice folks at National Semiconductor/AMD. | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or modify it | |
20 | * under the terms of the GNU General Public License version 2 as published by | |
21 | * the Free Software Foundation. | |
22 | * | |
23 | * Documentation: | |
24 | * CS5535 documentation available from AMD | |
25 | */ | |
26 | ||
f5b2d8b4 JK |
27 | #include <linux/module.h> |
28 | #include <linux/pci.h> | |
29 | #include <linux/ide.h> | |
30 | ||
31 | #include "ide-timing.h" | |
32 | ||
33 | #define MSR_ATAC_BASE 0x51300000 | |
34 | #define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0) | |
35 | #define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01) | |
36 | #define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02) | |
37 | #define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03) | |
38 | #define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04) | |
39 | #define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05) | |
40 | #define ATAC_IO_BAR (MSR_ATAC_BASE+0x08) | |
41 | #define ATAC_RESET (MSR_ATAC_BASE+0x10) | |
42 | #define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20) | |
43 | #define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21) | |
44 | #define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22) | |
45 | #define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23) | |
46 | #define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24) | |
47 | #define ATAC_BM0_CMD_PRIM 0x00 | |
48 | #define ATAC_BM0_STS_PRIM 0x02 | |
49 | #define ATAC_BM0_PRD 0x04 | |
50 | #define CS5535_CABLE_DETECT 0x48 | |
51 | ||
a1c6d28c | 52 | /* Format I PIO settings. We separate out cmd and data for safer timings */ |
f5b2d8b4 JK |
53 | |
54 | static unsigned int cs5535_pio_cmd_timings[5] = | |
55 | { 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 }; | |
56 | static unsigned int cs5535_pio_dta_timings[5] = | |
57 | { 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 }; | |
58 | ||
59 | static unsigned int cs5535_mwdma_timings[3] = | |
60 | { 0x7F0FFFF3, 0x7F035352, 0x7f024241 }; | |
61 | ||
62 | static unsigned int cs5535_udma_timings[5] = | |
63 | { 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 }; | |
64 | ||
65 | /* Macros to check if the register is the reset value - reset value is an | |
66 | invalid timing and indicates the register has not been set previously */ | |
67 | ||
68 | #define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 ) | |
69 | #define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 ) | |
70 | ||
71 | /**** | |
72 | * cs5535_set_speed - Configure the chipset to the new speed | |
73 | * @drive: Drive to set up | |
74 | * @speed: desired speed | |
75 | * | |
76 | * cs5535_set_speed() configures the chipset to a new speed. | |
77 | */ | |
f212ff28 | 78 | static void cs5535_set_speed(ide_drive_t *drive, const u8 speed) |
f5b2d8b4 JK |
79 | { |
80 | ||
81 | u32 reg = 0, dummy; | |
82 | int unit = drive->select.b.unit; | |
83 | ||
84 | ||
85 | /* Set the PIO timings */ | |
86 | if ((speed & XFER_MODE) == XFER_PIO) { | |
15d8061b | 87 | ide_drive_t *pair = ide_get_paired_drive(drive); |
bc0b0b5c | 88 | u8 cmd, pioa; |
f5b2d8b4 | 89 | |
bc0b0b5c BZ |
90 | cmd = pioa = speed - XFER_PIO_0; |
91 | ||
92 | if (pair->present) { | |
93 | u8 piob = ide_get_best_pio_mode(pair, 255, 4); | |
94 | ||
95 | if (piob < cmd) | |
96 | cmd = piob; | |
97 | } | |
f5b2d8b4 JK |
98 | |
99 | /* Write the speed of the current drive */ | |
100 | reg = (cs5535_pio_cmd_timings[cmd] << 16) | | |
101 | cs5535_pio_dta_timings[pioa]; | |
102 | wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0); | |
103 | ||
104 | /* And if nessesary - change the speed of the other drive */ | |
105 | rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy); | |
106 | ||
107 | if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) != | |
108 | cs5535_pio_cmd_timings[cmd]) { | |
109 | reg &= 0x0000FFFF; | |
110 | reg |= cs5535_pio_cmd_timings[cmd] << 16; | |
111 | wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0); | |
112 | } | |
113 | ||
114 | /* Set bit 31 of the DMA register for PIO format 1 timings */ | |
115 | rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy); | |
116 | wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, | |
117 | reg | 0x80000000UL, 0); | |
118 | } else { | |
119 | rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy); | |
120 | ||
121 | reg &= 0x80000000UL; /* Preserve the PIO format bit */ | |
122 | ||
32a70a81 | 123 | if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4) |
f5b2d8b4 JK |
124 | reg |= cs5535_udma_timings[speed - XFER_UDMA_0]; |
125 | else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) | |
126 | reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0]; | |
127 | else | |
128 | return; | |
129 | ||
130 | wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0); | |
131 | } | |
132 | } | |
133 | ||
88b2b32b BZ |
134 | /** |
135 | * cs5535_set_dma_mode - set host controller for DMA mode | |
136 | * @drive: drive | |
137 | * @speed: DMA mode | |
f5b2d8b4 | 138 | * |
88b2b32b | 139 | * Programs the chipset for DMA mode. |
f5b2d8b4 | 140 | */ |
249aa4ff | 141 | |
88b2b32b BZ |
142 | static void cs5535_set_dma_mode(ide_drive_t *drive, const u8 speed) |
143 | { | |
f5b2d8b4 | 144 | cs5535_set_speed(drive, speed); |
f5b2d8b4 JK |
145 | } |
146 | ||
26bcb879 | 147 | /** |
88b2b32b | 148 | * cs5535_set_pio_mode - set host controller for PIO mode |
26bcb879 BZ |
149 | * @drive: drive |
150 | * @pio: PIO mode number | |
f5b2d8b4 JK |
151 | * |
152 | * A callback from the upper layers for PIO-only tuning. | |
153 | */ | |
26bcb879 BZ |
154 | |
155 | static void cs5535_set_pio_mode(ide_drive_t *drive, const u8 pio) | |
f5b2d8b4 | 156 | { |
bc0b0b5c | 157 | cs5535_set_speed(drive, XFER_PIO_0 + pio); |
f5b2d8b4 JK |
158 | } |
159 | ||
f5b2d8b4 JK |
160 | static u8 __devinit cs5535_cable_detect(struct pci_dev *dev) |
161 | { | |
162 | u8 bit; | |
163 | ||
164 | /* if a 80 wire cable was detected */ | |
165 | pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit); | |
49521f97 BZ |
166 | |
167 | return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; | |
f5b2d8b4 JK |
168 | } |
169 | ||
170 | /**** | |
171 | * init_hwif_cs5535 - Initialize one ide cannel | |
172 | * @hwif: Channel descriptor | |
173 | * | |
174 | * This gets invoked by the IDE driver once for each channel. It | |
175 | * performs channel-specific pre-initialization before drive probing. | |
176 | * | |
177 | */ | |
178 | static void __devinit init_hwif_cs5535(ide_hwif_t *hwif) | |
179 | { | |
26bcb879 | 180 | hwif->set_pio_mode = &cs5535_set_pio_mode; |
88b2b32b | 181 | hwif->set_dma_mode = &cs5535_set_dma_mode; |
7bda292d | 182 | |
7bda292d BZ |
183 | if (hwif->dma_base == 0) |
184 | return; | |
185 | ||
49521f97 | 186 | hwif->cbl = cs5535_cable_detect(hwif->pci_dev); |
f5b2d8b4 JK |
187 | } |
188 | ||
85620436 | 189 | static const struct ide_port_info cs5535_chipset __devinitdata = { |
f5b2d8b4 JK |
190 | .name = "CS5535", |
191 | .init_hwif = init_hwif_cs5535, | |
7cab14a7 | 192 | .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE | |
4db90a14 | 193 | IDE_HFLAG_ABUSE_SET_DMA_MODE | IDE_HFLAG_BOOTABLE, |
4099d143 | 194 | .pio_mask = ATA_PIO4, |
5f8b6c34 BZ |
195 | .mwdma_mask = ATA_MWDMA2, |
196 | .udma_mask = ATA_UDMA4, | |
f5b2d8b4 JK |
197 | }; |
198 | ||
199 | static int __devinit cs5535_init_one(struct pci_dev *dev, | |
200 | const struct pci_device_id *id) | |
201 | { | |
202 | return ide_setup_pci_device(dev, &cs5535_chipset); | |
203 | } | |
204 | ||
9cbcc5e3 BZ |
205 | static const struct pci_device_id cs5535_pci_tbl[] = { |
206 | { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 }, | |
f5b2d8b4 JK |
207 | { 0, }, |
208 | }; | |
209 | ||
210 | MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl); | |
211 | ||
212 | static struct pci_driver driver = { | |
213 | .name = "CS5535_IDE", | |
214 | .id_table = cs5535_pci_tbl, | |
215 | .probe = cs5535_init_one, | |
216 | }; | |
217 | ||
218 | static int __init cs5535_ide_init(void) | |
219 | { | |
220 | return ide_pci_register_driver(&driver); | |
221 | } | |
222 | ||
223 | module_init(cs5535_ide_init); | |
224 | ||
225 | MODULE_AUTHOR("AMD"); | |
226 | MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE"); | |
227 | MODULE_LICENSE("GPL"); |