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1da177e4 LT |
1 | /* |
2 | * IDE tuning and bus mastering support for the CS5510/CS5520 | |
3 | * chipsets | |
4 | * | |
5 | * The CS5510/CS5520 are slightly unusual devices. Unlike the | |
6 | * typical IDE controllers they do bus mastering with the drive in | |
7 | * PIO mode and smarter silicon. | |
8 | * | |
9 | * The practical upshot of this is that we must always tune the | |
10 | * drive for the right PIO mode. We must also ignore all the blacklists | |
11 | * and the drive bus mastering DMA information. | |
12 | * | |
13 | * *** This driver is strictly experimental *** | |
14 | * | |
15 | * (c) Copyright Red Hat Inc 2002 | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify it | |
18 | * under the terms of the GNU General Public License as published by the | |
19 | * Free Software Foundation; either version 2, or (at your option) any | |
20 | * later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, but | |
23 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
25 | * General Public License for more details. | |
26 | * | |
27 | * For the avoidance of doubt the "preferred form" of this code is one which | |
28 | * is in an open non patent encumbered format. Where cryptographic key signing | |
29 | * forms part of the process of creating an executable the information | |
30 | * including keys needed to generate an equivalently functional executable | |
31 | * are deemed to be part of the source code. | |
32 | * | |
33 | */ | |
34 | ||
1da177e4 LT |
35 | #include <linux/module.h> |
36 | #include <linux/types.h> | |
37 | #include <linux/kernel.h> | |
1da177e4 | 38 | #include <linux/hdreg.h> |
1da177e4 LT |
39 | #include <linux/init.h> |
40 | #include <linux/pci.h> | |
41 | #include <linux/ide.h> | |
42 | #include <linux/dma-mapping.h> | |
43 | ||
1da177e4 LT |
44 | struct pio_clocks |
45 | { | |
46 | int address; | |
47 | int assert; | |
48 | int recovery; | |
49 | }; | |
50 | ||
51 | static struct pio_clocks cs5520_pio_clocks[]={ | |
52 | {3, 6, 11}, | |
53 | {2, 5, 6}, | |
54 | {1, 4, 3}, | |
55 | {1, 3, 2}, | |
56 | {1, 2, 1} | |
57 | }; | |
58 | ||
8f4dd2e4 | 59 | static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 LT |
60 | { |
61 | ide_hwif_t *hwif = HWIF(drive); | |
36501650 | 62 | struct pci_dev *pdev = to_pci_dev(hwif->dev); |
1da177e4 | 63 | int controller = drive->dn > 1 ? 1 : 0; |
f212ff28 | 64 | |
1da177e4 LT |
65 | /* FIXME: if DMA = 1 do we need to set the DMA bit here ? */ |
66 | ||
67 | /* 8bit CAT/CRT - 8bit command timing for channel */ | |
68 | pci_write_config_byte(pdev, 0x62 + controller, | |
69 | (cs5520_pio_clocks[pio].recovery << 4) | | |
70 | (cs5520_pio_clocks[pio].assert)); | |
71 | ||
72 | /* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */ | |
73 | ||
74 | /* FIXME: should these use address ? */ | |
75 | /* Data read timing */ | |
76 | pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1), | |
77 | (cs5520_pio_clocks[pio].recovery << 4) | | |
78 | (cs5520_pio_clocks[pio].assert)); | |
79 | /* Write command timing */ | |
80 | pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1), | |
81 | (cs5520_pio_clocks[pio].recovery << 4) | | |
82 | (cs5520_pio_clocks[pio].assert)); | |
326d72f4 | 83 | } |
26bcb879 | 84 | |
88b2b32b | 85 | static void cs5520_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 86 | { |
8f4dd2e4 BZ |
87 | printk(KERN_ERR "cs55x0: bad ide timing.\n"); |
88 | ||
89 | cs5520_set_pio_mode(drive, 0); | |
1da177e4 LT |
90 | } |
91 | ||
1da177e4 LT |
92 | /* |
93 | * We wrap the DMA activate to set the vdma flag. This is needed | |
94 | * so that the IDE DMA layer issues PIO not DMA commands over the | |
95 | * DMA channel | |
aea5d375 BZ |
96 | * |
97 | * ATAPI is harder so disable it for now using IDE_HFLAG_NO_ATAPI_DMA | |
1da177e4 | 98 | */ |
aea5d375 | 99 | |
15ce926a | 100 | static void cs5520_dma_host_set(ide_drive_t *drive, int on) |
aea5d375 | 101 | { |
15ce926a BZ |
102 | drive->vdma = on; |
103 | ide_dma_host_set(drive, on); | |
1da177e4 LT |
104 | } |
105 | ||
106 | static void __devinit init_hwif_cs5520(ide_hwif_t *hwif) | |
107 | { | |
26bcb879 | 108 | hwif->set_pio_mode = &cs5520_set_pio_mode; |
88b2b32b | 109 | hwif->set_dma_mode = &cs5520_set_dma_mode; |
1da177e4 | 110 | |
f0bb945c | 111 | if (hwif->dma_base == 0) |
1da177e4 | 112 | return; |
326d72f4 | 113 | |
15ce926a | 114 | hwif->dma_host_set = &cs5520_dma_host_set; |
1da177e4 LT |
115 | } |
116 | ||
117 | #define DECLARE_CS_DEV(name_str) \ | |
118 | { \ | |
119 | .name = name_str, \ | |
1da177e4 | 120 | .init_hwif = init_hwif_cs5520, \ |
0ae2e178 | 121 | .host_flags = IDE_HFLAG_ISA_PORTS | \ |
9ffcf364 | 122 | IDE_HFLAG_CS5520 | \ |
33c1002e | 123 | IDE_HFLAG_VDMA | \ |
7cab14a7 | 124 | IDE_HFLAG_NO_ATAPI_DMA | \ |
4db90a14 | 125 | IDE_HFLAG_ABUSE_SET_DMA_MODE |\ |
7cab14a7 | 126 | IDE_HFLAG_BOOTABLE, \ |
4099d143 | 127 | .pio_mask = ATA_PIO4, \ |
1da177e4 LT |
128 | } |
129 | ||
85620436 | 130 | static const struct ide_port_info cyrix_chipsets[] __devinitdata = { |
1da177e4 LT |
131 | /* 0 */ DECLARE_CS_DEV("Cyrix 5510"), |
132 | /* 1 */ DECLARE_CS_DEV("Cyrix 5520") | |
133 | }; | |
134 | ||
135 | /* | |
136 | * The 5510/5520 are a bit weird. They don't quite set up the way | |
137 | * the PCI helper layer expects so we must do much of the set up | |
138 | * work longhand. | |
139 | */ | |
140 | ||
141 | static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
142 | { | |
85620436 | 143 | const struct ide_port_info *d = &cyrix_chipsets[id->driver_data]; |
8447d9d5 | 144 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 LT |
145 | |
146 | ide_setup_pci_noise(dev, d); | |
147 | ||
148 | /* We must not grab the entire device, it has 'ISA' space in its | |
09483916 BH |
149 | * BARS too and we will freak out other bits of the kernel |
150 | * | |
151 | * pci_enable_device_bars() is going away. I replaced it with | |
152 | * IO only enable for now but I'll need confirmation this is | |
153 | * allright for that device. If not, it will need some kind of | |
154 | * quirk. --BenH. | |
155 | */ | |
156 | if (pci_enable_device_io(dev)) { | |
1da177e4 | 157 | printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name); |
1e39dead | 158 | return -ENODEV; |
1da177e4 LT |
159 | } |
160 | pci_set_master(dev); | |
161 | if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { | |
162 | printk(KERN_WARNING "cs5520: No suitable DMA available.\n"); | |
163 | return -ENODEV; | |
164 | } | |
165 | ||
1da177e4 LT |
166 | /* |
167 | * Now the chipset is configured we can let the core | |
168 | * do all the device setup for us | |
169 | */ | |
170 | ||
8447d9d5 | 171 | ide_pci_setup_ports(dev, d, 14, &idx[0]); |
5cbf79cd | 172 | |
c413b9b9 | 173 | ide_device_add(idx, d); |
5cbf79cd | 174 | |
1da177e4 LT |
175 | return 0; |
176 | } | |
177 | ||
9cbcc5e3 BZ |
178 | static const struct pci_device_id cs5520_pci_tbl[] = { |
179 | { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), 0 }, | |
180 | { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), 1 }, | |
1da177e4 LT |
181 | { 0, }, |
182 | }; | |
183 | MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl); | |
184 | ||
185 | static struct pci_driver driver = { | |
186 | .name = "Cyrix_IDE", | |
187 | .id_table = cs5520_pci_tbl, | |
188 | .probe = cs5520_init_one, | |
189 | }; | |
190 | ||
82ab1eec | 191 | static int __init cs5520_ide_init(void) |
1da177e4 LT |
192 | { |
193 | return ide_pci_register_driver(&driver); | |
194 | } | |
195 | ||
196 | module_init(cs5520_ide_init); | |
197 | ||
198 | MODULE_AUTHOR("Alan Cox"); | |
199 | MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE"); | |
200 | MODULE_LICENSE("GPL"); |