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Documentation/i386/boot.txt: update and correct
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / cmd64x.c
CommitLineData
60e7a82f 1/*
66602c83 2 * linux/drivers/ide/pci/cmd64x.c Version 1.47 Mar 19, 2007
1da177e4
LT		 3 *
4 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
1da177e4
LT		 5 * Due to massive hardware bugs, UltraDMA is only supported
6 * on the 646U2 and not on the 646U.
7 *
8 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
10 *
11 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
f92d50e6 12 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4
LT		 13 */
14
1da177e4
LT		 15#include <linux/module.h>
16#include <linux/types.h>
17#include <linux/pci.h>
18#include <linux/delay.h>
19#include <linux/hdreg.h>
20#include <linux/ide.h>
21#include <linux/init.h>
22
23#include <asm/io.h>
24
25#define DISPLAY_CMD64X_TIMINGS
26
27#define CMD_DEBUG 0
28
29#if CMD_DEBUG
30#define cmdprintk(x...) printk(x)
31#else
32#define cmdprintk(x...)
33#endif
34
35/*
36 * CMD64x specific registers definition.
37 */
38#define CFR 0x50
e51e2528 39#define CFR_INTR_CH0 0x04
1da177e4 40#define CNTRL 0x51
5826b318
SS		 41#define CNTRL_ENA_1ST 0x04
42#define CNTRL_ENA_2ND 0x08
43#define CNTRL_DIS_RA0 0x40
44#define CNTRL_DIS_RA1 0x80
1da177e4
LT		 45
46#define CMDTIM 0x52
47#define ARTTIM0 0x53
48#define DRWTIM0 0x54
49#define ARTTIM1 0x55
50#define DRWTIM1 0x56
51#define ARTTIM23 0x57
52#define ARTTIM23_DIS_RA2 0x04
53#define ARTTIM23_DIS_RA3 0x08
54#define ARTTIM23_INTR_CH1 0x10
55#define ARTTIM2 0x57
56#define ARTTIM3 0x57
57#define DRWTIM23 0x58
58#define DRWTIM2 0x58
59#define BRST 0x59
60#define DRWTIM3 0x5b
61
62#define BMIDECR0 0x70
63#define MRDMODE 0x71
64#define MRDMODE_INTR_CH0 0x04
65#define MRDMODE_INTR_CH1 0x08
66#define MRDMODE_BLK_CH0 0x10
67#define MRDMODE_BLK_CH1 0x20
68#define BMIDESR0 0x72
69#define UDIDETCR0 0x73
70#define DTPR0 0x74
71#define BMIDECR1 0x78
72#define BMIDECSR 0x79
73#define BMIDESR1 0x7A
74#define UDIDETCR1 0x7B
75#define DTPR1 0x7C
76
77#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
78#include <linux/stat.h>
79#include <linux/proc_fs.h>
80
81static u8 cmd64x_proc = 0;
82
83#define CMD_MAX_DEVS 5
84
85static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
86static int n_cmd_devs;
87
88static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
89{
90 char *p = buf;
1da177e4
LT		 91 u8 reg72 = 0, reg73 = 0; /* primary */
92 u8 reg7a = 0, reg7b = 0; /* secondary */
5826b318
SS		 93 u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */
94 u8 rev = 0;
1da177e4
LT		 95
96 p += sprintf(p, "\nController: %d\n", index);
5826b318
SS		 97 p += sprintf(p, "PCI-%x Chipset.\n", dev->device);
98
1da177e4 99 (void) pci_read_config_byte(dev, CFR, &reg50);
5826b318
SS		 100 (void) pci_read_config_byte(dev, CNTRL, &reg51);
101 (void) pci_read_config_byte(dev, ARTTIM23, &reg57);
1da177e4
LT		 102 (void) pci_read_config_byte(dev, MRDMODE, &reg71);
103 (void) pci_read_config_byte(dev, BMIDESR0, &reg72);
104 (void) pci_read_config_byte(dev, UDIDETCR0, &reg73);
105 (void) pci_read_config_byte(dev, BMIDESR1, &reg7a);
106 (void) pci_read_config_byte(dev, UDIDETCR1, &reg7b);
107
5826b318
SS		 108 /* PCI0643/6 originally didn't have the primary channel enable bit */
109 (void) pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
110 if ((dev->device == PCI_DEVICE_ID_CMD_643) ||
111 (dev->device == PCI_DEVICE_ID_CMD_646 && rev < 3))
112 reg51 |= CNTRL_ENA_1ST;
113
114 p += sprintf(p, "---------------- Primary Channel "
115 "---------------- Secondary Channel ------------\n");
116 p += sprintf(p, " %s %s\n",
117 (reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled",
118 (reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled");
119 p += sprintf(p, "---------------- drive0 --------- drive1 "
120 "-------- drive0 --------- drive1 ------\n");
121 p += sprintf(p, "DMA enabled: %s %s"
122 " %s %s\n",
123 (reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ",
124 (reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no ");
125 p += sprintf(p, "UltraDMA mode: %s (%c) %s (%c)",
126 ( reg73 & 0x01) ? " on" : "off",
127 ((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') :
128 ((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') :
129 ((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') :
130 ((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?',
131 ( reg73 & 0x02) ? " on" : "off",
132 ((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') :
133 ((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') :
134 ((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') :
135 ((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?');
136 p += sprintf(p, " %s (%c) %s (%c)\n",
137 ( reg7b & 0x01) ? " on" : "off",
138 ((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') :
139 ((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') :
140 ((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') :
141 ((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?',
142 ( reg7b & 0x02) ? " on" : "off",
143 ((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') :
144 ((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') :
145 ((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') :
146 ((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?');
147 p += sprintf(p, "Interrupt: %s, %s %s, %s\n",
148 (reg71 & MRDMODE_BLK_CH0 ) ? "blocked" : "enabled",
149 (reg50 & CFR_INTR_CH0 ) ? "pending" : "clear ",
150 (reg71 & MRDMODE_BLK_CH1 ) ? "blocked" : "enabled",
151 (reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear ");
1da177e4
LT		 152
153 return (char *)p;
154}
155
156static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
157{
158 char *p = buffer;
159 int i;
160
1da177e4
LT		 161 for (i = 0; i < n_cmd_devs; i++) {
162 struct pci_dev *dev = cmd_devs[i];
163 p = print_cmd64x_get_info(p, dev, i);
164 }
165 return p-buffer; /* => must be less than 4k! */
166}
167
168#endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */
169
e277a1aa
SS		 170static u8 quantize_timing(int timing, int quant)
171{
172 return (timing + quant - 1) / quant;
173}
174
1da177e4 175/*
60e7a82f
SS		 176 * This routine calculates active/recovery counts and then writes them into
177 * the chipset registers.
1da177e4 178 */
60e7a82f 179static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
1da177e4 180{
60e7a82f
SS		 181 struct pci_dev *dev = HWIF(drive)->pci_dev;
182 int clock_time = 1000 / system_bus_clock();
183 u8 cycle_count, active_count, recovery_count, drwtim;
184 static const u8 recovery_values[] =
1da177e4 185 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
60e7a82f
SS		 186 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
187
188 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
189 cycle_time, active_time);
190
191 cycle_count = quantize_timing( cycle_time, clock_time);
192 active_count = quantize_timing(active_time, clock_time);
193 recovery_count = cycle_count - active_count;
194
1da177e4 195 /*
60e7a82f
SS		 196 * In case we've got too long recovery phase, try to lengthen
197 * the active phase
1da177e4 198 */
60e7a82f
SS		 199 if (recovery_count > 16) {
200 active_count += recovery_count - 16;
201 recovery_count = 16;
1da177e4 202 }
60e7a82f
SS		 203 if (active_count > 16) /* shouldn't actually happen... */
204 active_count = 16;
205
206 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
207 cycle_count, active_count, recovery_count);
1da177e4
LT		 208
209 /*
210 * Convert values to internal chipset representation
211 */
60e7a82f
SS		 212 recovery_count = recovery_values[recovery_count];
213 active_count &= 0x0f;
1da177e4 214
60e7a82f
SS		 215 /* Program the active/recovery counts into the DRWTIM register */
216 drwtim = (active_count << 4) | recovery_count;
217 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
218 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
1da177e4
LT		 219}
220
221/*
60e7a82f
SS		 222 * This routine selects drive's best PIO mode and writes into the chipset
223 * registers setup/active/recovery timings.
1da177e4 224 */
f92d50e6 225static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted)
1da177e4 226{
60e7a82f
SS		 227 ide_hwif_t *hwif = HWIF(drive);
228 struct pci_dev *dev = hwif->pci_dev;
e277a1aa 229 ide_pio_data_t pio;
60e7a82f
SS		 230 u8 pio_mode, setup_count, arttim = 0;
231 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
232 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
e277a1aa 233 pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio);
1da177e4 234
60e7a82f
SS		 235 cmdprintk("%s: PIO mode wanted %d, selected %d (%d ns)%s\n",
236 drive->name, mode_wanted, pio_mode, pio.cycle_time,
237 pio.overridden ? " (overriding vendor mode)" : "");
1da177e4 238
60e7a82f
SS		 239 program_cycle_times(drive, pio.cycle_time,
240 ide_pio_timings[pio_mode].active_time);
1da177e4 241
60e7a82f
SS		 242 setup_count = quantize_timing(ide_pio_timings[pio_mode].setup_time,
243 1000 / system_bus_clock());
244
245 /*
246 * The primary channel has individual address setup timing registers
247 * for each drive and the hardware selects the slowest timing itself.
248 * The secondary channel has one common register and we have to select
249 * the slowest address setup timing ourselves.
250 */
251 if (hwif->channel) {
252 ide_drive_t *drives = hwif->drives;
253
254 drive->drive_data = setup_count;
255 setup_count = max(drives[0].drive_data, drives[1].drive_data);
1da177e4 256 }
1da177e4 257
60e7a82f
SS		 258 if (setup_count > 5) /* shouldn't actually happen... */
259 setup_count = 5;
260 cmdprintk("Final address setup count: %d\n", setup_count);
1da177e4 261
60e7a82f
SS		 262 /*
263 * Program the address setup clocks into the ARTTIM registers.
264 * Avoid clearing the secondary channel's interrupt bit.
265 */
266 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
267 if (hwif->channel)
268 arttim &= ~ARTTIM23_INTR_CH1;
269 arttim &= ~0xc0;
270 arttim |= setup_values[setup_count];
271 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
272 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
f92d50e6
SS		 273
274 return pio_mode;
275}
276
277/*
278 * Attempts to set drive's PIO mode.
279 * Special cases are 8: prefetch off, 9: prefetch on (both never worked),
280 * and 255: auto-select best mode (used at boot time).
281 */
282static void cmd64x_tune_drive (ide_drive_t *drive, u8 pio)
283{
284 /*
285 * Filter out the prefetch control values
286 * to prevent PIO5 from being programmed
287 */
288 if (pio == 8 || pio == 9)
289 return;
290
291 pio = cmd64x_tune_pio(drive, pio);
292 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
1da177e4
LT		 293}
294
295static u8 cmd64x_ratemask (ide_drive_t *drive)
296{
297 struct pci_dev *dev = HWIF(drive)->pci_dev;
298 u8 mode = 0;
299
300 switch(dev->device) {
301 case PCI_DEVICE_ID_CMD_649:
302 mode = 3;
303 break;
304 case PCI_DEVICE_ID_CMD_648:
305 mode = 2;
306 break;
307 case PCI_DEVICE_ID_CMD_643:
308 return 0;
309
310 case PCI_DEVICE_ID_CMD_646:
311 {
312 unsigned int class_rev = 0;
313 pci_read_config_dword(dev,
314 PCI_CLASS_REVISION, &class_rev);
315 class_rev &= 0xff;
316 /*
317 * UltraDMA only supported on PCI646U and PCI646U2, which
318 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
319 * Actually, although the CMD tech support people won't
320 * tell me the details, the 0x03 revision cannot support
321 * UDMA correctly without hardware modifications, and even
322 * then it only works with Quantum disks due to some
323 * hold time assumptions in the 646U part which are fixed
324 * in the 646U2.
325 *
326 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
327 */
328 switch(class_rev) {
329 case 0x07:
330 case 0x05:
331 return 1;
332 case 0x03:
333 case 0x01:
334 default:
335 return 0;
336 }
337 }
338 }
339 if (!eighty_ninty_three(drive))
340 mode = min(mode, (u8)1);
341 return mode;
342}
343
60e7a82f 344static int cmd64x_tune_chipset (ide_drive_t *drive, u8 speed)
1da177e4
LT		 345{
346 ide_hwif_t *hwif = HWIF(drive);
347 struct pci_dev *dev = hwif->pci_dev;
60e7a82f
SS		 348 u8 unit = drive->dn & 0x01;
349 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
1da177e4 350
60e7a82f 351 speed = ide_rate_filter(cmd64x_ratemask(drive), speed);
1da177e4 352
f92d50e6 353 if (speed >= XFER_SW_DMA_0) {
1da177e4 354 (void) pci_read_config_byte(dev, pciU, &regU);
1da177e4 355 regU &= ~(unit ? 0xCA : 0x35);
1da177e4
LT		 356 }
357
358 switch(speed) {
60e7a82f
SS		 359 case XFER_UDMA_5:
360 regU |= unit ? 0x0A : 0x05;
361 break;
362 case XFER_UDMA_4:
363 regU |= unit ? 0x4A : 0x15;
364 break;
365 case XFER_UDMA_3:
366 regU |= unit ? 0x8A : 0x25;
367 break;
368 case XFER_UDMA_2:
369 regU |= unit ? 0x42 : 0x11;
370 break;
371 case XFER_UDMA_1:
372 regU |= unit ? 0x82 : 0x21;
373 break;
374 case XFER_UDMA_0:
375 regU |= unit ? 0xC2 : 0x31;
376 break;
377 case XFER_MW_DMA_2:
378 program_cycle_times(drive, 120, 70);
379 break;
380 case XFER_MW_DMA_1:
381 program_cycle_times(drive, 150, 80);
382 break;
383 case XFER_MW_DMA_0:
384 program_cycle_times(drive, 480, 215);
385 break;
386 case XFER_PIO_5:
387 case XFER_PIO_4:
388 case XFER_PIO_3:
389 case XFER_PIO_2:
390 case XFER_PIO_1:
391 case XFER_PIO_0:
392 (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0);
393 break;
394 default:
395 return 1;
1da177e4
LT		 396 }
397
60e7a82f 398 if (speed >= XFER_SW_DMA_0)
1da177e4 399 (void) pci_write_config_byte(dev, pciU, regU);
1da177e4 400
60e7a82f 401 return ide_config_drive_speed(drive, speed);
1da177e4
LT		 402}
403
404static int config_chipset_for_dma (ide_drive_t *drive)
405{
406 u8 speed = ide_dma_speed(drive, cmd64x_ratemask(drive));
407
1da177e4
LT		 408 if (!speed)
409 return 0;
410
056a697b
BZ		 411 if (cmd64x_tune_chipset(drive, speed))
412 return 0;
1da177e4
LT		 413
414 return ide_dma_enable(drive);
415}
416
417static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
418{
7569e8dc 419 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
3608b5d7 420 return 0;
1da177e4 421
d8f4469d 422 if (ide_use_fast_pio(drive))
f92d50e6 423 cmd64x_tune_drive(drive, 255);
d8f4469d 424
3608b5d7 425 return -1;
1da177e4
LT		 426}
427
66602c83 428static int cmd648_ide_dma_end (ide_drive_t *drive)
1da177e4 429{
66602c83
SS		 430 ide_hwif_t *hwif = HWIF(drive);
431 int err = __ide_dma_end(drive);
432 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
433 MRDMODE_INTR_CH0;
434 u8 mrdmode = inb(hwif->dma_master + 0x01);
435
436 /* clear the interrupt bit */
437 outb(mrdmode | irq_mask, hwif->dma_master + 0x01);
438
439 return err;
1da177e4
LT		 440}
441
442static int cmd64x_ide_dma_end (ide_drive_t *drive)
443{
1da177e4
LT		 444 ide_hwif_t *hwif = HWIF(drive);
445 struct pci_dev *dev = hwif->pci_dev;
66602c83
SS		 446 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
447 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
448 CFR_INTR_CH0;
449 u8 irq_stat = 0;
450 int err = __ide_dma_end(drive);
1da177e4 451
66602c83
SS		 452 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
453 /* clear the interrupt bit */
454 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
455
456 return err;
457}
458
459static int cmd648_ide_dma_test_irq (ide_drive_t *drive)
460{
461 ide_hwif_t *hwif = HWIF(drive);
462 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
463 MRDMODE_INTR_CH0;
464 u8 dma_stat = inb(hwif->dma_status);
465 u8 mrdmode = inb(hwif->dma_master + 0x01);
466
467#ifdef DEBUG
468 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
469 drive->name, dma_stat, mrdmode, irq_mask);
470#endif
471 if (!(mrdmode & irq_mask))
472 return 0;
473
474 /* return 1 if INTR asserted */
475 if (dma_stat & 4)
476 return 1;
477
478 return 0;
1da177e4
LT		 479}
480
481static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
482{
e51e2528
SS		 483 ide_hwif_t *hwif = HWIF(drive);
484 struct pci_dev *dev = hwif->pci_dev;
66602c83
SS		 485 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
486 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
487 CFR_INTR_CH0;
488 u8 dma_stat = inb(hwif->dma_status);
489 u8 irq_stat = 0;
e51e2528
SS		 490
491 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
1da177e4 492
1da177e4 493#ifdef DEBUG
66602c83
SS		 494 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
495 drive->name, dma_stat, irq_stat, irq_mask);
1da177e4 496#endif
66602c83 497 if (!(irq_stat & irq_mask))
1da177e4
LT		 498 return 0;
499
500 /* return 1 if INTR asserted */
66602c83 501 if (dma_stat & 4)
1da177e4
LT		 502 return 1;
503
504 return 0;
505}
506
507/*
508 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
509 * event order for DMA transfers.
510 */
511
512static int cmd646_1_ide_dma_end (ide_drive_t *drive)
513{
514 ide_hwif_t *hwif = HWIF(drive);
515 u8 dma_stat = 0, dma_cmd = 0;
516
517 drive->waiting_for_dma = 0;
518 /* get DMA status */
0ecdca26 519 dma_stat = inb(hwif->dma_status);
1da177e4 520 /* read DMA command state */
0ecdca26 521 dma_cmd = inb(hwif->dma_command);
1da177e4 522 /* stop DMA */
0ecdca26 523 outb(dma_cmd & ~1, hwif->dma_command);
1da177e4 524 /* clear the INTR & ERROR bits */
0ecdca26 525 outb(dma_stat | 6, hwif->dma_status);
1da177e4
LT		 526 /* and free any DMA resources */
527 ide_destroy_dmatable(drive);
528 /* verify good DMA status */
529 return (dma_stat & 7) != 4;
530}
531
532static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
533{
534 u32 class_rev = 0;
535 u8 mrdmode = 0;
536
537 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
538 class_rev &= 0xff;
539
1da177e4
LT		 540 switch(dev->device) {
541 case PCI_DEVICE_ID_CMD_643:
542 break;
543 case PCI_DEVICE_ID_CMD_646:
544 printk(KERN_INFO "%s: chipset revision 0x%02X, ", name, class_rev);
545 switch(class_rev) {
546 case 0x07:
547 case 0x05:
548 printk("UltraDMA Capable");
549 break;
550 case 0x03:
551 printk("MultiWord DMA Force Limited");
552 break;
553 case 0x01:
554 default:
555 printk("MultiWord DMA Limited, IRQ workaround enabled");
556 break;
557 }
558 printk("\n");
559 break;
560 case PCI_DEVICE_ID_CMD_648:
561 case PCI_DEVICE_ID_CMD_649:
562 break;
563 default:
564 break;
565 }
566
567 /* Set a good latency timer and cache line size value. */
568 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
569 /* FIXME: pci_set_master() to ensure a good latency timer value */
570
571 /* Setup interrupts. */
572 (void) pci_read_config_byte(dev, MRDMODE, &mrdmode);
573 mrdmode &= ~(0x30);
574 (void) pci_write_config_byte(dev, MRDMODE, mrdmode);
575
576 /* Use MEMORY READ LINE for reads.
577 * NOTE: Although not mentioned in the PCI0646U specs,
578 * these bits are write only and won't be read
579 * back as set or not. The PCI0646U2 specs clarify
580 * this point.
581 */
582 (void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02);
583
584 /* Set reasonable active/recovery/address-setup values. */
585 (void) pci_write_config_byte(dev, ARTTIM0, 0x40);
586 (void) pci_write_config_byte(dev, DRWTIM0, 0x3f);
587 (void) pci_write_config_byte(dev, ARTTIM1, 0x40);
588 (void) pci_write_config_byte(dev, DRWTIM1, 0x3f);
589#ifdef __i386__
590 (void) pci_write_config_byte(dev, ARTTIM23, 0x1c);
591#else
592 (void) pci_write_config_byte(dev, ARTTIM23, 0x5c);
593#endif
594 (void) pci_write_config_byte(dev, DRWTIM23, 0x3f);
595 (void) pci_write_config_byte(dev, DRWTIM3, 0x3f);
596#ifdef CONFIG_PPC
597 (void) pci_write_config_byte(dev, UDIDETCR0, 0xf0);
598#endif /* CONFIG_PPC */
599
600#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
601
602 cmd_devs[n_cmd_devs++] = dev;
603
604 if (!cmd64x_proc) {
605 cmd64x_proc = 1;
606 ide_pci_create_host_proc("cmd64x", cmd64x_get_info);
607 }
608#endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */
609
610 return 0;
611}
612
613static unsigned int __devinit ata66_cmd64x(ide_hwif_t *hwif)
614{
615 u8 ata66 = 0, mask = (hwif->channel) ? 0x02 : 0x01;
616
617 switch(hwif->pci_dev->device) {
618 case PCI_DEVICE_ID_CMD_643:
619 case PCI_DEVICE_ID_CMD_646:
620 return ata66;
621 default:
622 break;
623 }
624 pci_read_config_byte(hwif->pci_dev, BMIDECSR, &ata66);
625 return (ata66 & mask) ? 1 : 0;
626}
627
628static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
629{
630 struct pci_dev *dev = hwif->pci_dev;
631 unsigned int class_rev;
632
633 hwif->autodma = 0;
634 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
635 class_rev &= 0xff;
636
f92d50e6 637 hwif->tuneproc = &cmd64x_tune_drive;
1da177e4
LT		 638 hwif->speedproc = &cmd64x_tune_chipset;
639
f92d50e6
SS		 640 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
641
642 if (!hwif->dma_base)
1da177e4 643 return;
1da177e4
LT		 644
645 hwif->atapi_dma = 1;
646
647 hwif->ultra_mask = 0x3f;
648 hwif->mwdma_mask = 0x07;
1da177e4
LT		 649
650 if (dev->device == PCI_DEVICE_ID_CMD_643)
651 hwif->ultra_mask = 0x80;
652 if (dev->device == PCI_DEVICE_ID_CMD_646)
653 hwif->ultra_mask = (class_rev > 0x04) ? 0x07 : 0x80;
654 if (dev->device == PCI_DEVICE_ID_CMD_648)
655 hwif->ultra_mask = 0x1f;
656
657 hwif->ide_dma_check = &cmd64x_config_drive_for_dma;
658 if (!(hwif->udma_four))
659 hwif->udma_four = ata66_cmd64x(hwif);
660
66602c83
SS		 661 switch(dev->device) {
662 case PCI_DEVICE_ID_CMD_648:
663 case PCI_DEVICE_ID_CMD_649:
664 alt_irq_bits:
665 hwif->ide_dma_end = &cmd648_ide_dma_end;
666 hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq;
667 break;
668 case PCI_DEVICE_ID_CMD_646:
1da177e4
LT		 669 hwif->chipset = ide_cmd646;
670 if (class_rev == 0x01) {
671 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
66602c83
SS		 672 break;
673 } else if (class_rev >= 0x03)
674 goto alt_irq_bits;
675 /* fall thru */
676 default:
677 hwif->ide_dma_end = &cmd64x_ide_dma_end;
678 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
679 break;
1da177e4
LT		 680 }
681
682
683 if (!noautodma)
684 hwif->autodma = 1;
685 hwif->drives[0].autodma = hwif->autodma;
686 hwif->drives[1].autodma = hwif->autodma;
687}
688
7accbffd
SS		 689static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d)
690{
691 return ide_setup_pci_device(dev, d);
692}
693
694static int __devinit init_setup_cmd646(struct pci_dev *dev, ide_pci_device_t *d)
695{
696 u8 rev = 0;
697
698 /*
699 * The original PCI0646 didn't have the primary channel enable bit,
700 * it appeared starting with PCI0646U (i.e. revision ID 3).
701 */
702 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
703 if (rev < 3)
704 d->enablebits[0].reg = 0;
705
706 return ide_setup_pci_device(dev, d);
707}
708
1da177e4
LT		 709static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
710 { /* 0 */
711 .name = "CMD643",
7accbffd 712 .init_setup = init_setup_cmd64x,
1da177e4
LT		 713 .init_chipset = init_chipset_cmd64x,
714 .init_hwif = init_hwif_cmd64x,
715 .channels = 2,
716 .autodma = AUTODMA,
7accbffd 717 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
1da177e4
LT		 718 .bootable = ON_BOARD,
719 },{ /* 1 */
720 .name = "CMD646",
7accbffd 721 .init_setup = init_setup_cmd646,
1da177e4
LT		 722 .init_chipset = init_chipset_cmd64x,
723 .init_hwif = init_hwif_cmd64x,
724 .channels = 2,
725 .autodma = AUTODMA,
7accbffd 726 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
1da177e4
LT		 727 .bootable = ON_BOARD,
728 },{ /* 2 */
729 .name = "CMD648",
7accbffd 730 .init_setup = init_setup_cmd64x,
1da177e4
LT		 731 .init_chipset = init_chipset_cmd64x,
732 .init_hwif = init_hwif_cmd64x,
733 .channels = 2,
734 .autodma = AUTODMA,
7accbffd 735 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
1da177e4
LT		 736 .bootable = ON_BOARD,
737 },{ /* 3 */
738 .name = "CMD649",
7accbffd 739 .init_setup = init_setup_cmd64x,
1da177e4
LT		 740 .init_chipset = init_chipset_cmd64x,
741 .init_hwif = init_hwif_cmd64x,
742 .channels = 2,
743 .autodma = AUTODMA,
7accbffd 744 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
1da177e4
LT		 745 .bootable = ON_BOARD,
746 }
747};
748
7accbffd
SS		 749/*
750 * We may have to modify enablebits for PCI0646, so we'd better pass
751 * a local copy of the ide_pci_device_t structure down the call chain...
752 */
1da177e4
LT		 753static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
754{
7accbffd
SS		 755 ide_pci_device_t d = cmd64x_chipsets[id->driver_data];
756
757 return d.init_setup(dev, &d);
1da177e4
LT		 758}
759
760static struct pci_device_id cmd64x_pci_tbl[] = {
761 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
762 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
763 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
764 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
765 { 0, },
766};
767MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
768
769static struct pci_driver driver = {
770 .name = "CMD64x_IDE",
771 .id_table = cmd64x_pci_tbl,
772 .probe = cmd64x_init_one,
773};
774
82ab1eec 775static int __init cmd64x_ide_init(void)
1da177e4
LT		 776{
777 return ide_pci_register_driver(&driver);
778}
779
780module_init(cmd64x_ide_init);
781
782MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
783MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
784MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)