projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PCI: Change all drivers to use pci_device->revision
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ide / pci / cmd64x.c
CommitLineData
60e7a82f 1/*
83a6d4ab 2 * linux/drivers/ide/pci/cmd64x.c Version 1.50 May 10, 2007
1da177e4
LT		 3 *
4 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
1da177e4
LT		 5 * Due to massive hardware bugs, UltraDMA is only supported
6 * on the 646U2 and not on the 646U.
7 *
8 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
10 *
11 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
f92d50e6 12 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4
LT		 13 */
14
1da177e4
LT		 15#include <linux/module.h>
16#include <linux/types.h>
17#include <linux/pci.h>
18#include <linux/delay.h>
19#include <linux/hdreg.h>
20#include <linux/ide.h>
21#include <linux/init.h>
22
23#include <asm/io.h>
24
25#define DISPLAY_CMD64X_TIMINGS
26
27#define CMD_DEBUG 0
28
29#if CMD_DEBUG
30#define cmdprintk(x...) printk(x)
31#else
32#define cmdprintk(x...)
33#endif
34
35/*
36 * CMD64x specific registers definition.
37 */
38#define CFR 0x50
e51e2528 39#define CFR_INTR_CH0 0x04
1da177e4 40#define CNTRL 0x51
5826b318
SS		 41#define CNTRL_ENA_1ST 0x04
42#define CNTRL_ENA_2ND 0x08
43#define CNTRL_DIS_RA0 0x40
44#define CNTRL_DIS_RA1 0x80
1da177e4
LT		 45
46#define CMDTIM 0x52
47#define ARTTIM0 0x53
48#define DRWTIM0 0x54
49#define ARTTIM1 0x55
50#define DRWTIM1 0x56
51#define ARTTIM23 0x57
52#define ARTTIM23_DIS_RA2 0x04
53#define ARTTIM23_DIS_RA3 0x08
54#define ARTTIM23_INTR_CH1 0x10
1da177e4
LT		 55#define DRWTIM2 0x58
56#define BRST 0x59
57#define DRWTIM3 0x5b
58
59#define BMIDECR0 0x70
60#define MRDMODE 0x71
61#define MRDMODE_INTR_CH0 0x04
62#define MRDMODE_INTR_CH1 0x08
63#define MRDMODE_BLK_CH0 0x10
64#define MRDMODE_BLK_CH1 0x20
65#define BMIDESR0 0x72
66#define UDIDETCR0 0x73
67#define DTPR0 0x74
68#define BMIDECR1 0x78
69#define BMIDECSR 0x79
70#define BMIDESR1 0x7A
71#define UDIDETCR1 0x7B
72#define DTPR1 0x7C
73
ecfd80e4 74#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
1da177e4
LT		 75#include <linux/stat.h>
76#include <linux/proc_fs.h>
77
78static u8 cmd64x_proc = 0;
79
80#define CMD_MAX_DEVS 5
81
82static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
83static int n_cmd_devs;
84
85static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
86{
87 char *p = buf;
1da177e4
LT		 88 u8 reg72 = 0, reg73 = 0; /* primary */
89 u8 reg7a = 0, reg7b = 0; /* secondary */
5826b318 90 u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */
1da177e4
LT		 91
92 p += sprintf(p, "\nController: %d\n", index);
5826b318
SS		 93 p += sprintf(p, "PCI-%x Chipset.\n", dev->device);
94
1da177e4 95 (void) pci_read_config_byte(dev, CFR, &reg50);
5826b318
SS		 96 (void) pci_read_config_byte(dev, CNTRL, &reg51);
97 (void) pci_read_config_byte(dev, ARTTIM23, &reg57);
1da177e4
LT		 98 (void) pci_read_config_byte(dev, MRDMODE, &reg71);
99 (void) pci_read_config_byte(dev, BMIDESR0, &reg72);
100 (void) pci_read_config_byte(dev, UDIDETCR0, &reg73);
101 (void) pci_read_config_byte(dev, BMIDESR1, &reg7a);
102 (void) pci_read_config_byte(dev, UDIDETCR1, &reg7b);
103
5826b318 104 /* PCI0643/6 originally didn't have the primary channel enable bit */
5826b318 105 if ((dev->device == PCI_DEVICE_ID_CMD_643) ||
44c10138 106 (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 3))
5826b318
SS		 107 reg51 |= CNTRL_ENA_1ST;
108
109 p += sprintf(p, "---------------- Primary Channel "
110 "---------------- Secondary Channel ------------\n");
111 p += sprintf(p, " %s %s\n",
112 (reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled",
113 (reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled");
114 p += sprintf(p, "---------------- drive0 --------- drive1 "
115 "-------- drive0 --------- drive1 ------\n");
116 p += sprintf(p, "DMA enabled: %s %s"
117 " %s %s\n",
118 (reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ",
119 (reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no ");
120 p += sprintf(p, "UltraDMA mode: %s (%c) %s (%c)",
121 ( reg73 & 0x01) ? " on" : "off",
122 ((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') :
123 ((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') :
124 ((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') :
125 ((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?',
126 ( reg73 & 0x02) ? " on" : "off",
127 ((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') :
128 ((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') :
129 ((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') :
130 ((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?');
131 p += sprintf(p, " %s (%c) %s (%c)\n",
132 ( reg7b & 0x01) ? " on" : "off",
133 ((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') :
134 ((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') :
135 ((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') :
136 ((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?',
137 ( reg7b & 0x02) ? " on" : "off",
138 ((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') :
139 ((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') :
140 ((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') :
141 ((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?');
142 p += sprintf(p, "Interrupt: %s, %s %s, %s\n",
143 (reg71 & MRDMODE_BLK_CH0 ) ? "blocked" : "enabled",
144 (reg50 & CFR_INTR_CH0 ) ? "pending" : "clear ",
145 (reg71 & MRDMODE_BLK_CH1 ) ? "blocked" : "enabled",
146 (reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear ");
1da177e4
LT		 147
148 return (char *)p;
149}
150
151static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
152{
153 char *p = buffer;
154 int i;
155
1da177e4
LT		 156 for (i = 0; i < n_cmd_devs; i++) {
157 struct pci_dev *dev = cmd_devs[i];
158 p = print_cmd64x_get_info(p, dev, i);
159 }
160 return p-buffer; /* => must be less than 4k! */
161}
162
ecfd80e4 163#endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
1da177e4 164
e277a1aa
SS		 165static u8 quantize_timing(int timing, int quant)
166{
167 return (timing + quant - 1) / quant;
168}
169
1da177e4 170/*
60e7a82f
SS		 171 * This routine calculates active/recovery counts and then writes them into
172 * the chipset registers.
1da177e4 173 */
60e7a82f 174static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
1da177e4 175{
60e7a82f
SS		 176 struct pci_dev *dev = HWIF(drive)->pci_dev;
177 int clock_time = 1000 / system_bus_clock();
178 u8 cycle_count, active_count, recovery_count, drwtim;
179 static const u8 recovery_values[] =
1da177e4 180 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
60e7a82f
SS		 181 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
182
183 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
184 cycle_time, active_time);
185
186 cycle_count = quantize_timing( cycle_time, clock_time);
187 active_count = quantize_timing(active_time, clock_time);
188 recovery_count = cycle_count - active_count;
189
1da177e4 190 /*
60e7a82f
SS		 191 * In case we've got too long recovery phase, try to lengthen
192 * the active phase
1da177e4 193 */
60e7a82f
SS		 194 if (recovery_count > 16) {
195 active_count += recovery_count - 16;
196 recovery_count = 16;
1da177e4 197 }
60e7a82f
SS		 198 if (active_count > 16) /* shouldn't actually happen... */
199 active_count = 16;
200
201 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
202 cycle_count, active_count, recovery_count);
1da177e4
LT		 203
204 /*
205 * Convert values to internal chipset representation
206 */
60e7a82f
SS		 207 recovery_count = recovery_values[recovery_count];
208 active_count &= 0x0f;
1da177e4 209
60e7a82f
SS		 210 /* Program the active/recovery counts into the DRWTIM register */
211 drwtim = (active_count << 4) | recovery_count;
212 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
213 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
1da177e4
LT		 214}
215
216/*
60e7a82f
SS		 217 * This routine selects drive's best PIO mode and writes into the chipset
218 * registers setup/active/recovery timings.
1da177e4 219 */
f92d50e6 220static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted)
1da177e4 221{
60e7a82f
SS		 222 ide_hwif_t *hwif = HWIF(drive);
223 struct pci_dev *dev = hwif->pci_dev;
e277a1aa 224 ide_pio_data_t pio;
60e7a82f
SS		 225 u8 pio_mode, setup_count, arttim = 0;
226 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
227 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
e277a1aa 228 pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio);
1da177e4 229
60e7a82f
SS		 230 cmdprintk("%s: PIO mode wanted %d, selected %d (%d ns)%s\n",
231 drive->name, mode_wanted, pio_mode, pio.cycle_time,
232 pio.overridden ? " (overriding vendor mode)" : "");
1da177e4 233
60e7a82f
SS		 234 program_cycle_times(drive, pio.cycle_time,
235 ide_pio_timings[pio_mode].active_time);
1da177e4 236
60e7a82f
SS		 237 setup_count = quantize_timing(ide_pio_timings[pio_mode].setup_time,
238 1000 / system_bus_clock());
239
240 /*
241 * The primary channel has individual address setup timing registers
242 * for each drive and the hardware selects the slowest timing itself.
243 * The secondary channel has one common register and we have to select
244 * the slowest address setup timing ourselves.
245 */
246 if (hwif->channel) {
247 ide_drive_t *drives = hwif->drives;
248
249 drive->drive_data = setup_count;
250 setup_count = max(drives[0].drive_data, drives[1].drive_data);
1da177e4 251 }
1da177e4 252
60e7a82f
SS		 253 if (setup_count > 5) /* shouldn't actually happen... */
254 setup_count = 5;
255 cmdprintk("Final address setup count: %d\n", setup_count);
1da177e4 256
60e7a82f
SS		 257 /*
258 * Program the address setup clocks into the ARTTIM registers.
259 * Avoid clearing the secondary channel's interrupt bit.
260 */
261 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
262 if (hwif->channel)
263 arttim &= ~ARTTIM23_INTR_CH1;
264 arttim &= ~0xc0;
265 arttim |= setup_values[setup_count];
266 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
267 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
f92d50e6
SS		 268
269 return pio_mode;
270}
271
272/*
273 * Attempts to set drive's PIO mode.
274 * Special cases are 8: prefetch off, 9: prefetch on (both never worked),
275 * and 255: auto-select best mode (used at boot time).
276 */
277static void cmd64x_tune_drive (ide_drive_t *drive, u8 pio)
278{
279 /*
280 * Filter out the prefetch control values
281 * to prevent PIO5 from being programmed
282 */
283 if (pio == 8 || pio == 9)
284 return;
285
286 pio = cmd64x_tune_pio(drive, pio);
287 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
1da177e4
LT		 288}
289
60e7a82f 290static int cmd64x_tune_chipset (ide_drive_t *drive, u8 speed)
1da177e4
LT		 291{
292 ide_hwif_t *hwif = HWIF(drive);
293 struct pci_dev *dev = hwif->pci_dev;
60e7a82f
SS		 294 u8 unit = drive->dn & 0x01;
295 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
1da177e4 296
2d5eaa6d 297 speed = ide_rate_filter(drive, speed);
1da177e4 298
f92d50e6 299 if (speed >= XFER_SW_DMA_0) {
1da177e4 300 (void) pci_read_config_byte(dev, pciU, &regU);
1da177e4 301 regU &= ~(unit ? 0xCA : 0x35);
1da177e4
LT		 302 }
303
304 switch(speed) {
60e7a82f
SS		 305 case XFER_UDMA_5:
306 regU |= unit ? 0x0A : 0x05;
307 break;
308 case XFER_UDMA_4:
309 regU |= unit ? 0x4A : 0x15;
310 break;
311 case XFER_UDMA_3:
312 regU |= unit ? 0x8A : 0x25;
313 break;
314 case XFER_UDMA_2:
315 regU |= unit ? 0x42 : 0x11;
316 break;
317 case XFER_UDMA_1:
318 regU |= unit ? 0x82 : 0x21;
319 break;
320 case XFER_UDMA_0:
321 regU |= unit ? 0xC2 : 0x31;
322 break;
323 case XFER_MW_DMA_2:
324 program_cycle_times(drive, 120, 70);
325 break;
326 case XFER_MW_DMA_1:
327 program_cycle_times(drive, 150, 80);
328 break;
329 case XFER_MW_DMA_0:
330 program_cycle_times(drive, 480, 215);
331 break;
332 case XFER_PIO_5:
333 case XFER_PIO_4:
334 case XFER_PIO_3:
335 case XFER_PIO_2:
336 case XFER_PIO_1:
337 case XFER_PIO_0:
338 (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0);
339 break;
340 default:
341 return 1;
1da177e4
LT		 342 }
343
60e7a82f 344 if (speed >= XFER_SW_DMA_0)
1da177e4 345 (void) pci_write_config_byte(dev, pciU, regU);
1da177e4 346
60e7a82f 347 return ide_config_drive_speed(drive, speed);
1da177e4
LT		 348}
349
1da177e4
LT		 350static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
351{
4728d546 352 if (ide_tune_dma(drive))
3608b5d7 353 return 0;
1da177e4 354
d8f4469d 355 if (ide_use_fast_pio(drive))
f92d50e6 356 cmd64x_tune_drive(drive, 255);
d8f4469d 357
3608b5d7 358 return -1;
1da177e4
LT		 359}
360
66602c83 361static int cmd648_ide_dma_end (ide_drive_t *drive)
1da177e4 362{
66602c83
SS		 363 ide_hwif_t *hwif = HWIF(drive);
364 int err = __ide_dma_end(drive);
365 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
366 MRDMODE_INTR_CH0;
367 u8 mrdmode = inb(hwif->dma_master + 0x01);
368
369 /* clear the interrupt bit */
370 outb(mrdmode | irq_mask, hwif->dma_master + 0x01);
371
372 return err;
1da177e4
LT		 373}
374
375static int cmd64x_ide_dma_end (ide_drive_t *drive)
376{
1da177e4
LT		 377 ide_hwif_t *hwif = HWIF(drive);
378 struct pci_dev *dev = hwif->pci_dev;
66602c83
SS		 379 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
380 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
381 CFR_INTR_CH0;
382 u8 irq_stat = 0;
383 int err = __ide_dma_end(drive);
1da177e4 384
66602c83
SS		 385 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
386 /* clear the interrupt bit */
387 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
388
389 return err;
390}
391
392static int cmd648_ide_dma_test_irq (ide_drive_t *drive)
393{
394 ide_hwif_t *hwif = HWIF(drive);
395 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
396 MRDMODE_INTR_CH0;
397 u8 dma_stat = inb(hwif->dma_status);
398 u8 mrdmode = inb(hwif->dma_master + 0x01);
399
400#ifdef DEBUG
401 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
402 drive->name, dma_stat, mrdmode, irq_mask);
403#endif
404 if (!(mrdmode & irq_mask))
405 return 0;
406
407 /* return 1 if INTR asserted */
408 if (dma_stat & 4)
409 return 1;
410
411 return 0;
1da177e4
LT		 412}
413
414static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
415{
e51e2528
SS		 416 ide_hwif_t *hwif = HWIF(drive);
417 struct pci_dev *dev = hwif->pci_dev;
66602c83
SS		 418 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
419 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
420 CFR_INTR_CH0;
421 u8 dma_stat = inb(hwif->dma_status);
422 u8 irq_stat = 0;
e51e2528
SS		 423
424 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
1da177e4 425
1da177e4 426#ifdef DEBUG
66602c83
SS		 427 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
428 drive->name, dma_stat, irq_stat, irq_mask);
1da177e4 429#endif
66602c83 430 if (!(irq_stat & irq_mask))
1da177e4
LT		 431 return 0;
432
433 /* return 1 if INTR asserted */
66602c83 434 if (dma_stat & 4)
1da177e4
LT		 435 return 1;
436
437 return 0;
438}
439
440/*
441 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
442 * event order for DMA transfers.
443 */
444
445static int cmd646_1_ide_dma_end (ide_drive_t *drive)
446{
447 ide_hwif_t *hwif = HWIF(drive);
448 u8 dma_stat = 0, dma_cmd = 0;
449
450 drive->waiting_for_dma = 0;
451 /* get DMA status */
0ecdca26 452 dma_stat = inb(hwif->dma_status);
1da177e4 453 /* read DMA command state */
0ecdca26 454 dma_cmd = inb(hwif->dma_command);
1da177e4 455 /* stop DMA */
0ecdca26 456 outb(dma_cmd & ~1, hwif->dma_command);
1da177e4 457 /* clear the INTR & ERROR bits */
0ecdca26 458 outb(dma_stat | 6, hwif->dma_status);
1da177e4
LT		 459 /* and free any DMA resources */
460 ide_destroy_dmatable(drive);
461 /* verify good DMA status */
462 return (dma_stat & 7) != 4;
463}
464
465static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
466{
1da177e4
LT		 467 u8 mrdmode = 0;
468
83a6d4ab
SS		 469 if (dev->device == PCI_DEVICE_ID_CMD_646) {
470 u8 rev = 0;
1da177e4 471
83a6d4ab
SS		 472 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
473
474 switch (rev) {
475 case 0x07:
476 case 0x05:
477 printk("%s: UltraDMA capable", name);
1da177e4 478 break;
83a6d4ab 479 case 0x03:
1da177e4 480 default:
83a6d4ab
SS		 481 printk("%s: MultiWord DMA force limited", name);
482 break;
483 case 0x01:
484 printk("%s: MultiWord DMA limited, "
485 "IRQ workaround enabled\n", name);
1da177e4 486 break;
83a6d4ab 487 }
1da177e4
LT		 488 }
489
490 /* Set a good latency timer and cache line size value. */
491 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
492 /* FIXME: pci_set_master() to ensure a good latency timer value */
493
83a6d4ab
SS		 494 /*
495 * Enable interrupts, select MEMORY READ LINE for reads.
496 *
497 * NOTE: although not mentioned in the PCI0646U specs,
498 * bits 0-1 are write only and won't be read back as
499 * set or not -- PCI0646U2 specs clarify this point.
1da177e4 500 */
83a6d4ab
SS		 501 (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
502 mrdmode &= ~0x30;
503 (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
1da177e4 504
ecfd80e4 505#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
1da177e4
LT		 506
507 cmd_devs[n_cmd_devs++] = dev;
508
509 if (!cmd64x_proc) {
510 cmd64x_proc = 1;
511 ide_pci_create_host_proc("cmd64x", cmd64x_get_info);
512 }
ecfd80e4 513#endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_IDE_PROC_FS */
1da177e4
LT		 514
515 return 0;
516}
517
49521f97 518static u8 __devinit ata66_cmd64x(ide_hwif_t *hwif)
1da177e4 519{
83a6d4ab
SS		 520 struct pci_dev *dev = hwif->pci_dev;
521 u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
1da177e4 522
83a6d4ab
SS		 523 switch (dev->device) {
524 case PCI_DEVICE_ID_CMD_648:
525 case PCI_DEVICE_ID_CMD_649:
526 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
49521f97 527 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
83a6d4ab 528 default:
49521f97 529 return ATA_CBL_PATA40;
1da177e4 530 }
1da177e4
LT		 531}
532
533static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
534{
535 struct pci_dev *dev = hwif->pci_dev;
83a6d4ab 536 u8 rev = 0;
1da177e4 537
83a6d4ab 538 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1da177e4 539
f92d50e6 540 hwif->tuneproc = &cmd64x_tune_drive;
1da177e4
LT		 541 hwif->speedproc = &cmd64x_tune_chipset;
542
f92d50e6
SS		 543 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
544
545 if (!hwif->dma_base)
1da177e4 546 return;
1da177e4 547
83a6d4ab
SS		 548 hwif->atapi_dma = 1;
549 hwif->mwdma_mask = 0x07;
18137207
BZ		 550 hwif->ultra_mask = hwif->cds->udma_mask;
551
2d5eaa6d
BZ		 552 /*
553 * UltraDMA only supported on PCI646U and PCI646U2, which
554 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
555 * Actually, although the CMD tech support people won't
556 * tell me the details, the 0x03 revision cannot support
557 * UDMA correctly without hardware modifications, and even
558 * then it only works with Quantum disks due to some
559 * hold time assumptions in the 646U part which are fixed
560 * in the 646U2.
561 *
562 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
563 */
83a6d4ab 564 if (dev->device == PCI_DEVICE_ID_CMD_646 && rev < 5)
18137207 565 hwif->ultra_mask = 0x00;
1da177e4 566
1da177e4 567 hwif->ide_dma_check = &cmd64x_config_drive_for_dma;
83a6d4ab 568
49521f97
BZ		 569 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
570 hwif->cbl = ata66_cmd64x(hwif);
1da177e4 571
83a6d4ab 572 switch (dev->device) {
66602c83
SS		 573 case PCI_DEVICE_ID_CMD_648:
574 case PCI_DEVICE_ID_CMD_649:
575 alt_irq_bits:
576 hwif->ide_dma_end = &cmd648_ide_dma_end;
577 hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq;
578 break;
579 case PCI_DEVICE_ID_CMD_646:
1da177e4 580 hwif->chipset = ide_cmd646;
83a6d4ab 581 if (rev == 0x01) {
1da177e4 582 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
66602c83 583 break;
83a6d4ab 584 } else if (rev >= 0x03)
66602c83
SS		 585 goto alt_irq_bits;
586 /* fall thru */
587 default:
588 hwif->ide_dma_end = &cmd64x_ide_dma_end;
589 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
590 break;
1da177e4
LT		 591 }
592
1da177e4
LT		 593 if (!noautodma)
594 hwif->autodma = 1;
83a6d4ab 595 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1da177e4
LT		 596}
597
7accbffd
SS		 598static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d)
599{
600 return ide_setup_pci_device(dev, d);
601}
602
603static int __devinit init_setup_cmd646(struct pci_dev *dev, ide_pci_device_t *d)
604{
7accbffd
SS		 605 /*
606 * The original PCI0646 didn't have the primary channel enable bit,
607 * it appeared starting with PCI0646U (i.e. revision ID 3).
608 */
44c10138 609 if (dev->revision < 3)
7accbffd
SS		 610 d->enablebits[0].reg = 0;
611
612 return ide_setup_pci_device(dev, d);
613}
614
1da177e4
LT		 615static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
616 { /* 0 */
617 .name = "CMD643",
7accbffd 618 .init_setup = init_setup_cmd64x,
1da177e4
LT		 619 .init_chipset = init_chipset_cmd64x,
620 .init_hwif = init_hwif_cmd64x,
621 .channels = 2,
622 .autodma = AUTODMA,
7accbffd 623 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
1da177e4 624 .bootable = ON_BOARD,
18137207 625 .udma_mask = 0x00, /* no udma */
1da177e4
LT		 626 },{ /* 1 */
627 .name = "CMD646",
7accbffd 628 .init_setup = init_setup_cmd646,
1da177e4
LT		 629 .init_chipset = init_chipset_cmd64x,
630 .init_hwif = init_hwif_cmd64x,
631 .channels = 2,
632 .autodma = AUTODMA,
7accbffd 633 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
1da177e4 634 .bootable = ON_BOARD,
18137207 635 .udma_mask = 0x07, /* udma0-2 */
1da177e4
LT		 636 },{ /* 2 */
637 .name = "CMD648",
7accbffd 638 .init_setup = init_setup_cmd64x,
1da177e4
LT		 639 .init_chipset = init_chipset_cmd64x,
640 .init_hwif = init_hwif_cmd64x,
641 .channels = 2,
642 .autodma = AUTODMA,
7accbffd 643 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
1da177e4 644 .bootable = ON_BOARD,
18137207 645 .udma_mask = 0x1f, /* udma0-4 */
1da177e4
LT		 646 },{ /* 3 */
647 .name = "CMD649",
7accbffd 648 .init_setup = init_setup_cmd64x,
1da177e4
LT		 649 .init_chipset = init_chipset_cmd64x,
650 .init_hwif = init_hwif_cmd64x,
651 .channels = 2,
652 .autodma = AUTODMA,
7accbffd 653 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
1da177e4 654 .bootable = ON_BOARD,
18137207 655 .udma_mask = 0x3f, /* udma0-5 */
1da177e4
LT		 656 }
657};
658
7accbffd
SS		 659/*
660 * We may have to modify enablebits for PCI0646, so we'd better pass
661 * a local copy of the ide_pci_device_t structure down the call chain...
662 */
1da177e4
LT		 663static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
664{
7accbffd
SS		 665 ide_pci_device_t d = cmd64x_chipsets[id->driver_data];
666
667 return d.init_setup(dev, &d);
1da177e4
LT		 668}
669
670static struct pci_device_id cmd64x_pci_tbl[] = {
671 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
672 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
673 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
674 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
675 { 0, },
676};
677MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
678
679static struct pci_driver driver = {
680 .name = "CMD64x_IDE",
681 .id_table = cmd64x_pci_tbl,
682 .probe = cmd64x_init_one,
683};
684
82ab1eec 685static int __init cmd64x_ide_init(void)
1da177e4
LT		 686{
687 return ide_pci_register_driver(&driver);
688}
689
690module_init(cmd64x_ide_init);
691
692MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
693MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
694MODULE_LICENSE("GPL");