[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / amd74xx.c

/*
 * Version 2.25
 *
 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
 * IDE driver for Linux.
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
 *
 * Based on the work of:
 *      Andre Hedrick
 */

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>
#include <asm/io.h>

#include "ide-timing.h"

enum {
	AMD_IDE_CONFIG		= 0x41,
	AMD_CABLE_DETECT	= 0x42,
	AMD_DRIVE_TIMING	= 0x48,
	AMD_8BIT_TIMING		= 0x4e,
	AMD_ADDRESS_SETUP	= 0x4c,
	AMD_UDMA_TIMING		= 0x50,
};

static unsigned int amd_80w;
static unsigned int amd_clock;

static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };

static inline u8 amd_offset(struct pci_dev *dev)
{
	return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0;
}

/*
 * amd_set_speed() writes timing values to the chipset registers
 */

static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,
			  struct ide_timing *timing)
{
	u8 t = 0, offset = amd_offset(dev);

	pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t);
	t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
	pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t);

	pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)),
		((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));

	pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn),
		((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));

	switch (udma_mask) {
	case ATA_UDMA2: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
	case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
	case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break;
	default: return;
	}

	pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + (3 - dn), t);
}

/*
 * amd_set_drive() computes timing values and configures the chipset
 * to a desired transfer mode.  It also can be called by upper layers.
 */

static void amd_set_drive(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif = drive->hwif;
	ide_drive_t *peer = hwif->drives + (~drive->dn & 1);
	struct ide_timing t, p;
	int T, UT;
	u8 udma_mask = hwif->ultra_mask;

	T = 1000000000 / amd_clock;
	UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);

	ide_timing_compute(drive, speed, &t, T, UT);

	if (peer->present) {
		ide_timing_compute(peer, peer->current_speed, &p, T, UT);
		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	}

	if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
	if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;

	amd_set_speed(hwif->pci_dev, drive->dn, udma_mask, &t);
}

/*
 * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
 */

static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	amd_set_drive(drive, XFER_PIO_0 + pio);
}

static void __devinit amd7409_cable_detect(struct pci_dev *dev,
					   const char *name)
{
	/* no host side cable detection */
	amd_80w = 0x03;
}

static void __devinit amd7411_cable_detect(struct pci_dev *dev,
					   const char *name)
{
	int i;
	u32 u = 0;
	u8 t = 0, offset = amd_offset(dev);

	pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t);
	pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u);
	amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
	for (i = 24; i >= 0; i -= 8)
		if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
			printk(KERN_WARNING "%s: BIOS didn't set cable bits "
					    "correctly. Enabling workaround.\n",
					    name);
			amd_80w |= (1 << (1 - (i >> 4)));
		}
}

/*
 * The initialization callback.  Initialize drive independent registers.
 */

static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev,
						   const char *name)
{
	u8 t = 0, offset = amd_offset(dev);

/*
 * Check 80-wire cable presence.
 */

	if (dev->vendor == PCI_VENDOR_ID_AMD &&
	    dev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
		; /* no UDMA > 2 */
	else if (dev->vendor == PCI_VENDOR_ID_AMD &&
		 dev->device == PCI_DEVICE_ID_AMD_VIPER_7409)
		amd7409_cable_detect(dev, name);
	else
		amd7411_cable_detect(dev, name);

/*
 * Take care of prefetch & postwrite.
 */

	pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t);
	/*
	 * Check for broken FIFO support.
	 */
	if (dev->vendor == PCI_VENDOR_ID_AMD &&
	    dev->vendor == PCI_DEVICE_ID_AMD_VIPER_7411)
		t &= 0x0f;
	else
		t |= 0xf0;
	pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t);

/*
 * Determine the system bus clock.
 */

	amd_clock = system_bus_clock() * 1000;

	switch (amd_clock) {
		case 33000: amd_clock = 33333; break;
		case 37000: amd_clock = 37500; break;
		case 41000: amd_clock = 41666; break;
	}

	if (amd_clock < 20000 || amd_clock > 50000) {
		printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
				    name, amd_clock);
		amd_clock = 33333;
	}

	return dev->irq;
}

static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
{
	if (hwif->irq == 0) /* 0 is bogus but will do for now */
		hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel);

	hwif->set_pio_mode = &amd_set_pio_mode;
	hwif->set_dma_mode = &amd_set_drive;

	if (!hwif->dma_base)
		return;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
		if ((amd_80w >> hwif->channel) & 1)
			hwif->cbl = ATA_CBL_PATA80;
		else
			hwif->cbl = ATA_CBL_PATA40;
	}
}

#define IDE_HFLAGS_AMD \
	(IDE_HFLAG_PIO_NO_BLACKLIST | \
	 IDE_HFLAG_PIO_NO_DOWNGRADE | \
	 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
	 IDE_HFLAG_POST_SET_MODE | \
	 IDE_HFLAG_IO_32BIT | \
	 IDE_HFLAG_UNMASK_IRQS | \
	 IDE_HFLAG_BOOTABLE)

#define DECLARE_AMD_DEV(name_str, swdma, udma)				\
	{								\
		.name		= name_str,				\
		.init_chipset	= init_chipset_amd74xx,			\
		.init_hwif	= init_hwif_amd74xx,			\
		.enablebits	= {{0x40,0x02,0x02}, {0x40,0x01,0x01}},	\
		.host_flags	= IDE_HFLAGS_AMD,			\
		.pio_mask	= ATA_PIO5,				\
		.swdma_mask	= swdma,				\
		.mwdma_mask	= ATA_MWDMA2,				\
		.udma_mask	= udma,					\
	}

#define DECLARE_NV_DEV(name_str, udma)					\
	{								\
		.name		= name_str,				\
		.init_chipset	= init_chipset_amd74xx,			\
		.init_hwif	= init_hwif_amd74xx,			\
		.enablebits	= {{0x50,0x02,0x02}, {0x50,0x01,0x01}},	\
		.host_flags	= IDE_HFLAGS_AMD,			\
		.pio_mask	= ATA_PIO5,				\
		.swdma_mask	= ATA_SWDMA2,				\
		.mwdma_mask	= ATA_MWDMA2,				\
		.udma_mask	= udma,					\
	}

static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
	/*  0 */ DECLARE_AMD_DEV("AMD7401",	  0x00, ATA_UDMA2),
	/*  1 */ DECLARE_AMD_DEV("AMD7409", ATA_SWDMA2, ATA_UDMA4),
	/*  2 */ DECLARE_AMD_DEV("AMD7411", ATA_SWDMA2, ATA_UDMA5),
	/*  3 */ DECLARE_AMD_DEV("AMD7441", ATA_SWDMA2, ATA_UDMA5),
	/*  4 */ DECLARE_AMD_DEV("AMD8111", ATA_SWDMA2, ATA_UDMA6),

	/*  5 */ DECLARE_NV_DEV("NFORCE",		ATA_UDMA5),
	/*  6 */ DECLARE_NV_DEV("NFORCE2",		ATA_UDMA6),
	/*  7 */ DECLARE_NV_DEV("NFORCE2-U400R",	ATA_UDMA6),
	/*  8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA",	ATA_UDMA6),
	/*  9 */ DECLARE_NV_DEV("NFORCE3-150",		ATA_UDMA6),
	/* 10 */ DECLARE_NV_DEV("NFORCE3-250",		ATA_UDMA6),
	/* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA",	ATA_UDMA6),
	/* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2",	ATA_UDMA6),
	/* 13 */ DECLARE_NV_DEV("NFORCE-CK804",		ATA_UDMA6),
	/* 14 */ DECLARE_NV_DEV("NFORCE-MCP04",		ATA_UDMA6),
	/* 15 */ DECLARE_NV_DEV("NFORCE-MCP51",		ATA_UDMA6),
	/* 16 */ DECLARE_NV_DEV("NFORCE-MCP55",		ATA_UDMA6),
	/* 17 */ DECLARE_NV_DEV("NFORCE-MCP61",		ATA_UDMA6),
	/* 18 */ DECLARE_NV_DEV("NFORCE-MCP65",		ATA_UDMA6),
	/* 19 */ DECLARE_NV_DEV("NFORCE-MCP67",		ATA_UDMA6),
	/* 20 */ DECLARE_NV_DEV("NFORCE-MCP73",		ATA_UDMA6),
	/* 21 */ DECLARE_NV_DEV("NFORCE-MCP77",		ATA_UDMA6),

	/* 22 */ DECLARE_AMD_DEV("AMD5536", ATA_SWDMA2, ATA_UDMA5),
};

static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d;
	u8 idx = id->driver_data;

	d = amd74xx_chipsets[idx];

	/*
	 * Check for bad SWDMA and incorrectly wired Serenade mainboards.
	 */
	if (idx == 1) {
		if (dev->revision <= 7)
			d.swdma_mask = 0;
	} else if (idx == 4) {
		if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
		    dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
			d.udma_mask = ATA_UDMA5;
	}

	printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n",
			 d.name, pci_name(dev), dev->revision,
			 amd_dma[fls(d.udma_mask) - 1]);

	return ide_setup_pci_device(dev, &d);
}

static const struct pci_device_id amd74xx_pci_tbl[] = {
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_COBRA_7401),		 0 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7409),		 1 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7411),		 2 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_OPUS_7441),		 3 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_8111_IDE),		 4 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_IDE),	 5 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE),	 6 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE),	 7 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA),	 8 },
#endif
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE),	 9 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE),	10 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA),	11 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2),	12 },
#endif
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE),	13 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE),	14 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE),	15 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE),	16 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE),	17 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE),	18 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE),	19 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE),	20 },
	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE),	21 },
	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_CS5536_IDE),		22 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);

static struct pci_driver driver = {
	.name		= "AMD_IDE",
	.id_table	= amd74xx_pci_tbl,
	.probe		= amd74xx_probe,
};

static int __init amd74xx_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(amd74xx_ide_init);

MODULE_AUTHOR("Vojtech Pavlik");
MODULE_DESCRIPTION("AMD PCI IDE driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
993da8f9	2	* Version 2.25
1da177e4 LT	3	*
	4	* AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
	5	* IDE driver for Linux.
	6	*
	7	* Copyright (c) 2000-2002 Vojtech Pavlik
75b1d975	8	* Copyright (c) 2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	9	*
	10	* Based on the work of:
	11	* Andre Hedrick
	12	*/
	13
	14	/*
	15	* This program is free software; you can redistribute it and/or modify it
	16	* under the terms of the GNU General Public License version 2 as published by
	17	* the Free Software Foundation.
	18	*/
	19
1da177e4 LT	20	#include <linux/module.h>
	21	#include <linux/kernel.h>
	22	#include <linux/ioport.h>
	23	#include <linux/blkdev.h>
	24	#include <linux/pci.h>
	25	#include <linux/init.h>
	26	#include <linux/ide.h>
	27	#include <asm/io.h>
	28
	29	#include "ide-timing.h"
	30
993da8f9 BZ	31	enum {
	32	AMD_IDE_CONFIG = 0x41,
	33	AMD_CABLE_DETECT = 0x42,
	34	AMD_DRIVE_TIMING = 0x48,
	35	AMD_8BIT_TIMING = 0x4e,
	36	AMD_ADDRESS_SETUP = 0x4c,
	37	AMD_UDMA_TIMING = 0x50,
1da177e4 LT	38	};
1da177e4 LT	39
1da177e4 LT	40	static unsigned int amd_80w;
	41	static unsigned int amd_clock;
	42
75b1d975	43	static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
1da177e4 LT	44	static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
1da177e4 LT	45
993da8f9 BZ	46	static inline u8 amd_offset(struct pci_dev *dev)
	47	{
	48	return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0;
	49	}
	50
1da177e4 LT	51	/*
	52	* amd_set_speed() writes timing values to the chipset registers
	53	*/
	54
993da8f9 BZ	55	static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,
993da8f9 BZ	56	struct ide_timing *timing)
1da177e4	57	{
993da8f9	58	u8 t = 0, offset = amd_offset(dev);
1da177e4	59
993da8f9	60	pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t);
1da177e4	61	t = (t & ~(3 << ((3 - dn) << 1))) \| ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
993da8f9	62	pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t);
1da177e4	63
993da8f9	64	pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)),
1da177e4 LT	65	((FIT(timing->act8b, 1, 16) - 1) << 4) \| (FIT(timing->rec8b, 1, 16) - 1));
1da177e4 LT	66
993da8f9	67	pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn),
1da177e4 LT	68	((FIT(timing->active, 1, 16) - 1) << 4) \| (FIT(timing->recover, 1, 16) - 1));
1da177e4 LT	69
993da8f9	70	switch (udma_mask) {
75b1d975 BZ	71	case ATA_UDMA2: t = timing->udma ? (0xc0 \| (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
	72	case ATA_UDMA4: t = timing->udma ? (0xc0 \| amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
	73	case ATA_UDMA5: t = timing->udma ? (0xc0 \| amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
	74	case ATA_UDMA6: t = timing->udma ? (0xc0 \| amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break;
	75	default: return;
1da177e4 LT	76	}
1da177e4 LT	77
993da8f9	78	pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + (3 - dn), t);
1da177e4 LT	79	}
	80
	81	/*
88b2b32b BZ	82	* amd_set_drive() computes timing values and configures the chipset
88b2b32b BZ	83	* to a desired transfer mode. It also can be called by upper layers.
1da177e4 LT	84	*/
1da177e4 LT	85
88b2b32b	86	static void amd_set_drive(ide_drive_t *drive, const u8 speed)
1da177e4	87	{
993da8f9 BZ	88	ide_hwif_t *hwif = drive->hwif;
993da8f9 BZ	89	ide_drive_t *peer = hwif->drives + (~drive->dn & 1);
1da177e4 LT	90	struct ide_timing t, p;
1da177e4 LT	91	int T, UT;
993da8f9	92	u8 udma_mask = hwif->ultra_mask;
1da177e4	93
1da177e4	94	T = 1000000000 / amd_clock;
993da8f9	95	UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);
1da177e4 LT	96
	97	ide_timing_compute(drive, speed, &t, T, UT);
	98
	99	if (peer->present) {
	100	ide_timing_compute(peer, peer->current_speed, &p, T, UT);
	101	ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
	102	}
	103
	104	if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
	105	if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
	106
993da8f9	107	amd_set_speed(hwif->pci_dev, drive->dn, udma_mask, &t);
1da177e4 LT	108	}
	109
	110	/*
26bcb879	111	* amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
1da177e4 LT	112	*/
1da177e4 LT	113
26bcb879	114	static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	115	{
26bcb879	116	amd_set_drive(drive, XFER_PIO_0 + pio);
1da177e4 LT	117	}
1da177e4 LT	118
993da8f9 BZ	119	static void __devinit amd7409_cable_detect(struct pci_dev *dev,
	120	const char *name)
	121	{
	122	/* no host side cable detection */
	123	amd_80w = 0x03;
	124	}
1da177e4	125
993da8f9 BZ	126	static void __devinit amd7411_cable_detect(struct pci_dev *dev,
993da8f9 BZ	127	const char *name)
1da177e4	128	{
1da177e4	129	int i;
993da8f9 BZ	130	u32 u = 0;
	131	u8 t = 0, offset = amd_offset(dev);
	132
	133	pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t);
	134	pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u);
	135	amd_80w = ((t & 0x3) ? 1 : 0) \| ((t & 0xc) ? 2 : 0);
	136	for (i = 24; i >= 0; i -= 8)
	137	if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
	138	printk(KERN_WARNING "%s: BIOS didn't set cable bits "
	139	"correctly. Enabling workaround.\n",
	140	name);
	141	amd_80w \|= (1 << (1 - (i >> 4)));
	142	}
	143	}
1da177e4 LT	144
1da177e4 LT	145	/*
993da8f9	146	* The initialization callback. Initialize drive independent registers.
1da177e4 LT	147	*/
1da177e4 LT	148
993da8f9 BZ	149	static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev,
	150	const char *name)
	151	{
	152	u8 t = 0, offset = amd_offset(dev);
1da177e4 LT	153
	154	/*
	155	* Check 80-wire cable presence.
	156	*/
	157
993da8f9 BZ	158	if (dev->vendor == PCI_VENDOR_ID_AMD &&
	159	dev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
	160	; /* no UDMA > 2 */
	161	else if (dev->vendor == PCI_VENDOR_ID_AMD &&
	162	dev->device == PCI_DEVICE_ID_AMD_VIPER_7409)
	163	amd7409_cable_detect(dev, name);
	164	else
	165	amd7411_cable_detect(dev, name);
1da177e4 LT	166
	167	/*
	168	* Take care of prefetch & postwrite.
	169	*/
	170
993da8f9 BZ	171	pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t);
	172	/*
	173	* Check for broken FIFO support.
	174	*/
	175	if (dev->vendor == PCI_VENDOR_ID_AMD &&
	176	dev->vendor == PCI_DEVICE_ID_AMD_VIPER_7411)
	177	t &= 0x0f;
	178	else
	179	t \|= 0xf0;
	180	pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t);
1da177e4 LT	181
	182	/*
	183	* Determine the system bus clock.
	184	*/
	185
	186	amd_clock = system_bus_clock() * 1000;
	187
	188	switch (amd_clock) {
	189	case 33000: amd_clock = 33333; break;
	190	case 37000: amd_clock = 37500; break;
	191	case 41000: amd_clock = 41666; break;
	192	}
	193
	194	if (amd_clock < 20000 \|\| amd_clock > 50000) {
	195	printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
993da8f9	196	name, amd_clock);
1da177e4 LT	197	amd_clock = 33333;
	198	}
	199
1da177e4 LT	200	return dev->irq;
	201	}
	202
e895f926	203	static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
1da177e4	204	{
1da177e4 LT	205	if (hwif->irq == 0) /* 0 is bogus but will do for now */
	206	hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel);
	207
26bcb879	208	hwif->set_pio_mode = &amd_set_pio_mode;
88b2b32b	209	hwif->set_dma_mode = &amd_set_drive;
1da177e4	210
1da177e4 LT	211	if (!hwif->dma_base)
	212	return;
	213
49521f97 BZ	214	if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
	215	if ((amd_80w >> hwif->channel) & 1)
	216	hwif->cbl = ATA_CBL_PATA80;
	217	else
	218	hwif->cbl = ATA_CBL_PATA40;
	219	}
1da177e4 LT	220	}
1da177e4 LT	221
caea7602 BZ	222	#define IDE_HFLAGS_AMD \
	223	(IDE_HFLAG_PIO_NO_BLACKLIST \| \
	224	IDE_HFLAG_PIO_NO_DOWNGRADE \| \
4db90a14	225	IDE_HFLAG_ABUSE_SET_DMA_MODE \| \
caea7602 BZ	226	IDE_HFLAG_POST_SET_MODE \| \
	227	IDE_HFLAG_IO_32BIT \| \
	228	IDE_HFLAG_UNMASK_IRQS \| \
	229	IDE_HFLAG_BOOTABLE)
	230
993da8f9	231	#define DECLARE_AMD_DEV(name_str, swdma, udma) \
1da177e4 LT	232	{ \
	233	.name = name_str, \
	234	.init_chipset = init_chipset_amd74xx, \
	235	.init_hwif = init_hwif_amd74xx, \
1da177e4	236	.enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
caea7602	237	.host_flags = IDE_HFLAGS_AMD, \
4099d143	238	.pio_mask = ATA_PIO5, \
993da8f9	239	.swdma_mask = swdma, \
5f8b6c34	240	.mwdma_mask = ATA_MWDMA2, \
993da8f9	241	.udma_mask = udma, \
1da177e4 LT	242	}
1da177e4 LT	243
993da8f9	244	#define DECLARE_NV_DEV(name_str, udma) \
1da177e4 LT	245	{ \
	246	.name = name_str, \
	247	.init_chipset = init_chipset_amd74xx, \
	248	.init_hwif = init_hwif_amd74xx, \
1da177e4	249	.enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
caea7602	250	.host_flags = IDE_HFLAGS_AMD, \
4099d143	251	.pio_mask = ATA_PIO5, \
5f8b6c34 BZ	252	.swdma_mask = ATA_SWDMA2, \
5f8b6c34 BZ	253	.mwdma_mask = ATA_MWDMA2, \
993da8f9	254	.udma_mask = udma, \
1da177e4 LT	255	}
1da177e4 LT	256
85620436	257	static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
993da8f9 BZ	258	/* 0 */ DECLARE_AMD_DEV("AMD7401", 0x00, ATA_UDMA2),
	259	/* 1 */ DECLARE_AMD_DEV("AMD7409", ATA_SWDMA2, ATA_UDMA4),
	260	/* 2 */ DECLARE_AMD_DEV("AMD7411", ATA_SWDMA2, ATA_UDMA5),
	261	/* 3 */ DECLARE_AMD_DEV("AMD7441", ATA_SWDMA2, ATA_UDMA5),
	262	/* 4 */ DECLARE_AMD_DEV("AMD8111", ATA_SWDMA2, ATA_UDMA6),
	263
	264	/* 5 */ DECLARE_NV_DEV("NFORCE", ATA_UDMA5),
	265	/* 6 */ DECLARE_NV_DEV("NFORCE2", ATA_UDMA6),
	266	/* 7 */ DECLARE_NV_DEV("NFORCE2-U400R", ATA_UDMA6),
	267	/* 8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA", ATA_UDMA6),
	268	/* 9 */ DECLARE_NV_DEV("NFORCE3-150", ATA_UDMA6),
	269	/* 10 */ DECLARE_NV_DEV("NFORCE3-250", ATA_UDMA6),
	270	/* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA", ATA_UDMA6),
	271	/* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2", ATA_UDMA6),
	272	/* 13 */ DECLARE_NV_DEV("NFORCE-CK804", ATA_UDMA6),
	273	/* 14 */ DECLARE_NV_DEV("NFORCE-MCP04", ATA_UDMA6),
	274	/* 15 */ DECLARE_NV_DEV("NFORCE-MCP51", ATA_UDMA6),
	275	/* 16 */ DECLARE_NV_DEV("NFORCE-MCP55", ATA_UDMA6),
	276	/* 17 */ DECLARE_NV_DEV("NFORCE-MCP61", ATA_UDMA6),
	277	/* 18 */ DECLARE_NV_DEV("NFORCE-MCP65", ATA_UDMA6),
	278	/* 19 */ DECLARE_NV_DEV("NFORCE-MCP67", ATA_UDMA6),
	279	/* 20 */ DECLARE_NV_DEV("NFORCE-MCP73", ATA_UDMA6),
	280	/* 21 */ DECLARE_NV_DEV("NFORCE-MCP77", ATA_UDMA6),
	281
	282	/* 22 */ DECLARE_AMD_DEV("AMD5536", ATA_SWDMA2, ATA_UDMA5),
1da177e4 LT	283	};
	284
	285	static int __devinit amd74xx_probe(struct pci_dev dev, const struct pci_device_id id)
	286	{
993da8f9 BZ	287	struct ide_port_info d;
	288	u8 idx = id->driver_data;
	289
	290	d = amd74xx_chipsets[idx];
	291
	292	/*
	293	* Check for bad SWDMA and incorrectly wired Serenade mainboards.
	294	*/
	295	if (idx == 1) {
	296	if (dev->revision <= 7)
	297	d.swdma_mask = 0;
	298	} else if (idx == 4) {
	299	if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
	300	dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
	301	d.udma_mask = ATA_UDMA5;
1da177e4	302	}
993da8f9 BZ	303
	304	printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n",
	305	d.name, pci_name(dev), dev->revision,
	306	amd_dma[fls(d.udma_mask) - 1]);
	307
	308	return ide_setup_pci_device(dev, &d);
1da177e4 LT	309	}
1da177e4 LT	310
9cbcc5e3 BZ	311	static const struct pci_device_id amd74xx_pci_tbl[] = {
	312	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
	313	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
	314	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 },
	315	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 3 },
	316	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 4 },
	317	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 5 },
	318	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 6 },
	319	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 7 },
1da177e4	320	#ifdef CONFIG_BLK_DEV_IDE_SATA
9cbcc5e3	321	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 8 },
1da177e4	322	#endif
9cbcc5e3 BZ	323	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 9 },
9cbcc5e3 BZ	324	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 10 },
1da177e4	325	#ifdef CONFIG_BLK_DEV_IDE_SATA
9cbcc5e3 BZ	326	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 11 },
9cbcc5e3 BZ	327	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 12 },
1da177e4	328	#endif
9cbcc5e3 BZ	329	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 13 },
	330	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 14 },
	331	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 15 },
	332	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 16 },
	333	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 17 },
	334	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 18 },
	335	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 19 },
	336	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 20 },
	337	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 21 },
	338	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 22 },
1da177e4 LT	339	{ 0, },
	340	};
	341	MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
	342
	343	static struct pci_driver driver = {
	344	.name = "AMD_IDE",
	345	.id_table = amd74xx_pci_tbl,
	346	.probe = amd74xx_probe,
	347	};
	348
82ab1eec	349	static int __init amd74xx_ide_init(void)
1da177e4 LT	350	{
	351	return ide_pci_register_driver(&driver);
	352	}
	353
	354	module_init(amd74xx_ide_init);
	355
	356	MODULE_AUTHOR("Vojtech Pavlik");
	357	MODULE_DESCRIPTION("AMD PCI IDE driver");
	358	MODULE_LICENSE("GPL");