Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04 |
3 | * IDE driver for Linux. | |
4 | * | |
5 | * Copyright (c) 2000-2002 Vojtech Pavlik | |
75b1d975 | 6 | * Copyright (c) 2007 Bartlomiej Zolnierkiewicz |
1da177e4 LT |
7 | * |
8 | * Based on the work of: | |
9 | * Andre Hedrick | |
10 | */ | |
11 | ||
12 | /* | |
13 | * This program is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License version 2 as published by | |
15 | * the Free Software Foundation. | |
16 | */ | |
17 | ||
1da177e4 LT |
18 | #include <linux/module.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/blkdev.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/ide.h> | |
25 | #include <asm/io.h> | |
26 | ||
27 | #include "ide-timing.h" | |
28 | ||
993da8f9 BZ |
29 | enum { |
30 | AMD_IDE_CONFIG = 0x41, | |
31 | AMD_CABLE_DETECT = 0x42, | |
32 | AMD_DRIVE_TIMING = 0x48, | |
33 | AMD_8BIT_TIMING = 0x4e, | |
34 | AMD_ADDRESS_SETUP = 0x4c, | |
35 | AMD_UDMA_TIMING = 0x50, | |
1da177e4 LT |
36 | }; |
37 | ||
1da177e4 LT |
38 | static unsigned int amd_80w; |
39 | static unsigned int amd_clock; | |
40 | ||
75b1d975 | 41 | static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" }; |
1da177e4 LT |
42 | static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 }; |
43 | ||
993da8f9 BZ |
44 | static inline u8 amd_offset(struct pci_dev *dev) |
45 | { | |
46 | return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0; | |
47 | } | |
48 | ||
1da177e4 LT |
49 | /* |
50 | * amd_set_speed() writes timing values to the chipset registers | |
51 | */ | |
52 | ||
993da8f9 BZ |
53 | static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask, |
54 | struct ide_timing *timing) | |
1da177e4 | 55 | { |
993da8f9 | 56 | u8 t = 0, offset = amd_offset(dev); |
1da177e4 | 57 | |
993da8f9 | 58 | pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t); |
1da177e4 | 59 | t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); |
993da8f9 | 60 | pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t); |
1da177e4 | 61 | |
993da8f9 | 62 | pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)), |
1da177e4 LT |
63 | ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1)); |
64 | ||
993da8f9 | 65 | pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn), |
1da177e4 LT |
66 | ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1)); |
67 | ||
993da8f9 | 68 | switch (udma_mask) { |
75b1d975 BZ |
69 | case ATA_UDMA2: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break; |
70 | case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break; | |
71 | case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break; | |
72 | case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break; | |
73 | default: return; | |
1da177e4 LT |
74 | } |
75 | ||
993da8f9 | 76 | pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + (3 - dn), t); |
1da177e4 LT |
77 | } |
78 | ||
79 | /* | |
88b2b32b BZ |
80 | * amd_set_drive() computes timing values and configures the chipset |
81 | * to a desired transfer mode. It also can be called by upper layers. | |
1da177e4 LT |
82 | */ |
83 | ||
88b2b32b | 84 | static void amd_set_drive(ide_drive_t *drive, const u8 speed) |
1da177e4 | 85 | { |
993da8f9 | 86 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 87 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
993da8f9 | 88 | ide_drive_t *peer = hwif->drives + (~drive->dn & 1); |
1da177e4 LT |
89 | struct ide_timing t, p; |
90 | int T, UT; | |
993da8f9 | 91 | u8 udma_mask = hwif->ultra_mask; |
1da177e4 | 92 | |
1da177e4 | 93 | T = 1000000000 / amd_clock; |
993da8f9 | 94 | UT = (udma_mask == ATA_UDMA2) ? T : (T / 2); |
1da177e4 LT |
95 | |
96 | ide_timing_compute(drive, speed, &t, T, UT); | |
97 | ||
98 | if (peer->present) { | |
99 | ide_timing_compute(peer, peer->current_speed, &p, T, UT); | |
100 | ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); | |
101 | } | |
102 | ||
103 | if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1; | |
104 | if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15; | |
105 | ||
36501650 | 106 | amd_set_speed(dev, drive->dn, udma_mask, &t); |
1da177e4 LT |
107 | } |
108 | ||
109 | /* | |
26bcb879 | 110 | * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning. |
1da177e4 LT |
111 | */ |
112 | ||
26bcb879 | 113 | static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio) |
1da177e4 | 114 | { |
26bcb879 | 115 | amd_set_drive(drive, XFER_PIO_0 + pio); |
1da177e4 LT |
116 | } |
117 | ||
993da8f9 BZ |
118 | static void __devinit amd7409_cable_detect(struct pci_dev *dev, |
119 | const char *name) | |
120 | { | |
121 | /* no host side cable detection */ | |
122 | amd_80w = 0x03; | |
123 | } | |
1da177e4 | 124 | |
993da8f9 BZ |
125 | static void __devinit amd7411_cable_detect(struct pci_dev *dev, |
126 | const char *name) | |
1da177e4 | 127 | { |
1da177e4 | 128 | int i; |
993da8f9 BZ |
129 | u32 u = 0; |
130 | u8 t = 0, offset = amd_offset(dev); | |
131 | ||
132 | pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t); | |
133 | pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u); | |
134 | amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0); | |
135 | for (i = 24; i >= 0; i -= 8) | |
136 | if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) { | |
137 | printk(KERN_WARNING "%s: BIOS didn't set cable bits " | |
138 | "correctly. Enabling workaround.\n", | |
139 | name); | |
140 | amd_80w |= (1 << (1 - (i >> 4))); | |
141 | } | |
142 | } | |
1da177e4 LT |
143 | |
144 | /* | |
993da8f9 | 145 | * The initialization callback. Initialize drive independent registers. |
1da177e4 LT |
146 | */ |
147 | ||
993da8f9 BZ |
148 | static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, |
149 | const char *name) | |
150 | { | |
151 | u8 t = 0, offset = amd_offset(dev); | |
1da177e4 LT |
152 | |
153 | /* | |
154 | * Check 80-wire cable presence. | |
155 | */ | |
156 | ||
993da8f9 BZ |
157 | if (dev->vendor == PCI_VENDOR_ID_AMD && |
158 | dev->device == PCI_DEVICE_ID_AMD_COBRA_7401) | |
159 | ; /* no UDMA > 2 */ | |
160 | else if (dev->vendor == PCI_VENDOR_ID_AMD && | |
161 | dev->device == PCI_DEVICE_ID_AMD_VIPER_7409) | |
162 | amd7409_cable_detect(dev, name); | |
163 | else | |
164 | amd7411_cable_detect(dev, name); | |
1da177e4 LT |
165 | |
166 | /* | |
167 | * Take care of prefetch & postwrite. | |
168 | */ | |
169 | ||
993da8f9 BZ |
170 | pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t); |
171 | /* | |
172 | * Check for broken FIFO support. | |
173 | */ | |
174 | if (dev->vendor == PCI_VENDOR_ID_AMD && | |
175 | dev->vendor == PCI_DEVICE_ID_AMD_VIPER_7411) | |
176 | t &= 0x0f; | |
177 | else | |
178 | t |= 0xf0; | |
179 | pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t); | |
1da177e4 LT |
180 | |
181 | /* | |
182 | * Determine the system bus clock. | |
183 | */ | |
184 | ||
185 | amd_clock = system_bus_clock() * 1000; | |
186 | ||
187 | switch (amd_clock) { | |
188 | case 33000: amd_clock = 33333; break; | |
189 | case 37000: amd_clock = 37500; break; | |
190 | case 41000: amd_clock = 41666; break; | |
191 | } | |
192 | ||
193 | if (amd_clock < 20000 || amd_clock > 50000) { | |
194 | printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n", | |
993da8f9 | 195 | name, amd_clock); |
1da177e4 LT |
196 | amd_clock = 33333; |
197 | } | |
198 | ||
1da177e4 LT |
199 | return dev->irq; |
200 | } | |
201 | ||
e895f926 | 202 | static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif) |
1da177e4 | 203 | { |
36501650 BZ |
204 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
205 | ||
1da177e4 | 206 | if (hwif->irq == 0) /* 0 is bogus but will do for now */ |
36501650 | 207 | hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel); |
1da177e4 | 208 | |
26bcb879 | 209 | hwif->set_pio_mode = &amd_set_pio_mode; |
88b2b32b | 210 | hwif->set_dma_mode = &amd_set_drive; |
1da177e4 | 211 | |
1da177e4 LT |
212 | if (!hwif->dma_base) |
213 | return; | |
214 | ||
49521f97 BZ |
215 | if (hwif->cbl != ATA_CBL_PATA40_SHORT) { |
216 | if ((amd_80w >> hwif->channel) & 1) | |
217 | hwif->cbl = ATA_CBL_PATA80; | |
218 | else | |
219 | hwif->cbl = ATA_CBL_PATA40; | |
220 | } | |
1da177e4 LT |
221 | } |
222 | ||
caea7602 BZ |
223 | #define IDE_HFLAGS_AMD \ |
224 | (IDE_HFLAG_PIO_NO_BLACKLIST | \ | |
225 | IDE_HFLAG_PIO_NO_DOWNGRADE | \ | |
4db90a14 | 226 | IDE_HFLAG_ABUSE_SET_DMA_MODE | \ |
caea7602 BZ |
227 | IDE_HFLAG_POST_SET_MODE | \ |
228 | IDE_HFLAG_IO_32BIT | \ | |
229 | IDE_HFLAG_UNMASK_IRQS | \ | |
230 | IDE_HFLAG_BOOTABLE) | |
231 | ||
993da8f9 | 232 | #define DECLARE_AMD_DEV(name_str, swdma, udma) \ |
1da177e4 LT |
233 | { \ |
234 | .name = name_str, \ | |
235 | .init_chipset = init_chipset_amd74xx, \ | |
236 | .init_hwif = init_hwif_amd74xx, \ | |
1da177e4 | 237 | .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \ |
caea7602 | 238 | .host_flags = IDE_HFLAGS_AMD, \ |
4099d143 | 239 | .pio_mask = ATA_PIO5, \ |
993da8f9 | 240 | .swdma_mask = swdma, \ |
5f8b6c34 | 241 | .mwdma_mask = ATA_MWDMA2, \ |
993da8f9 | 242 | .udma_mask = udma, \ |
1da177e4 LT |
243 | } |
244 | ||
993da8f9 | 245 | #define DECLARE_NV_DEV(name_str, udma) \ |
1da177e4 LT |
246 | { \ |
247 | .name = name_str, \ | |
248 | .init_chipset = init_chipset_amd74xx, \ | |
249 | .init_hwif = init_hwif_amd74xx, \ | |
1da177e4 | 250 | .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \ |
caea7602 | 251 | .host_flags = IDE_HFLAGS_AMD, \ |
4099d143 | 252 | .pio_mask = ATA_PIO5, \ |
5f8b6c34 BZ |
253 | .swdma_mask = ATA_SWDMA2, \ |
254 | .mwdma_mask = ATA_MWDMA2, \ | |
993da8f9 | 255 | .udma_mask = udma, \ |
1da177e4 LT |
256 | } |
257 | ||
85620436 | 258 | static const struct ide_port_info amd74xx_chipsets[] __devinitdata = { |
993da8f9 BZ |
259 | /* 0 */ DECLARE_AMD_DEV("AMD7401", 0x00, ATA_UDMA2), |
260 | /* 1 */ DECLARE_AMD_DEV("AMD7409", ATA_SWDMA2, ATA_UDMA4), | |
261 | /* 2 */ DECLARE_AMD_DEV("AMD7411", ATA_SWDMA2, ATA_UDMA5), | |
262 | /* 3 */ DECLARE_AMD_DEV("AMD7441", ATA_SWDMA2, ATA_UDMA5), | |
263 | /* 4 */ DECLARE_AMD_DEV("AMD8111", ATA_SWDMA2, ATA_UDMA6), | |
264 | ||
265 | /* 5 */ DECLARE_NV_DEV("NFORCE", ATA_UDMA5), | |
266 | /* 6 */ DECLARE_NV_DEV("NFORCE2", ATA_UDMA6), | |
267 | /* 7 */ DECLARE_NV_DEV("NFORCE2-U400R", ATA_UDMA6), | |
268 | /* 8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA", ATA_UDMA6), | |
269 | /* 9 */ DECLARE_NV_DEV("NFORCE3-150", ATA_UDMA6), | |
270 | /* 10 */ DECLARE_NV_DEV("NFORCE3-250", ATA_UDMA6), | |
271 | /* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA", ATA_UDMA6), | |
272 | /* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2", ATA_UDMA6), | |
273 | /* 13 */ DECLARE_NV_DEV("NFORCE-CK804", ATA_UDMA6), | |
274 | /* 14 */ DECLARE_NV_DEV("NFORCE-MCP04", ATA_UDMA6), | |
275 | /* 15 */ DECLARE_NV_DEV("NFORCE-MCP51", ATA_UDMA6), | |
276 | /* 16 */ DECLARE_NV_DEV("NFORCE-MCP55", ATA_UDMA6), | |
277 | /* 17 */ DECLARE_NV_DEV("NFORCE-MCP61", ATA_UDMA6), | |
278 | /* 18 */ DECLARE_NV_DEV("NFORCE-MCP65", ATA_UDMA6), | |
279 | /* 19 */ DECLARE_NV_DEV("NFORCE-MCP67", ATA_UDMA6), | |
280 | /* 20 */ DECLARE_NV_DEV("NFORCE-MCP73", ATA_UDMA6), | |
281 | /* 21 */ DECLARE_NV_DEV("NFORCE-MCP77", ATA_UDMA6), | |
282 | ||
283 | /* 22 */ DECLARE_AMD_DEV("AMD5536", ATA_SWDMA2, ATA_UDMA5), | |
1da177e4 LT |
284 | }; |
285 | ||
286 | static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
287 | { | |
993da8f9 BZ |
288 | struct ide_port_info d; |
289 | u8 idx = id->driver_data; | |
290 | ||
291 | d = amd74xx_chipsets[idx]; | |
292 | ||
293 | /* | |
294 | * Check for bad SWDMA and incorrectly wired Serenade mainboards. | |
295 | */ | |
296 | if (idx == 1) { | |
297 | if (dev->revision <= 7) | |
298 | d.swdma_mask = 0; | |
8ac2b42a | 299 | d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX; |
993da8f9 BZ |
300 | } else if (idx == 4) { |
301 | if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD && | |
302 | dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE) | |
303 | d.udma_mask = ATA_UDMA5; | |
1da177e4 | 304 | } |
993da8f9 BZ |
305 | |
306 | printk(KERN_INFO "%s: %s (rev %02x) UDMA%s controller\n", | |
307 | d.name, pci_name(dev), dev->revision, | |
308 | amd_dma[fls(d.udma_mask) - 1]); | |
309 | ||
310 | return ide_setup_pci_device(dev, &d); | |
1da177e4 LT |
311 | } |
312 | ||
9cbcc5e3 BZ |
313 | static const struct pci_device_id amd74xx_pci_tbl[] = { |
314 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 }, | |
315 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 }, | |
316 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 }, | |
317 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 3 }, | |
318 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 4 }, | |
319 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 5 }, | |
320 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 6 }, | |
321 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 7 }, | |
1da177e4 | 322 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
9cbcc5e3 | 323 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 8 }, |
1da177e4 | 324 | #endif |
9cbcc5e3 BZ |
325 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 9 }, |
326 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 10 }, | |
1da177e4 | 327 | #ifdef CONFIG_BLK_DEV_IDE_SATA |
9cbcc5e3 BZ |
328 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 11 }, |
329 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 12 }, | |
1da177e4 | 330 | #endif |
9cbcc5e3 BZ |
331 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 13 }, |
332 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 14 }, | |
333 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 15 }, | |
334 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 16 }, | |
335 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 17 }, | |
336 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 18 }, | |
337 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 19 }, | |
338 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 20 }, | |
339 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 21 }, | |
340 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 22 }, | |
1da177e4 LT |
341 | { 0, }, |
342 | }; | |
343 | MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl); | |
344 | ||
345 | static struct pci_driver driver = { | |
346 | .name = "AMD_IDE", | |
347 | .id_table = amd74xx_pci_tbl, | |
348 | .probe = amd74xx_probe, | |
349 | }; | |
350 | ||
82ab1eec | 351 | static int __init amd74xx_ide_init(void) |
1da177e4 LT |
352 | { |
353 | return ide_pci_register_driver(&driver); | |
354 | } | |
355 | ||
356 | module_init(amd74xx_ide_init); | |
357 | ||
358 | MODULE_AUTHOR("Vojtech Pavlik"); | |
359 | MODULE_DESCRIPTION("AMD PCI IDE driver"); | |
360 | MODULE_LICENSE("GPL"); |