projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PCI: Change all drivers to use pci_device->revision
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ide / pci / alim15x3.c
CommitLineData
1da177e4 1/*
95ba8c17 2 * linux/drivers/ide/pci/alim15x3.c Version 0.25 Jun 9 2007
1da177e4
LT		 3 *
4 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
6 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
7 *
8 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
9 * May be copied or modified under the terms of the GNU General Public License
10 * Copyright (C) 2002 Alan Cox <alan@redhat.com>
11 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
21b82477 12 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
95ba8c17 13 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
1da177e4
LT		 14 *
15 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
16 *
17 **********************************************************************
18 * 9/7/99 --Parts from the above author are included and need to be
19 * converted into standard interface, once I finish the thought.
20 *
21 * Recent changes
22 * Don't use LBA48 mode on ALi <= 0xC4
23 * Don't poke 0x79 with a non ALi northbridge
24 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
25 * Allow UDMA6 on revisions > 0xC4
26 *
27 * Documentation
28 * Chipset documentation available under NDA only
29 *
30 */
31
1da177e4
LT		 32#include <linux/module.h>
33#include <linux/types.h>
34#include <linux/kernel.h>
35#include <linux/pci.h>
36#include <linux/delay.h>
37#include <linux/hdreg.h>
38#include <linux/ide.h>
39#include <linux/init.h>
95ba8c17 40#include <linux/dmi.h>
1da177e4
LT		 41
42#include <asm/io.h>
43
44#define DISPLAY_ALI_TIMINGS
45
46/*
47 * ALi devices are not plug in. Otherwise these static values would
48 * need to go. They ought to go away anyway
49 */
50
51static u8 m5229_revision;
52static u8 chip_is_1543c_e;
53static struct pci_dev *isa_dev;
54
ecfd80e4 55#if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
1da177e4
LT		 56#include <linux/stat.h>
57#include <linux/proc_fs.h>
58
59static u8 ali_proc = 0;
60
61static struct pci_dev *bmide_dev;
62
63static char *fifo[4] = {
64 "FIFO Off",
65 "FIFO On ",
66 "DMA mode",
67 "PIO mode" };
68
69static char *udmaT[8] = {
70 "1.5T",
71 " 2T",
72 "2.5T",
73 " 3T",
74 "3.5T",
75 " 4T",
76 " 6T",
77 " 8T"
78};
79
80static char *channel_status[8] = {
81 "OK ",
82 "busy ",
83 "DRQ ",
84 "DRQ busy ",
85 "error ",
86 "error busy ",
87 "error DRQ ",
88 "error DRQ busy"
89};
90
91/**
92 * ali_get_info - generate proc file for ALi IDE
93 * @buffer: buffer to fill
94 * @addr: address of user start in buffer
95 * @offset: offset into 'file'
96 * @count: buffer count
97 *
98 * Walks the Ali devices and outputs summary data on the tuning and
99 * anything else that will help with debugging
100 */
101
102static int ali_get_info (char *buffer, char **addr, off_t offset, int count)
103{
104 unsigned long bibma;
105 u8 reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1, c0, c1, rev, tmp;
106 char *q, *p = buffer;
107
108 /* fetch rev. */
109 pci_read_config_byte(bmide_dev, 0x08, &rev);
110 if (rev >= 0xc1) /* M1543C or newer */
111 udmaT[7] = " ???";
112 else
113 fifo[3] = " ??? ";
114
115 /* first fetch bibma: */
116
117 bibma = pci_resource_start(bmide_dev, 4);
118
119 /*
120 * at that point bibma+0x2 et bibma+0xa are byte
121 * registers to investigate:
122 */
123 c0 = inb(bibma + 0x02);
124 c1 = inb(bibma + 0x0a);
125
126 p += sprintf(p,
127 "\n Ali M15x3 Chipset.\n");
128 p += sprintf(p,
129 " ------------------\n");
130 pci_read_config_byte(bmide_dev, 0x78, &reg53h);
131 p += sprintf(p, "PCI Clock: %d.\n", reg53h);
132
133 pci_read_config_byte(bmide_dev, 0x53, &reg53h);
134 p += sprintf(p,
135 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
136 (reg53h & 0x02) ? "Yes" : "No ",
137 (reg53h & 0x01) ? "Yes" : "No " );
138 pci_read_config_byte(bmide_dev, 0x74, &reg53h);
139 p += sprintf(p,
140 "FIFO Status: contains %d Words, runs%s%s\n\n",
141 (reg53h & 0x3f),
142 (reg53h & 0x40) ? " OVERWR" : "",
143 (reg53h & 0x80) ? " OVERRD." : "." );
144
145 p += sprintf(p,
146 "-------------------primary channel"
147 "-------------------secondary channel"
148 "---------\n\n");
149
150 pci_read_config_byte(bmide_dev, 0x09, &reg53h);
151 p += sprintf(p,
152 "channel status: %s"
153 " %s\n",
154 (reg53h & 0x20) ? "On " : "Off",
155 (reg53h & 0x10) ? "On " : "Off" );
156
157 p += sprintf(p,
158 "both channels togth: %s"
159 " %s\n",
160 (c0&0x80) ? "No " : "Yes",
161 (c1&0x80) ? "No " : "Yes" );
162
163 pci_read_config_byte(bmide_dev, 0x76, &reg53h);
164 p += sprintf(p,
165 "Channel state: %s %s\n",
166 channel_status[reg53h & 0x07],
167 channel_status[(reg53h & 0x70) >> 4] );
168
169 pci_read_config_byte(bmide_dev, 0x58, &reg5xh);
170 pci_read_config_byte(bmide_dev, 0x5c, &reg5yh);
171 p += sprintf(p,
172 "Add. Setup Timing: %dT"
173 " %dT\n",
174 (reg5xh & 0x07) ? (reg5xh & 0x07) : 8,
175 (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 );
176
177 pci_read_config_byte(bmide_dev, 0x59, &reg5xh);
178 pci_read_config_byte(bmide_dev, 0x5d, &reg5yh);
179 p += sprintf(p,
180 "Command Act. Count: %dT"
181 " %dT\n"
182 "Command Rec. Count: %dT"
183 " %dT\n\n",
184 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
185 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
186 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
187 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 );
188
189 p += sprintf(p,
190 "----------------drive0-----------drive1"
191 "------------drive0-----------drive1------\n\n");
192 p += sprintf(p,
193 "DMA enabled: %s %s"
194 " %s %s\n",
195 (c0&0x20) ? "Yes" : "No ",
196 (c0&0x40) ? "Yes" : "No ",
197 (c1&0x20) ? "Yes" : "No ",
198 (c1&0x40) ? "Yes" : "No " );
199
200 pci_read_config_byte(bmide_dev, 0x54, &reg5xh);
201 pci_read_config_byte(bmide_dev, 0x55, &reg5yh);
202 q = "FIFO threshold: %2d Words %2d Words"
203 " %2d Words %2d Words\n";
204 if (rev < 0xc1) {
205 if ((rev == 0x20) &&
206 (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) {
207 p += sprintf(p, q, 8, 8, 8, 8);
208 } else {
209 p += sprintf(p, q,
210 (reg5xh & 0x03) + 12,
211 ((reg5xh & 0x30)>>4) + 12,
212 (reg5yh & 0x03) + 12,
213 ((reg5yh & 0x30)>>4) + 12 );
214 }
215 } else {
216 int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4;
217 int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4;
218 int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4;
219 int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4;
220 p += sprintf(p, q, t1, t2, t3, t4);
221 }
222
223#if 0
224 p += sprintf(p,
225 "FIFO threshold: %2d Words %2d Words"
226 " %2d Words %2d Words\n",
227 (reg5xh & 0x03) + 12,
228 ((reg5xh & 0x30)>>4) + 12,
229 (reg5yh & 0x03) + 12,
230 ((reg5yh & 0x30)>>4) + 12 );
231#endif
232
233 p += sprintf(p,
234 "FIFO mode: %s %s %s %s\n",
235 fifo[((reg5xh & 0x0c) >> 2)],
236 fifo[((reg5xh & 0xc0) >> 6)],
237 fifo[((reg5yh & 0x0c) >> 2)],
238 fifo[((reg5yh & 0xc0) >> 6)] );
239
240 pci_read_config_byte(bmide_dev, 0x5a, &reg5xh);
241 pci_read_config_byte(bmide_dev, 0x5b, &reg5xh1);
242 pci_read_config_byte(bmide_dev, 0x5e, &reg5yh);
243 pci_read_config_byte(bmide_dev, 0x5f, &reg5yh1);
244
245 p += sprintf(p,/*
246 "------------------drive0-----------drive1"
247 "------------drive0-----------drive1------\n")*/
248 "Dt RW act. Cnt %2dT %2dT"
249 " %2dT %2dT\n"
250 "Dt RW rec. Cnt %2dT %2dT"
251 " %2dT %2dT\n\n",
252 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
253 (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8,
254 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
255 (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8,
256 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
257 (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16,
258 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16,
259 (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 );
260
261 p += sprintf(p,
262 "-----------------------------------UDMA Timings"
263 "--------------------------------\n\n");
264
265 pci_read_config_byte(bmide_dev, 0x56, &reg5xh);
266 pci_read_config_byte(bmide_dev, 0x57, &reg5yh);
267 p += sprintf(p,
268 "UDMA: %s %s"
269 " %s %s\n"
270 "UDMA timings: %s %s"
271 " %s %s\n\n",
272 (reg5xh & 0x08) ? "OK" : "No",
273 (reg5xh & 0x80) ? "OK" : "No",
274 (reg5yh & 0x08) ? "OK" : "No",
275 (reg5yh & 0x80) ? "OK" : "No",
276 udmaT[(reg5xh & 0x07)],
277 udmaT[(reg5xh & 0x70) >> 4],
278 udmaT[reg5yh & 0x07],
279 udmaT[(reg5yh & 0x70) >> 4] );
280
281 return p-buffer; /* => must be less than 4k! */
282}
ecfd80e4 283#endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
1da177e4
LT		 284
285/**
21b82477 286 * ali15x3_tune_pio - set up chipset for PIO mode
1da177e4 287 * @drive: drive to tune
21b82477 288 * @pio: desired mode
1da177e4 289 *
21b82477
SS		 290 * Select the best PIO mode for the drive in question.
291 * Then program the controller for this mode.
292 *
293 * Returns the PIO mode programmed.
1da177e4
LT		 294 */
295
21b82477 296static u8 ali15x3_tune_pio (ide_drive_t *drive, u8 pio)
1da177e4
LT		 297{
298 ide_pio_data_t d;
299 ide_hwif_t *hwif = HWIF(drive);
300 struct pci_dev *dev = hwif->pci_dev;
301 int s_time, a_time, c_time;
302 u8 s_clc, a_clc, r_clc;
303 unsigned long flags;
304 int bus_speed = system_bus_clock();
305 int port = hwif->channel ? 0x5c : 0x58;
306 int portFIFO = hwif->channel ? 0x55 : 0x54;
307 u8 cd_dma_fifo = 0;
308 int unit = drive->select.b.unit & 1;
309
310 pio = ide_get_best_pio_mode(drive, pio, 5, &d);
311 s_time = ide_pio_timings[pio].setup_time;
312 a_time = ide_pio_timings[pio].active_time;
313 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
314 s_clc = 0;
315 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
316 a_clc = 0;
317 c_time = ide_pio_timings[pio].cycle_time;
318
319#if 0
320 if ((r_clc = ((c_time - s_time - a_time) * bus_speed + 999) / 1000) >= 16)
321 r_clc = 0;
322#endif
323
324 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
325 r_clc = 1;
326 } else {
327 if (r_clc >= 16)
328 r_clc = 0;
329 }
330 local_irq_save(flags);
331
332 /*
333 * PIO mode => ATA FIFO on, ATAPI FIFO off
334 */
335 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
336 if (drive->media==ide_disk) {
337 if (unit) {
338 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
339 } else {
340 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
341 }
342 } else {
343 if (unit) {
344 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
345 } else {
346 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
347 }
348 }
349
350 pci_write_config_byte(dev, port, s_clc);
351 pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc);
352 local_irq_restore(flags);
353
354 /*
355 * setup active rec
356 * { 70, 165, 365 }, PIO Mode 0
357 * { 50, 125, 208 }, PIO Mode 1
358 * { 30, 100, 110 }, PIO Mode 2
359 * { 30, 80, 70 }, PIO Mode 3 with IORDY
360 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns
361 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard)
362 */
363
21b82477
SS		 364 return pio;
365}
366
367/**
368 * ali15x3_tune_drive - set up drive for PIO mode
369 * @drive: drive to tune
370 * @pio: desired mode
371 *
372 * Program the controller with the best PIO timing for the given drive.
373 * Then set up the drive itself.
374 */
375
376static void ali15x3_tune_drive (ide_drive_t *drive, u8 pio)
377{
378 pio = ali15x3_tune_pio(drive, pio);
379 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
1da177e4
LT		 380}
381
382/**
2d5eaa6d
BZ		 383 * ali_udma_filter - compute UDMA mask
384 * @drive: IDE device
1da177e4 385 *
2d5eaa6d
BZ		 386 * Return available UDMA modes.
387 *
388 * The actual rules for the ALi are:
1da177e4
LT		 389 * No UDMA on revisions <= 0x20
390 * Disk only for revisions < 0xC2
391 * Not WDC drives for revisions < 0xC2
392 *
393 * FIXME: WDC ifdef needs to die
394 */
1da177e4 395
2d5eaa6d 396static u8 ali_udma_filter(ide_drive_t *drive)
1da177e4 397{
2d5eaa6d
BZ		 398 if (m5229_revision > 0x20 && m5229_revision < 0xC2) {
399 if (drive->media != ide_disk)
400 return 0;
401#ifndef CONFIG_WDC_ALI15X3
402 if (chip_is_1543c_e && strstr(drive->id->model, "WDC "))
403 return 0;
404#endif
1da177e4
LT		 405 }
406
2d5eaa6d 407 return drive->hwif->ultra_mask;
1da177e4
LT		 408}
409
410/**
21b82477 411 * ali15x3_tune_chipset - set up chipset/drive for new speed
1da177e4
LT		 412 * @drive: drive to configure for
413 * @xferspeed: desired speed
414 *
415 * Configure the hardware for the desired IDE transfer mode.
416 * We also do the needed drive configuration through helpers
417 */
418
419static int ali15x3_tune_chipset (ide_drive_t *drive, u8 xferspeed)
420{
421 ide_hwif_t *hwif = HWIF(drive);
422 struct pci_dev *dev = hwif->pci_dev;
2d5eaa6d 423 u8 speed = ide_rate_filter(drive, xferspeed);
1da177e4
LT		 424 u8 speed1 = speed;
425 u8 unit = (drive->select.b.unit & 0x01);
426 u8 tmpbyte = 0x00;
427 int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
428
429 if (speed == XFER_UDMA_6)
430 speed1 = 0x47;
431
432 if (speed < XFER_UDMA_0) {
433 u8 ultra_enable = (unit) ? 0x7f : 0xf7;
434 /*
435 * clear "ultra enable" bit
436 */
437 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
438 tmpbyte &= ultra_enable;
439 pci_write_config_byte(dev, m5229_udma, tmpbyte);
440
441 if (speed < XFER_SW_DMA_0)
21b82477 442 (void) ali15x3_tune_pio(drive, speed - XFER_PIO_0);
1da177e4
LT		 443 } else {
444 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
445 tmpbyte &= (0x0f << ((1-unit) << 2));
446 /*
447 * enable ultra dma and set timing
448 */
449 tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
450 pci_write_config_byte(dev, m5229_udma, tmpbyte);
451 if (speed >= XFER_UDMA_3) {
452 pci_read_config_byte(dev, 0x4b, &tmpbyte);
453 tmpbyte |= 1;
454 pci_write_config_byte(dev, 0x4b, tmpbyte);
455 }
456 }
457 return (ide_config_drive_speed(drive, speed));
458}
459
1da177e4
LT		 460/**
461 * ali15x3_config_drive_for_dma - configure for DMA
462 * @drive: drive to configure
463 *
464 * Configure a drive for DMA operation. If DMA is not possible we
465 * drop the drive into PIO mode instead.
1da177e4 466 */
3608b5d7 467
1da177e4
LT		 468static int ali15x3_config_drive_for_dma(ide_drive_t *drive)
469{
1da177e4
LT		 470 drive->init_speed = 0;
471
38ff8a74
BZ		 472 if (ide_tune_dma(drive))
473 return 0;
3608b5d7 474
38ff8a74
BZ		 475 ali15x3_tune_drive(drive, 255);
476
477 return -1;
1da177e4
LT		 478}
479
480/**
481 * ali15x3_dma_setup - begin a DMA phase
482 * @drive: target device
483 *
484 * Returns 1 if the DMA cannot be performed, zero on success.
485 */
486
487static int ali15x3_dma_setup(ide_drive_t *drive)
488{
489 if (m5229_revision < 0xC2 && drive->media != ide_disk) {
490 if (rq_data_dir(drive->hwif->hwgroup->rq))
491 return 1; /* try PIO instead of DMA */
492 }
493 return ide_dma_setup(drive);
494}
495
496/**
497 * init_chipset_ali15x3 - Initialise an ALi IDE controller
498 * @dev: PCI device
499 * @name: Name of the controller
500 *
501 * This function initializes the ALI IDE controller and where
502 * appropriate also sets up the 1533 southbridge.
503 */
504
c2f12589 505static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const char *name)
1da177e4
LT		 506{
507 unsigned long flags;
508 u8 tmpbyte;
b1489009 509 struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0));
1da177e4 510
44c10138 511 m5229_revision = dev->revision;
1da177e4 512
b1489009 513 isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
1da177e4 514
ecfd80e4 515#if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
1da177e4
LT		 516 if (!ali_proc) {
517 ali_proc = 1;
518 bmide_dev = dev;
519 ide_pci_create_host_proc("ali", ali_get_info);
520 }
ecfd80e4 521#endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
1da177e4
LT		 522
523 local_irq_save(flags);
524
525 if (m5229_revision < 0xC2) {
526 /*
527 * revision 0x20 (1543-E, 1543-F)
528 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
529 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
530 */
531 pci_read_config_byte(dev, 0x4b, &tmpbyte);
532 /*
533 * clear bit 7
534 */
535 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
b1489009 536 goto out;
1da177e4
LT		 537 }
538
539 /*
540 * 1543C-B?, 1535, 1535D, 1553
541 * Note 1: not all "motherboard" support this detection
542 * Note 2: if no udma 66 device, the detection may "error".
543 * but in this case, we will not set the device to
544 * ultra 66, the detection result is not important
545 */
546
547 /*
548 * enable "Cable Detection", m5229, 0x4b, bit3
549 */
550 pci_read_config_byte(dev, 0x4b, &tmpbyte);
551 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
552
553 /*
554 * We should only tune the 1533 enable if we are using an ALi
555 * North bridge. We might have no north found on some zany
556 * box without a device at 0:0.0. The ALi bridge will be at
557 * 0:0.0 so if we didn't find one we know what is cooking.
558 */
b1489009
AC		 559 if (north && north->vendor != PCI_VENDOR_ID_AL)
560 goto out;
1da177e4
LT		 561
562 if (m5229_revision < 0xC5 && isa_dev)
563 {
564 /*
565 * set south-bridge's enable bit, m1533, 0x79
566 */
567
568 pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
569 if (m5229_revision == 0xC2) {
570 /*
571 * 1543C-B0 (m1533, 0x79, bit 2)
572 */
573 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
574 } else if (m5229_revision >= 0xC3) {
575 /*
576 * 1553/1535 (m1533, 0x79, bit 1)
577 */
578 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
579 }
580 }
b1489009
AC		 581out:
582 pci_dev_put(north);
583 pci_dev_put(isa_dev);
1da177e4
LT		 584 local_irq_restore(flags);
585 return 0;
586}
587
95ba8c17
BZ		 588/*
589 * Cable special cases
590 */
591
592static struct dmi_system_id cable_dmi_table[] = {
593 {
594 .ident = "HP Pavilion N5430",
595 .matches = {
596 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
597 DMI_MATCH(DMI_BOARD_NAME, "OmniBook N32N-736"),
598 },
599 },
600 { }
601};
602
603static int ali_cable_override(struct pci_dev *pdev)
604{
605 /* Fujitsu P2000 */
606 if (pdev->subsystem_vendor == 0x10CF &&
607 pdev->subsystem_device == 0x10AF)
608 return 1;
609
610 /* Systems by DMI */
611 if (dmi_check_system(cable_dmi_table))
612 return 1;
613
614 return 0;
615}
616
1da177e4
LT		 617/**
618 * ata66_ali15x3 - check for UDMA 66 support
619 * @hwif: IDE interface
620 *
621 * This checks if the controller and the cable are capable
622 * of UDMA66 transfers. It doesn't check the drives.
623 * But see note 2 below!
624 *
625 * FIXME: frobs bits that are not defined on newer ALi devicea
626 */
627
49521f97 628static u8 __devinit ata66_ali15x3(ide_hwif_t *hwif)
1da177e4
LT		 629{
630 struct pci_dev *dev = hwif->pci_dev;
1da177e4 631 unsigned long flags;
95ba8c17 632 u8 cbl = ATA_CBL_PATA40, tmpbyte;
1da177e4
LT		 633
634 local_irq_save(flags);
635
636 if (m5229_revision >= 0xC2) {
637 /*
95ba8c17
BZ		 638 * m5229 80-pin cable detection (from Host View)
639 *
640 * 0x4a bit0 is 0 => primary channel has 80-pin
641 * 0x4a bit1 is 0 => secondary channel has 80-pin
642 *
643 * Certain laptops use short but suitable cables
644 * and don't implement the detect logic.
1da177e4 645 */
95ba8c17
BZ		 646 if (ali_cable_override(dev))
647 cbl = ATA_CBL_PATA40_SHORT;
648 else {
649 pci_read_config_byte(dev, 0x4a, &tmpbyte);
650 if ((tmpbyte & (1 << hwif->channel)) == 0)
651 cbl = ATA_CBL_PATA80;
652 }
1da177e4
LT		 653 } else {
654 /*
655 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
656 */
657 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
658 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
659 }
660
661 /*
662 * CD_ROM DMA on (m5229, 0x53, bit0)
663 * Enable this bit even if we want to use PIO
664 * PIO FIFO off (m5229, 0x53, bit1)
665 * The hardware will use 0x54h and 0x55h to control PIO FIFO
666 * (Not on later devices it seems)
667 *
668 * 0x53 changes meaning on later revs - we must no touch
669 * bit 1 on them. Need to check if 0x20 is the right break
670 */
671
672 pci_read_config_byte(dev, 0x53, &tmpbyte);
673
674 if(m5229_revision <= 0x20)
675 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
e11db063 676 else if (m5229_revision == 0xc7 || m5229_revision == 0xc8)
0d8a95ef 677 tmpbyte |= 0x03;
1da177e4
LT		 678 else
679 tmpbyte |= 0x01;
680
681 pci_write_config_byte(dev, 0x53, tmpbyte);
682
683 local_irq_restore(flags);
684
95ba8c17 685 return cbl;
1da177e4
LT		 686}
687
688/**
689 * init_hwif_common_ali15x3 - Set up ALI IDE hardware
690 * @hwif: IDE interface
691 *
692 * Initialize the IDE structure side of the ALi 15x3 driver.
693 */
694
c2f12589 695static void __devinit init_hwif_common_ali15x3 (ide_hwif_t *hwif)
1da177e4
LT		 696{
697 hwif->autodma = 0;
698 hwif->tuneproc = &ali15x3_tune_drive;
699 hwif->speedproc = &ali15x3_tune_chipset;
2d5eaa6d 700 hwif->udma_filter = &ali_udma_filter;
1da177e4
LT		 701
702 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
703 hwif->no_lba48_dma = (m5229_revision <= 0xC4) ? 1 : 0;
704
705 if (!hwif->dma_base) {
706 hwif->drives[0].autotune = 1;
707 hwif->drives[1].autotune = 1;
708 return;
709 }
710
38ff8a74
BZ		 711 if (m5229_revision > 0x20)
712 hwif->atapi_dma = 1;
1da177e4 713
18137207
BZ		 714 if (m5229_revision <= 0x20)
715 hwif->ultra_mask = 0x00; /* no udma */
716 else if (m5229_revision < 0xC2)
717 hwif->ultra_mask = 0x07; /* udma0-2 */
718 else if (m5229_revision == 0xC2 || m5229_revision == 0xC3)
719 hwif->ultra_mask = 0x1f; /* udma0-4 */
720 else if (m5229_revision == 0xC4)
721 hwif->ultra_mask = 0x3f; /* udma0-5 */
722 else
723 hwif->ultra_mask = 0x7f; /* udma0-6 */
724
1da177e4
LT		 725 hwif->mwdma_mask = 0x07;
726 hwif->swdma_mask = 0x07;
727
728 if (m5229_revision >= 0x20) {
729 /*
730 * M1543C or newer for DMAing
731 */
732 hwif->ide_dma_check = &ali15x3_config_drive_for_dma;
733 hwif->dma_setup = &ali15x3_dma_setup;
734 if (!noautodma)
735 hwif->autodma = 1;
49521f97
BZ		 736
737 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
738 hwif->cbl = ata66_ali15x3(hwif);
1da177e4
LT		 739 }
740 hwif->drives[0].autodma = hwif->autodma;
741 hwif->drives[1].autodma = hwif->autodma;
742}
743
744/**
745 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
746 * @hwif: interface to configure
747 *
748 * Obtain the IRQ tables for an ALi based IDE solution on the PC
749 * class platforms. This part of the code isn't applicable to the
750 * Sparc systems
751 */
752
c2f12589 753static void __devinit init_hwif_ali15x3 (ide_hwif_t *hwif)
1da177e4
LT		 754{
755 u8 ideic, inmir;
756 s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
757 1, 11, 0, 12, 0, 14, 0, 15 };
758 int irq = -1;
759
760 if (hwif->pci_dev->device == PCI_DEVICE_ID_AL_M5229)
761 hwif->irq = hwif->channel ? 15 : 14;
762
763 if (isa_dev) {
764 /*
765 * read IDE interface control
766 */
767 pci_read_config_byte(isa_dev, 0x58, &ideic);
768
769 /* bit0, bit1 */
770 ideic = ideic & 0x03;
771
772 /* get IRQ for IDE Controller */
773 if ((hwif->channel && ideic == 0x03) ||
774 (!hwif->channel && !ideic)) {
775 /*
776 * get SIRQ1 routing table
777 */
778 pci_read_config_byte(isa_dev, 0x44, &inmir);
779 inmir = inmir & 0x0f;
780 irq = irq_routing_table[inmir];
781 } else if (hwif->channel && !(ideic & 0x01)) {
782 /*
783 * get SIRQ2 routing table
784 */
785 pci_read_config_byte(isa_dev, 0x75, &inmir);
786 inmir = inmir & 0x0f;
787 irq = irq_routing_table[inmir];
788 }
789 if(irq >= 0)
790 hwif->irq = irq;
791 }
792
793 init_hwif_common_ali15x3(hwif);
794}
795
796/**
797 * init_dma_ali15x3 - set up DMA on ALi15x3
798 * @hwif: IDE interface
799 * @dmabase: DMA interface base PCI address
800 *
801 * Set up the DMA functionality on the ALi 15x3. For the ALi
802 * controllers this is generic so we can let the generic code do
803 * the actual work.
804 */
805
c2f12589 806static void __devinit init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
1da177e4
LT		 807{
808 if (m5229_revision < 0x20)
809 return;
0ecdca26
BZ		 810 if (!hwif->channel)
811 outb(inb(dmabase + 2) & 0x60, dmabase + 2);
1da177e4
LT		 812 ide_setup_dma(hwif, dmabase, 8);
813}
814
815static ide_pci_device_t ali15x3_chipset __devinitdata = {
816 .name = "ALI15X3",
817 .init_chipset = init_chipset_ali15x3,
818 .init_hwif = init_hwif_ali15x3,
819 .init_dma = init_dma_ali15x3,
820 .channels = 2,
821 .autodma = AUTODMA,
822 .bootable = ON_BOARD,
823};
824
825/**
826 * alim15x3_init_one - set up an ALi15x3 IDE controller
827 * @dev: PCI device to set up
828 *
829 * Perform the actual set up for an ALi15x3 that has been found by the
830 * hot plug layer.
831 */
832
833static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
834{
cc3f7ca5
HL		 835 static struct pci_device_id ati_rs100[] = {
836 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100) },
837 { },
838 };
839
1da177e4
LT		 840 ide_pci_device_t *d = &ali15x3_chipset;
841
cc3f7ca5 842 if (pci_dev_present(ati_rs100))
2fefef18 843 printk(KERN_WARNING "alim15x3: ATI Radeon IGP Northbridge is not yet fully tested.\n");
1da177e4
LT		 844
845#if defined(CONFIG_SPARC64)
846 d->init_hwif = init_hwif_common_ali15x3;
847#endif /* CONFIG_SPARC64 */
848 return ide_setup_pci_device(dev, d);
849}
850
851
852static struct pci_device_id alim15x3_pci_tbl[] = {
853 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
854 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5228, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
855 { 0, },
856};
857MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
858
859static struct pci_driver driver = {
860 .name = "ALI15x3_IDE",
861 .id_table = alim15x3_pci_tbl,
862 .probe = alim15x3_init_one,
863};
864
82ab1eec 865static int __init ali15x3_ide_init(void)
1da177e4
LT		 866{
867 return ide_pci_register_driver(&driver);
868}
869
870module_init(ali15x3_ide_init);
871
872MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
873MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
874MODULE_LICENSE("GPL");