[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / aec62xx.c

/*
 * linux/drivers/ide/pci/aec62xx.c		Version 0.21	Apr 21, 2007
 *
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2007		MontaVista Software, Inc. <source@mvista.com>
 *
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

struct chipset_bus_clock_list_entry {
	u8 xfer_speed;
	u8 chipset_settings;
	u8 ultra_settings;
};

static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
	{	XFER_UDMA_6,	0x31,	0x07	},
	{	XFER_UDMA_5,	0x31,	0x06	},
	{	XFER_UDMA_4,	0x31,	0x05	},
	{	XFER_UDMA_3,	0x31,	0x04	},
	{	XFER_UDMA_2,	0x31,	0x03	},
	{	XFER_UDMA_1,	0x31,	0x02	},
	{	XFER_UDMA_0,	0x31,	0x01	},

	{	XFER_MW_DMA_2,	0x31,	0x00	},
	{	XFER_MW_DMA_1,	0x31,	0x00	},
	{	XFER_MW_DMA_0,	0x0a,	0x00	},
	{	XFER_PIO_4,	0x31,	0x00	},
	{	XFER_PIO_3,	0x33,	0x00	},
	{	XFER_PIO_2,	0x08,	0x00	},
	{	XFER_PIO_1,	0x0a,	0x00	},
	{	XFER_PIO_0,	0x00,	0x00	},
	{	0,		0x00,	0x00	}
};

static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
	{	XFER_UDMA_6,	0x41,	0x06	},
	{	XFER_UDMA_5,	0x41,	0x05	},
	{	XFER_UDMA_4,	0x41,	0x04	},
	{	XFER_UDMA_3,	0x41,	0x03	},
	{	XFER_UDMA_2,	0x41,	0x02	},
	{	XFER_UDMA_1,	0x41,	0x01	},
	{	XFER_UDMA_0,	0x41,	0x01	},

	{	XFER_MW_DMA_2,	0x41,	0x00	},
	{	XFER_MW_DMA_1,	0x42,	0x00	},
	{	XFER_MW_DMA_0,	0x7a,	0x00	},
	{	XFER_PIO_4,	0x41,	0x00	},
	{	XFER_PIO_3,	0x43,	0x00	},
	{	XFER_PIO_2,	0x78,	0x00	},
	{	XFER_PIO_1,	0x7a,	0x00	},
	{	XFER_PIO_0,	0x70,	0x00	},
	{	0,		0x00,	0x00	}
};

#define BUSCLOCK(D)	\
	((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))


/*
 * TO DO: active tuning and correction of cards without a bios.
 */
static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
{
	for ( ; chipset_table->xfer_speed ; chipset_table++)
		if (chipset_table->xfer_speed == speed) {
			return chipset_table->chipset_settings;
		}
	return chipset_table->chipset_settings;
}

static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
{
	for ( ; chipset_table->xfer_speed ; chipset_table++)
		if (chipset_table->xfer_speed == speed) {
			return chipset_table->ultra_settings;
		}
	return chipset_table->ultra_settings;
}

static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u16 d_conf		= 0;
	u8 speed		= ide_rate_filter(drive, xferspeed);
	u8 ultra = 0, ultra_conf = 0;
	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
	unsigned long flags;

	local_irq_save(flags);
	/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
	pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
	tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
	d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
	pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);

	tmp1 = 0x00;
	tmp2 = 0x00;
	pci_read_config_byte(dev, 0x54, &ultra);
	tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
	ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
	tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
	pci_write_config_byte(dev, 0x54, tmp2);
	local_irq_restore(flags);
	return(ide_config_drive_speed(drive, speed));
}

static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 speed	= ide_rate_filter(drive, xferspeed);
	u8 unit		= (drive->select.b.unit & 0x01);
	u8 tmp1 = 0, tmp2 = 0;
	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
	unsigned long flags;

	local_irq_save(flags);
	/* high 4-bits: Active, low 4-bits: Recovery */
	pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
	drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
	pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);

	pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
	tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
	ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
	tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
	pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
	local_irq_restore(flags);
	return(ide_config_drive_speed(drive, speed));
}

static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
{
	switch (HWIF(drive)->pci_dev->device) {
		case PCI_DEVICE_ID_ARTOP_ATP865:
		case PCI_DEVICE_ID_ARTOP_ATP865R:
		case PCI_DEVICE_ID_ARTOP_ATP860:
		case PCI_DEVICE_ID_ARTOP_ATP860R:
			return ((int) aec6260_tune_chipset(drive, speed));
		case PCI_DEVICE_ID_ARTOP_ATP850UF:
			return ((int) aec6210_tune_chipset(drive, speed));
		default:
			return -1;
	}
}

static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
{
	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
	(void) aec62xx_tune_chipset(drive, pio + XFER_PIO_0);
}

static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
{
	if (ide_tune_dma(drive))
		return 0;

	if (ide_use_fast_pio(drive))
		aec62xx_tune_drive(drive, 255);

	return -1;
}

static void aec62xx_dma_lost_irq (ide_drive_t *drive)
{
	switch (HWIF(drive)->pci_dev->device) {
		case PCI_DEVICE_ID_ARTOP_ATP860:
		case PCI_DEVICE_ID_ARTOP_ATP860R:
		case PCI_DEVICE_ID_ARTOP_ATP865:
		case PCI_DEVICE_ID_ARTOP_ATP865R:
			printk(" AEC62XX time out ");
		default:
			break;
	}
}

static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
{
	int bus_speed = system_bus_clock();

	if (dev->resource[PCI_ROM_RESOURCE].start) {
		pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
		printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
			(unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
	}

	if (bus_speed <= 33)
		pci_set_drvdata(dev, (void *) aec6xxx_33_base);
	else
		pci_set_drvdata(dev, (void *) aec6xxx_34_base);

	/* These are necessary to get AEC6280 Macintosh cards to work */
	if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
	    (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
		u8 reg49h = 0, reg4ah = 0;
		/* Clear reset and test bits.  */
		pci_read_config_byte(dev, 0x49, &reg49h);
		pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
		/* Enable chip interrupt output.  */
		pci_read_config_byte(dev, 0x4a, &reg4ah);
		pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
		/* Enable burst mode. */
		pci_read_config_byte(dev, 0x4a, &reg4ah);
		pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
	}

	return dev->irq;
}

static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
{
	struct pci_dev *dev = hwif->pci_dev;

	hwif->autodma = 0;
	hwif->tuneproc = &aec62xx_tune_drive;
	hwif->speedproc = &aec62xx_tune_chipset;

	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
		hwif->serialized = hwif->channel;

	if (hwif->mate)
		hwif->mate->serialized = hwif->serialized;

	if (!hwif->dma_base) {
		hwif->drives[0].autotune = 1;
		hwif->drives[1].autotune = 1;
		return;
	}

	hwif->ultra_mask = hwif->cds->udma_mask;

	/* atp865 and atp865r */
	if (hwif->ultra_mask == 0x3f) {
		/* check bit 0x10 of DMA status register */
		if (inb(pci_resource_start(dev, 4) + 2) & 0x10)
 			hwif->ultra_mask = 0x7f; /* udma0-6 */
	}

	hwif->mwdma_mask = 0x07;

	hwif->ide_dma_check	= &aec62xx_config_drive_xfer_rate;
	hwif->dma_lost_irq	= &aec62xx_dma_lost_irq;

	if (!noautodma)
		hwif->autodma = 1;
	hwif->drives[0].autodma = hwif->autodma;
	hwif->drives[1].autodma = hwif->autodma;
}

static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase)
{
	struct pci_dev *dev	= hwif->pci_dev;

	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
		u8 reg54h = 0;
		unsigned long flags;

		spin_lock_irqsave(&ide_lock, flags);
		pci_read_config_byte(dev, 0x54, &reg54h);
		pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
		spin_unlock_irqrestore(&ide_lock, flags);
	} else {
		u8 ata66	= 0;
		pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
	        if (!(hwif->udma_four))
			hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
	}

	ide_setup_dma(hwif, dmabase, 8);
}

static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
{
	return ide_setup_pci_device(dev, d);
}

static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
{
	unsigned long bar4reg = pci_resource_start(dev, 4);

	if (inb(bar4reg+2) & 0x10) {
		strcpy(d->name, "AEC6880");
		if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
			strcpy(d->name, "AEC6880R");
	} else {
		strcpy(d->name, "AEC6280");
		if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
			strcpy(d->name, "AEC6280R");
	}

	return ide_setup_pci_device(dev, d);
}

static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "AEC6210",
		.init_setup	= init_setup_aec62xx,
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.init_dma	= init_dma_aec62xx,
		.channels	= 2,
		.autodma	= AUTODMA,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.bootable	= OFF_BOARD,
		.udma_mask	= 0x07, /* udma0-2 */
	},{	/* 1 */
		.name		= "AEC6260",
		.init_setup	= init_setup_aec62xx,
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.init_dma	= init_dma_aec62xx,
		.channels	= 2,
		.autodma	= NOAUTODMA,
		.bootable	= OFF_BOARD,
		.udma_mask	= 0x1f, /* udma0-4 */
	},{	/* 2 */
		.name		= "AEC6260R",
		.init_setup	= init_setup_aec62xx,
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.init_dma	= init_dma_aec62xx,
		.channels	= 2,
		.autodma	= AUTODMA,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.bootable	= NEVER_BOARD,
		.udma_mask	= 0x1f, /* udma0-4 */
	},{	/* 3 */
		.name		= "AEC6X80",
		.init_setup	= init_setup_aec6x80,
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.init_dma	= init_dma_aec62xx,
		.channels	= 2,
		.autodma	= AUTODMA,
		.bootable	= OFF_BOARD,
		.udma_mask	= 0x3f, /* udma0-5 */
	},{	/* 4 */
		.name		= "AEC6X80R",
		.init_setup	= init_setup_aec6x80,
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.init_dma	= init_dma_aec62xx,
		.channels	= 2,
		.autodma	= AUTODMA,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.bootable	= OFF_BOARD,
		.udma_mask	= 0x3f, /* udma0-5 */
	}
};

/**
 *	aec62xx_init_one	-	called when a AEC is found
 *	@dev: the aec62xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];

	return d->init_setup(dev, d);
}

static struct pci_device_id aec62xx_pci_tbl[] = {
	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);

static struct pci_driver driver = {
	.name		= "AEC62xx_IDE",
	.id_table	= aec62xx_pci_tbl,
	.probe		= aec62xx_init_one,
};

static int __init aec62xx_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(aec62xx_ide_init);

MODULE_AUTHOR("Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
826a1b65	2	* linux/drivers/ide/pci/aec62xx.c Version 0.21 Apr 21, 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
826a1b65	5	* Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	6	*
	7	*/
	8
	9	#include <linux/module.h>
1da177e4 LT	10	#include <linux/types.h>
	11	#include <linux/pci.h>
	12	#include <linux/delay.h>
	13	#include <linux/hdreg.h>
	14	#include <linux/ide.h>
	15	#include <linux/init.h>
	16
	17	#include <asm/io.h>
	18
	19	struct chipset_bus_clock_list_entry {
	20	u8 xfer_speed;
	21	u8 chipset_settings;
	22	u8 ultra_settings;
	23	};
	24
f201f504	25	static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
1da177e4 LT	26	{ XFER_UDMA_6, 0x31, 0x07 },
	27	{ XFER_UDMA_5, 0x31, 0x06 },
	28	{ XFER_UDMA_4, 0x31, 0x05 },
	29	{ XFER_UDMA_3, 0x31, 0x04 },
	30	{ XFER_UDMA_2, 0x31, 0x03 },
	31	{ XFER_UDMA_1, 0x31, 0x02 },
	32	{ XFER_UDMA_0, 0x31, 0x01 },
	33
	34	{ XFER_MW_DMA_2, 0x31, 0x00 },
	35	{ XFER_MW_DMA_1, 0x31, 0x00 },
	36	{ XFER_MW_DMA_0, 0x0a, 0x00 },
	37	{ XFER_PIO_4, 0x31, 0x00 },
	38	{ XFER_PIO_3, 0x33, 0x00 },
	39	{ XFER_PIO_2, 0x08, 0x00 },
	40	{ XFER_PIO_1, 0x0a, 0x00 },
	41	{ XFER_PIO_0, 0x00, 0x00 },
	42	{ 0, 0x00, 0x00 }
	43	};
	44
f201f504	45	static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
1da177e4 LT	46	{ XFER_UDMA_6, 0x41, 0x06 },
	47	{ XFER_UDMA_5, 0x41, 0x05 },
	48	{ XFER_UDMA_4, 0x41, 0x04 },
	49	{ XFER_UDMA_3, 0x41, 0x03 },
	50	{ XFER_UDMA_2, 0x41, 0x02 },
	51	{ XFER_UDMA_1, 0x41, 0x01 },
	52	{ XFER_UDMA_0, 0x41, 0x01 },
	53
	54	{ XFER_MW_DMA_2, 0x41, 0x00 },
	55	{ XFER_MW_DMA_1, 0x42, 0x00 },
	56	{ XFER_MW_DMA_0, 0x7a, 0x00 },
	57	{ XFER_PIO_4, 0x41, 0x00 },
	58	{ XFER_PIO_3, 0x43, 0x00 },
	59	{ XFER_PIO_2, 0x78, 0x00 },
	60	{ XFER_PIO_1, 0x7a, 0x00 },
	61	{ XFER_PIO_0, 0x70, 0x00 },
	62	{ 0, 0x00, 0x00 }
	63	};
	64
	65	#define BUSCLOCK(D) \
	66	((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
	67
1da177e4 LT	68
	69	/*
	70	* TO DO: active tuning and correction of cards without a bios.
	71	*/
	72	static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
	73	{
	74	for ( ; chipset_table->xfer_speed ; chipset_table++)
	75	if (chipset_table->xfer_speed == speed) {
	76	return chipset_table->chipset_settings;
	77	}
	78	return chipset_table->chipset_settings;
	79	}
	80
	81	static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
	82	{
	83	for ( ; chipset_table->xfer_speed ; chipset_table++)
	84	if (chipset_table->xfer_speed == speed) {
	85	return chipset_table->ultra_settings;
	86	}
	87	return chipset_table->ultra_settings;
	88	}
	89
1da177e4 LT	90	static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
	91	{
	92	ide_hwif_t *hwif = HWIF(drive);
	93	struct pci_dev *dev = hwif->pci_dev;
	94	u16 d_conf = 0;
2d5eaa6d	95	u8 speed = ide_rate_filter(drive, xferspeed);
1da177e4 LT	96	u8 ultra = 0, ultra_conf = 0;
	97	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
	98	unsigned long flags;
	99
	100	local_irq_save(flags);
	101	/* 0x40\|(2drive->dn): Active, 0x41\|(2drive->dn): Recovery */
	102	pci_read_config_word(dev, 0x40\|(2*drive->dn), &d_conf);
	103	tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
	104	d_conf = ((tmp0 & 0xf0) << 4) \| (tmp0 & 0xf);
	105	pci_write_config_word(dev, 0x40\|(2*drive->dn), d_conf);
	106
	107	tmp1 = 0x00;
	108	tmp2 = 0x00;
	109	pci_read_config_byte(dev, 0x54, &ultra);
	110	tmp1 = ((0x00 << (2drive->dn)) \| (ultra & ~(3 << (2drive->dn))));
	111	ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
	112	tmp2 = ((ultra_conf << (2drive->dn)) \| (tmp1 & ~(3 << (2drive->dn))));
	113	pci_write_config_byte(dev, 0x54, tmp2);
	114	local_irq_restore(flags);
	115	return(ide_config_drive_speed(drive, speed));
	116	}
	117
	118	static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
	119	{
	120	ide_hwif_t *hwif = HWIF(drive);
	121	struct pci_dev *dev = hwif->pci_dev;
2d5eaa6d	122	u8 speed = ide_rate_filter(drive, xferspeed);
1da177e4 LT	123	u8 unit = (drive->select.b.unit & 0x01);
	124	u8 tmp1 = 0, tmp2 = 0;
	125	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
	126	unsigned long flags;
	127
	128	local_irq_save(flags);
	129	/* high 4-bits: Active, low 4-bits: Recovery */
	130	pci_read_config_byte(dev, 0x40\|drive->dn, &drive_conf);
	131	drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
	132	pci_write_config_byte(dev, 0x40\|drive->dn, drive_conf);
	133
	134	pci_read_config_byte(dev, (0x44\|hwif->channel), &ultra);
	135	tmp1 = ((0x00 << (4unit)) \| (ultra & ~(7 << (4unit))));
	136	ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
	137	tmp2 = ((ultra_conf << (4unit)) \| (tmp1 & ~(7 << (4unit))));
	138	pci_write_config_byte(dev, (0x44\|hwif->channel), tmp2);
	139	local_irq_restore(flags);
	140	return(ide_config_drive_speed(drive, speed));
	141	}
	142
	143	static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
	144	{
	145	switch (HWIF(drive)->pci_dev->device) {
	146	case PCI_DEVICE_ID_ARTOP_ATP865:
	147	case PCI_DEVICE_ID_ARTOP_ATP865R:
	148	case PCI_DEVICE_ID_ARTOP_ATP860:
	149	case PCI_DEVICE_ID_ARTOP_ATP860R:
	150	return ((int) aec6260_tune_chipset(drive, speed));
	151	case PCI_DEVICE_ID_ARTOP_ATP850UF:
	152	return ((int) aec6210_tune_chipset(drive, speed));
	153	default:
	154	return -1;
	155	}
	156	}
	157
1da177e4 LT	158	static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
1da177e4 LT	159	{
826a1b65 SS	160	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
826a1b65 SS	161	(void) aec62xx_tune_chipset(drive, pio + XFER_PIO_0);
1da177e4 LT	162	}
	163
	164	static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
	165	{
29e744d0	166	if (ide_tune_dma(drive))
3608b5d7	167	return 0;
1da177e4	168
d8f4469d	169	if (ide_use_fast_pio(drive))
826a1b65	170	aec62xx_tune_drive(drive, 255);
d8f4469d	171
3608b5d7	172	return -1;
1da177e4 LT	173	}
1da177e4 LT	174
841d2a9b	175	static void aec62xx_dma_lost_irq (ide_drive_t *drive)
1da177e4	176	{
841d2a9b	177	switch (HWIF(drive)->pci_dev->device) {
1da177e4 LT	178	case PCI_DEVICE_ID_ARTOP_ATP860:
	179	case PCI_DEVICE_ID_ARTOP_ATP860R:
	180	case PCI_DEVICE_ID_ARTOP_ATP865:
	181	case PCI_DEVICE_ID_ARTOP_ATP865R:
	182	printk(" AEC62XX time out ");
1da177e4 LT	183	default:
	184	break;
	185	}
1da177e4 LT	186	}
	187
	188	static unsigned int __devinit init_chipset_aec62xx(struct pci_dev dev, const char name)
	189	{
	190	int bus_speed = system_bus_clock();
	191
	192	if (dev->resource[PCI_ROM_RESOURCE].start) {
	193	pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start \| PCI_ROM_ADDRESS_ENABLE);
08f46de9 GKH	194	printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
08f46de9 GKH	195	(unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
1da177e4 LT	196	}
	197
	198	if (bus_speed <= 33)
	199	pci_set_drvdata(dev, (void *) aec6xxx_33_base);
	200	else
	201	pci_set_drvdata(dev, (void *) aec6xxx_34_base);
	202
d237bf49 TV	203	/* These are necessary to get AEC6280 Macintosh cards to work */
	204	if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) \|\|
	205	(dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
	206	u8 reg49h = 0, reg4ah = 0;
	207	/* Clear reset and test bits. */
	208	pci_read_config_byte(dev, 0x49, &reg49h);
	209	pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
	210	/* Enable chip interrupt output. */
	211	pci_read_config_byte(dev, 0x4a, &reg4ah);
	212	pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
	213	/* Enable burst mode. */
	214	pci_read_config_byte(dev, 0x4a, &reg4ah);
	215	pci_write_config_byte(dev, 0x4a, reg4ah \| 0x80);
	216	}
	217
1da177e4 LT	218	return dev->irq;
	219	}
	220
	221	static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
	222	{
18137207 BZ	223	struct pci_dev *dev = hwif->pci_dev;
18137207 BZ	224
1da177e4 LT	225	hwif->autodma = 0;
	226	hwif->tuneproc = &aec62xx_tune_drive;
	227	hwif->speedproc = &aec62xx_tune_chipset;
	228
18137207	229	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
1da177e4	230	hwif->serialized = hwif->channel;
1da177e4 LT	231
	232	if (hwif->mate)
	233	hwif->mate->serialized = hwif->serialized;
	234
	235	if (!hwif->dma_base) {
	236	hwif->drives[0].autotune = 1;
	237	hwif->drives[1].autotune = 1;
	238	return;
	239	}
	240
18137207 BZ	241	hwif->ultra_mask = hwif->cds->udma_mask;
	242
	243	/* atp865 and atp865r */
	244	if (hwif->ultra_mask == 0x3f) {
	245	/* check bit 0x10 of DMA status register */
	246	if (inb(pci_resource_start(dev, 4) + 2) & 0x10)
	247	hwif->ultra_mask = 0x7f; /* udma0-6 */
	248	}
	249
1da177e4	250	hwif->mwdma_mask = 0x07;
1da177e4 LT	251
1da177e4 LT	252	hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate;
841d2a9b	253	hwif->dma_lost_irq = &aec62xx_dma_lost_irq;
826a1b65	254
1da177e4 LT	255	if (!noautodma)
	256	hwif->autodma = 1;
	257	hwif->drives[0].autodma = hwif->autodma;
	258	hwif->drives[1].autodma = hwif->autodma;
	259	}
	260
	261	static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase)
	262	{
	263	struct pci_dev *dev = hwif->pci_dev;
	264
	265	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
	266	u8 reg54h = 0;
	267	unsigned long flags;
	268
	269	spin_lock_irqsave(&ide_lock, flags);
	270	pci_read_config_byte(dev, 0x54, &reg54h);
	271	pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
	272	spin_unlock_irqrestore(&ide_lock, flags);
	273	} else {
	274	u8 ata66 = 0;
	275	pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
	276	if (!(hwif->udma_four))
	277	hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
	278	}
	279
	280	ide_setup_dma(hwif, dmabase, 8);
	281	}
	282
	283	static int __devinit init_setup_aec62xx(struct pci_dev dev, ide_pci_device_t d)
	284	{
	285	return ide_setup_pci_device(dev, d);
	286	}
	287
	288	static int __devinit init_setup_aec6x80(struct pci_dev dev, ide_pci_device_t d)
	289	{
	290	unsigned long bar4reg = pci_resource_start(dev, 4);
	291
	292	if (inb(bar4reg+2) & 0x10) {
	293	strcpy(d->name, "AEC6880");
	294	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
	295	strcpy(d->name, "AEC6880R");
	296	} else {
	297	strcpy(d->name, "AEC6280");
	298	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
	299	strcpy(d->name, "AEC6280R");
	300	}
	301
	302	return ide_setup_pci_device(dev, d);
	303	}
	304
	305	static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
	306	{ /* 0 */
	307	.name = "AEC6210",
	308	.init_setup = init_setup_aec62xx,
	309	.init_chipset = init_chipset_aec62xx,
	310	.init_hwif = init_hwif_aec62xx,
	311	.init_dma = init_dma_aec62xx,
	312	.channels = 2,
	313	.autodma = AUTODMA,
	314	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
	315	.bootable = OFF_BOARD,
18137207	316	.udma_mask = 0x07, /* udma0-2 */
1da177e4 LT	317	},{ /* 1 */
	318	.name = "AEC6260",
	319	.init_setup = init_setup_aec62xx,
	320	.init_chipset = init_chipset_aec62xx,
	321	.init_hwif = init_hwif_aec62xx,
	322	.init_dma = init_dma_aec62xx,
	323	.channels = 2,
	324	.autodma = NOAUTODMA,
	325	.bootable = OFF_BOARD,
18137207	326	.udma_mask = 0x1f, /* udma0-4 */
1da177e4 LT	327	},{ /* 2 */
	328	.name = "AEC6260R",
	329	.init_setup = init_setup_aec62xx,
	330	.init_chipset = init_chipset_aec62xx,
	331	.init_hwif = init_hwif_aec62xx,
	332	.init_dma = init_dma_aec62xx,
	333	.channels = 2,
	334	.autodma = AUTODMA,
	335	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
	336	.bootable = NEVER_BOARD,
18137207	337	.udma_mask = 0x1f, /* udma0-4 */
1da177e4 LT	338	},{ /* 3 */
	339	.name = "AEC6X80",
	340	.init_setup = init_setup_aec6x80,
	341	.init_chipset = init_chipset_aec62xx,
	342	.init_hwif = init_hwif_aec62xx,
	343	.init_dma = init_dma_aec62xx,
	344	.channels = 2,
	345	.autodma = AUTODMA,
	346	.bootable = OFF_BOARD,
18137207	347	.udma_mask = 0x3f, /* udma0-5 */
1da177e4 LT	348	},{ /* 4 */
	349	.name = "AEC6X80R",
	350	.init_setup = init_setup_aec6x80,
	351	.init_chipset = init_chipset_aec62xx,
	352	.init_hwif = init_hwif_aec62xx,
	353	.init_dma = init_dma_aec62xx,
	354	.channels = 2,
	355	.autodma = AUTODMA,
	356	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
	357	.bootable = OFF_BOARD,
18137207	358	.udma_mask = 0x3f, /* udma0-5 */
1da177e4 LT	359	}
	360	};
	361
	362	/**
	363	* aec62xx_init_one - called when a AEC is found
	364	* @dev: the aec62xx device
	365	* @id: the matching pci id
	366	*
	367	* Called when the PCI registration layer (or the IDE initialization)
	368	* finds a device matching our IDE device tables.
	369	*/
	370
	371	static int __devinit aec62xx_init_one(struct pci_dev dev, const struct pci_device_id id)
	372	{
	373	ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];
	374
	375	return d->init_setup(dev, d);
	376	}
	377
28a2a3f5 AC	378	static struct pci_device_id aec62xx_pci_tbl[] = {
	379	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	380	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
	381	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
	382	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
	383	{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
1da177e4 LT	384	{ 0, },
	385	};
	386	MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
	387
	388	static struct pci_driver driver = {
	389	.name = "AEC62xx_IDE",
	390	.id_table = aec62xx_pci_tbl,
	391	.probe = aec62xx_init_one,
	392	};
	393
82ab1eec	394	static int __init aec62xx_ide_init(void)
1da177e4 LT	395	{
	396	return ide_pci_register_driver(&driver);
	397	}
	398
	399	module_init(aec62xx_ide_init);
	400
	401	MODULE_AUTHOR("Andre Hedrick");
	402	MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
	403	MODULE_LICENSE("GPL");