[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / pci / aec62xx.c

/*
 * linux/drivers/ide/pci/aec62xx.c		Version 0.27	Sep 16, 2007
 *
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2007		MontaVista Software, Inc. <source@mvista.com>
 *
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

struct chipset_bus_clock_list_entry {
	u8 xfer_speed;
	u8 chipset_settings;
	u8 ultra_settings;
};

static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
	{	XFER_UDMA_6,	0x31,	0x07	},
	{	XFER_UDMA_5,	0x31,	0x06	},
	{	XFER_UDMA_4,	0x31,	0x05	},
	{	XFER_UDMA_3,	0x31,	0x04	},
	{	XFER_UDMA_2,	0x31,	0x03	},
	{	XFER_UDMA_1,	0x31,	0x02	},
	{	XFER_UDMA_0,	0x31,	0x01	},

	{	XFER_MW_DMA_2,	0x31,	0x00	},
	{	XFER_MW_DMA_1,	0x31,	0x00	},
	{	XFER_MW_DMA_0,	0x0a,	0x00	},
	{	XFER_PIO_4,	0x31,	0x00	},
	{	XFER_PIO_3,	0x33,	0x00	},
	{	XFER_PIO_2,	0x08,	0x00	},
	{	XFER_PIO_1,	0x0a,	0x00	},
	{	XFER_PIO_0,	0x00,	0x00	},
	{	0,		0x00,	0x00	}
};

static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
	{	XFER_UDMA_6,	0x41,	0x06	},
	{	XFER_UDMA_5,	0x41,	0x05	},
	{	XFER_UDMA_4,	0x41,	0x04	},
	{	XFER_UDMA_3,	0x41,	0x03	},
	{	XFER_UDMA_2,	0x41,	0x02	},
	{	XFER_UDMA_1,	0x41,	0x01	},
	{	XFER_UDMA_0,	0x41,	0x01	},

	{	XFER_MW_DMA_2,	0x41,	0x00	},
	{	XFER_MW_DMA_1,	0x42,	0x00	},
	{	XFER_MW_DMA_0,	0x7a,	0x00	},
	{	XFER_PIO_4,	0x41,	0x00	},
	{	XFER_PIO_3,	0x43,	0x00	},
	{	XFER_PIO_2,	0x78,	0x00	},
	{	XFER_PIO_1,	0x7a,	0x00	},
	{	XFER_PIO_0,	0x70,	0x00	},
	{	0,		0x00,	0x00	}
};

#define BUSCLOCK(D)	\
	((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))


/*
 * TO DO: active tuning and correction of cards without a bios.
 */
static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
{
	for ( ; chipset_table->xfer_speed ; chipset_table++)
		if (chipset_table->xfer_speed == speed) {
			return chipset_table->chipset_settings;
		}
	return chipset_table->chipset_settings;
}

static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
{
	for ( ; chipset_table->xfer_speed ; chipset_table++)
		if (chipset_table->xfer_speed == speed) {
			return chipset_table->ultra_settings;
		}
	return chipset_table->ultra_settings;
}

static void aec6210_set_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u16 d_conf		= 0;
	u8 ultra = 0, ultra_conf = 0;
	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
	unsigned long flags;

	local_irq_save(flags);
	/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
	pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
	tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
	d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
	pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);

	tmp1 = 0x00;
	tmp2 = 0x00;
	pci_read_config_byte(dev, 0x54, &ultra);
	tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
	ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
	tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
	pci_write_config_byte(dev, 0x54, tmp2);
	local_irq_restore(flags);
}

static void aec6260_set_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;
	u8 unit		= (drive->select.b.unit & 0x01);
	u8 tmp1 = 0, tmp2 = 0;
	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
	unsigned long flags;

	local_irq_save(flags);
	/* high 4-bits: Active, low 4-bits: Recovery */
	pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
	drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
	pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);

	pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
	tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
	ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
	tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
	pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
	local_irq_restore(flags);
}

static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	drive->hwif->set_dma_mode(drive, pio + XFER_PIO_0);
}

static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
{
	int bus_speed = system_bus_clock();

	if (bus_speed <= 33)
		pci_set_drvdata(dev, (void *) aec6xxx_33_base);
	else
		pci_set_drvdata(dev, (void *) aec6xxx_34_base);

	/* These are necessary to get AEC6280 Macintosh cards to work */
	if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
	    (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
		u8 reg49h = 0, reg4ah = 0;
		/* Clear reset and test bits.  */
		pci_read_config_byte(dev, 0x49, &reg49h);
		pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
		/* Enable chip interrupt output.  */
		pci_read_config_byte(dev, 0x4a, &reg4ah);
		pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
		/* Enable burst mode. */
		pci_read_config_byte(dev, 0x4a, &reg4ah);
		pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
	}

	return dev->irq;
}

static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= hwif->pci_dev;

	hwif->set_pio_mode = &aec_set_pio_mode;

	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
		hwif->set_dma_mode = &aec6210_set_mode;
	else
		hwif->set_dma_mode = &aec6260_set_mode;

	if (hwif->dma_base == 0)
		return;

	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
		return;

	if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
		u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;

		pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);

		hwif->cbl = (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
	}
}

static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
	{	/* 0 */
		.name		= "AEC6210",
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.host_flags	= IDE_HFLAG_SERIALIZE |
				  IDE_HFLAG_NO_ATAPI_DMA |
				  IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},{	/* 1 */
		.name		= "AEC6260",
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
				  IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA4,
	},{	/* 2 */
		.name		= "AEC6260R",
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA4,
	},{	/* 3 */
		.name		= "AEC6280",
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},{	/* 4 */
		.name		= "AEC6280R",
		.init_chipset	= init_chipset_aec62xx,
		.init_hwif	= init_hwif_aec62xx,
		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_OFF_BOARD,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	}
};

/**
 *	aec62xx_init_one	-	called when a AEC is found
 *	@dev: the aec62xx device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 *
 *	NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
 *	chips, pass a local copy of 'struct ide_port_info' down the call chain.
 */

static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d;
	u8 idx = id->driver_data;

	d = aec62xx_chipsets[idx];

	if (idx == 3 || idx == 4) {
		unsigned long dma_base = pci_resource_start(dev, 4);

		if (inb(dma_base + 2) & 0x10) {
			d.name = (idx == 4) ? "AEC6880R" : "AEC6880";
			d.udma_mask = ATA_UDMA6;
		}
	}

	return ide_setup_pci_device(dev, &d);
}

static const struct pci_device_id aec62xx_pci_tbl[] = {
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860),   1 },
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R),  2 },
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865),   3 },
	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R),  4 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);

static struct pci_driver driver = {
	.name		= "AEC62xx_IDE",
	.id_table	= aec62xx_pci_tbl,
	.probe		= aec62xx_init_one,
};

static int __init aec62xx_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(aec62xx_ide_init);

MODULE_AUTHOR("Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
b1e03865	2	* linux/drivers/ide/pci/aec62xx.c Version 0.27 Sep 16, 2007
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
826a1b65	5	* Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	6	*
	7	*/
	8
	9	#include <linux/module.h>
1da177e4 LT	10	#include <linux/types.h>
	11	#include <linux/pci.h>
	12	#include <linux/delay.h>
	13	#include <linux/hdreg.h>
	14	#include <linux/ide.h>
	15	#include <linux/init.h>
	16
	17	#include <asm/io.h>
	18
	19	struct chipset_bus_clock_list_entry {
	20	u8 xfer_speed;
	21	u8 chipset_settings;
	22	u8 ultra_settings;
	23	};
	24
f201f504	25	static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
1da177e4 LT	26	{ XFER_UDMA_6, 0x31, 0x07 },
	27	{ XFER_UDMA_5, 0x31, 0x06 },
	28	{ XFER_UDMA_4, 0x31, 0x05 },
	29	{ XFER_UDMA_3, 0x31, 0x04 },
	30	{ XFER_UDMA_2, 0x31, 0x03 },
	31	{ XFER_UDMA_1, 0x31, 0x02 },
	32	{ XFER_UDMA_0, 0x31, 0x01 },
	33
	34	{ XFER_MW_DMA_2, 0x31, 0x00 },
	35	{ XFER_MW_DMA_1, 0x31, 0x00 },
	36	{ XFER_MW_DMA_0, 0x0a, 0x00 },
	37	{ XFER_PIO_4, 0x31, 0x00 },
	38	{ XFER_PIO_3, 0x33, 0x00 },
	39	{ XFER_PIO_2, 0x08, 0x00 },
	40	{ XFER_PIO_1, 0x0a, 0x00 },
	41	{ XFER_PIO_0, 0x00, 0x00 },
	42	{ 0, 0x00, 0x00 }
	43	};
	44
f201f504	45	static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
1da177e4 LT	46	{ XFER_UDMA_6, 0x41, 0x06 },
	47	{ XFER_UDMA_5, 0x41, 0x05 },
	48	{ XFER_UDMA_4, 0x41, 0x04 },
	49	{ XFER_UDMA_3, 0x41, 0x03 },
	50	{ XFER_UDMA_2, 0x41, 0x02 },
	51	{ XFER_UDMA_1, 0x41, 0x01 },
	52	{ XFER_UDMA_0, 0x41, 0x01 },
	53
	54	{ XFER_MW_DMA_2, 0x41, 0x00 },
	55	{ XFER_MW_DMA_1, 0x42, 0x00 },
	56	{ XFER_MW_DMA_0, 0x7a, 0x00 },
	57	{ XFER_PIO_4, 0x41, 0x00 },
	58	{ XFER_PIO_3, 0x43, 0x00 },
	59	{ XFER_PIO_2, 0x78, 0x00 },
	60	{ XFER_PIO_1, 0x7a, 0x00 },
	61	{ XFER_PIO_0, 0x70, 0x00 },
	62	{ 0, 0x00, 0x00 }
	63	};
	64
	65	#define BUSCLOCK(D) \
	66	((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
	67
1da177e4 LT	68
	69	/*
	70	* TO DO: active tuning and correction of cards without a bios.
	71	*/
	72	static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
	73	{
	74	for ( ; chipset_table->xfer_speed ; chipset_table++)
	75	if (chipset_table->xfer_speed == speed) {
	76	return chipset_table->chipset_settings;
	77	}
	78	return chipset_table->chipset_settings;
	79	}
	80
	81	static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
	82	{
	83	for ( ; chipset_table->xfer_speed ; chipset_table++)
	84	if (chipset_table->xfer_speed == speed) {
	85	return chipset_table->ultra_settings;
	86	}
	87	return chipset_table->ultra_settings;
	88	}
	89
88b2b32b	90	static void aec6210_set_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	91	{
	92	ide_hwif_t *hwif = HWIF(drive);
	93	struct pci_dev *dev = hwif->pci_dev;
	94	u16 d_conf = 0;
1da177e4 LT	95	u8 ultra = 0, ultra_conf = 0;
	96	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
	97	unsigned long flags;
	98
	99	local_irq_save(flags);
	100	/* 0x40\|(2drive->dn): Active, 0x41\|(2drive->dn): Recovery */
	101	pci_read_config_word(dev, 0x40\|(2*drive->dn), &d_conf);
	102	tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
	103	d_conf = ((tmp0 & 0xf0) << 4) \| (tmp0 & 0xf);
	104	pci_write_config_word(dev, 0x40\|(2*drive->dn), d_conf);
	105
	106	tmp1 = 0x00;
	107	tmp2 = 0x00;
	108	pci_read_config_byte(dev, 0x54, &ultra);
	109	tmp1 = ((0x00 << (2drive->dn)) \| (ultra & ~(3 << (2drive->dn))));
	110	ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
	111	tmp2 = ((ultra_conf << (2drive->dn)) \| (tmp1 & ~(3 << (2drive->dn))));
	112	pci_write_config_byte(dev, 0x54, tmp2);
	113	local_irq_restore(flags);
1da177e4 LT	114	}
1da177e4 LT	115
88b2b32b	116	static void aec6260_set_mode(ide_drive_t *drive, const u8 speed)
1da177e4 LT	117	{
	118	ide_hwif_t *hwif = HWIF(drive);
	119	struct pci_dev *dev = hwif->pci_dev;
1da177e4 LT	120	u8 unit = (drive->select.b.unit & 0x01);
	121	u8 tmp1 = 0, tmp2 = 0;
	122	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
	123	unsigned long flags;
	124
	125	local_irq_save(flags);
	126	/* high 4-bits: Active, low 4-bits: Recovery */
	127	pci_read_config_byte(dev, 0x40\|drive->dn, &drive_conf);
	128	drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
	129	pci_write_config_byte(dev, 0x40\|drive->dn, drive_conf);
	130
	131	pci_read_config_byte(dev, (0x44\|hwif->channel), &ultra);
	132	tmp1 = ((0x00 << (4unit)) \| (ultra & ~(7 << (4unit))));
	133	ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
	134	tmp2 = ((ultra_conf << (4unit)) \| (tmp1 & ~(7 << (4unit))));
	135	pci_write_config_byte(dev, (0x44\|hwif->channel), tmp2);
	136	local_irq_restore(flags);
1da177e4 LT	137	}
1da177e4 LT	138
26bcb879	139	static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	140	{
88b2b32b	141	drive->hwif->set_dma_mode(drive, pio + XFER_PIO_0);
1da177e4 LT	142	}
1da177e4 LT	143
1da177e4 LT	144	static unsigned int __devinit init_chipset_aec62xx(struct pci_dev dev, const char name)
	145	{
	146	int bus_speed = system_bus_clock();
	147
1da177e4 LT	148	if (bus_speed <= 33)
	149	pci_set_drvdata(dev, (void *) aec6xxx_33_base);
	150	else
	151	pci_set_drvdata(dev, (void *) aec6xxx_34_base);
	152
d237bf49 TV	153	/* These are necessary to get AEC6280 Macintosh cards to work */
	154	if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) \|\|
	155	(dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
	156	u8 reg49h = 0, reg4ah = 0;
	157	/* Clear reset and test bits. */
	158	pci_read_config_byte(dev, 0x49, &reg49h);
	159	pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
	160	/* Enable chip interrupt output. */
	161	pci_read_config_byte(dev, 0x4a, &reg4ah);
	162	pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
	163	/* Enable burst mode. */
	164	pci_read_config_byte(dev, 0x4a, &reg4ah);
	165	pci_write_config_byte(dev, 0x4a, reg4ah \| 0x80);
	166	}
	167
1da177e4 LT	168	return dev->irq;
	169	}
	170
	171	static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
	172	{
1b9da32a	173	struct pci_dev *dev = hwif->pci_dev;
18137207	174
26bcb879	175	hwif->set_pio_mode = &aec_set_pio_mode;
1da177e4	176
1c51361a	177	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
88b2b32b	178	hwif->set_dma_mode = &aec6210_set_mode;
1c51361a	179	else
88b2b32b	180	hwif->set_dma_mode = &aec6260_set_mode;
1da177e4	181
bc46b17d	182	if (hwif->dma_base == 0)
1da177e4	183	return;
1da177e4	184
6a7f62af BZ	185	if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
	186	return;
	187
	188	if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
1b9da32a SS	189	u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
1b9da32a SS	190
1da177e4	191	pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
49521f97 BZ	192
49521f97 BZ	193	hwif->cbl = (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1da177e4	194	}
1da177e4 LT	195	}
1da177e4 LT	196
85620436	197	static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
1da177e4 LT	198	{ /* 0 */
1da177e4 LT	199	.name = "AEC6210",
1da177e4 LT	200	.init_chipset = init_chipset_aec62xx,
1da177e4 LT	201	.init_hwif = init_hwif_aec62xx,
1da177e4	202	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
1c51361a BZ	203	.host_flags = IDE_HFLAG_SERIALIZE \|
	204	IDE_HFLAG_NO_ATAPI_DMA \|
	205	IDE_HFLAG_OFF_BOARD,
4099d143	206	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	207	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	208	.udma_mask = ATA_UDMA2,
1da177e4 LT	209	},{ /* 1 */
1da177e4 LT	210	.name = "AEC6260",
1da177e4 LT	211	.init_chipset = init_chipset_aec62xx,
1da177e4 LT	212	.init_hwif = init_hwif_aec62xx,
47b68788 BZ	213	.host_flags = IDE_HFLAG_NO_ATAPI_DMA \| IDE_HFLAG_NO_AUTODMA \|
47b68788 BZ	214	IDE_HFLAG_OFF_BOARD,
4099d143	215	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	216	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	217	.udma_mask = ATA_UDMA4,
1da177e4 LT	218	},{ /* 2 */
1da177e4 LT	219	.name = "AEC6260R",
1da177e4 LT	220	.init_chipset = init_chipset_aec62xx,
1da177e4 LT	221	.init_hwif = init_hwif_aec62xx,
1da177e4	222	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
33c1002e	223	.host_flags = IDE_HFLAG_NO_ATAPI_DMA,
4099d143	224	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	225	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	226	.udma_mask = ATA_UDMA4,
1da177e4	227	},{ /* 3 */
b1d19db4	228	.name = "AEC6280",
1da177e4 LT	229	.init_chipset = init_chipset_aec62xx,
1da177e4 LT	230	.init_hwif = init_hwif_aec62xx,
7cab14a7	231	.host_flags = IDE_HFLAG_NO_ATAPI_DMA \| IDE_HFLAG_OFF_BOARD,
4099d143	232	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	233	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	234	.udma_mask = ATA_UDMA5,
1da177e4	235	},{ /* 4 */
b1d19db4	236	.name = "AEC6280R",
1da177e4 LT	237	.init_chipset = init_chipset_aec62xx,
1da177e4 LT	238	.init_hwif = init_hwif_aec62xx,
1da177e4	239	.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
7cab14a7	240	.host_flags = IDE_HFLAG_NO_ATAPI_DMA \| IDE_HFLAG_OFF_BOARD,
4099d143	241	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	242	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	243	.udma_mask = ATA_UDMA5,
1da177e4 LT	244	}
	245	};
	246
	247	/**
	248	* aec62xx_init_one - called when a AEC is found
	249	* @dev: the aec62xx device
	250	* @id: the matching pci id
	251	*
	252	* Called when the PCI registration layer (or the IDE initialization)
	253	* finds a device matching our IDE device tables.
b1d19db4 SS	254	*
b1d19db4 SS	255	* NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
039788e1	256	* chips, pass a local copy of 'struct ide_port_info' down the call chain.
1da177e4	257	*/
039788e1	258
1da177e4 LT	259	static int __devinit aec62xx_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4 LT	260	{
039788e1	261	struct ide_port_info d;
df95f5ab BZ	262	u8 idx = id->driver_data;
	263
	264	d = aec62xx_chipsets[idx];
	265
	266	if (idx == 3 \|\| idx == 4) {
	267	unsigned long dma_base = pci_resource_start(dev, 4);
	268
	269	if (inb(dma_base + 2) & 0x10) {
	270	d.name = (idx == 4) ? "AEC6880R" : "AEC6880";
	271	d.udma_mask = ATA_UDMA6;
	272	}
	273	}
1da177e4	274
df95f5ab	275	return ide_setup_pci_device(dev, &d);
1da177e4 LT	276	}
1da177e4 LT	277
9cbcc5e3 BZ	278	static const struct pci_device_id aec62xx_pci_tbl[] = {
	279	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
	280	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860), 1 },
	281	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R), 2 },
	282	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865), 3 },
	283	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R), 4 },
1da177e4 LT	284	{ 0, },
	285	};
	286	MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
	287
	288	static struct pci_driver driver = {
	289	.name = "AEC62xx_IDE",
	290	.id_table = aec62xx_pci_tbl,
	291	.probe = aec62xx_init_one,
	292	};
	293
82ab1eec	294	static int __init aec62xx_ide_init(void)
1da177e4 LT	295	{
	296	return ide_pci_register_driver(&driver);
	297	}
	298
	299	module_init(aec62xx_ide_init);
	300
	301	MODULE_AUTHOR("Andre Hedrick");
	302	MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
	303	MODULE_LICENSE("GPL");