[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / ide / legacy / q40ide.c

/*
 *  Q40 I/O port IDE Driver
 *
 *     (c) Richard Zidlicky
 *
 *  This file is subject to the terms and conditions of the GNU General Public
 *  License.  See the file COPYING in the main directory of this archive for
 *  more details.
 *
 *
 */

#include <linux/types.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>

#include <linux/ide.h>

    /*
     *  Bases of the IDE interfaces
     */

#define Q40IDE_NUM_HWIFS	2

#define PCIDE_BASE1	0x1f0
#define PCIDE_BASE2	0x170
#define PCIDE_BASE3	0x1e8
#define PCIDE_BASE4	0x168
#define PCIDE_BASE5	0x1e0
#define PCIDE_BASE6	0x160

static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
    PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4  , PCIDE_BASE5,
    PCIDE_BASE6 */
};

static int q40ide_default_irq(unsigned long base)
{
           switch (base) {
	            case 0x1f0: return 14;
		    case 0x170: return 15;
		    case 0x1e8: return 11;
		    default:
			return 0;
	   }
}


/*
 * Addresses are pretranslated for Q40 ISA access.
 */
static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base,
			ide_ack_intr_t *ack_intr,
			int irq)
{
	memset(hw, 0, sizeof(hw_regs_t));
	/* BIG FAT WARNING: 
	   assumption: only DATA port is ever used in 16 bit mode */
	hw->io_ports.data_addr = Q40_ISA_IO_W(base);
	hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
	hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
	hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
	hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
	hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
	hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
	hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
	hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);

	hw->irq = irq;
	hw->ack_intr = ack_intr;

	hw->chipset = ide_generic;
}

static void q40ide_input_data(ide_drive_t *drive, struct request *rq,
			      void *buf, unsigned int len)
{
	unsigned long data_addr = drive->hwif->io_ports.data_addr;

	if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
		return insw(data_addr, buf, (len + 1) / 2);

	insw_swapw(data_addr, buf, (len + 1) / 2);
}

static void q40ide_output_data(ide_drive_t *drive, struct request *rq,
			       void *buf, unsigned int len)
{
	unsigned long data_addr = drive->hwif->io_ports.data_addr;

	if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
		return outsw(data_addr, buf, (len + 1) / 2);

	outsw_swapw(data_addr, buf, (len + 1) / 2);
}

/* Q40 has a byte-swapped IDE interface */
static const struct ide_tp_ops q40ide_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= ide_read_status,
	.read_altstatus		= ide_read_altstatus,
	.read_sff_dma_status	= ide_read_sff_dma_status,

	.set_irq		= ide_set_irq,

	.tf_load		= ide_tf_load,
	.tf_read		= ide_tf_read,

	.input_data		= q40ide_input_data,
	.output_data		= q40ide_output_data,
};

static const struct ide_port_info q40ide_port_info = {
	.tp_ops			= &q40ide_tp_ops,
	.host_flags		= IDE_HFLAG_NO_DMA,
};

/* 
 * the static array is needed to have the name reported in /proc/ioports,
 * hwif->name unfortunately isn't available yet
 */
static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
	"ide0", "ide1"
};

/*
 *  Probe for Q40 IDE interfaces
 */

static int __init q40ide_init(void)
{
    int i;
    ide_hwif_t *hwif;
    hw_regs_t hw[Q40IDE_NUM_HWIFS], *hws[] = { NULL, NULL, NULL, NULL };
    u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };

    if (!MACH_IS_Q40)
      return -ENODEV;

    printk(KERN_INFO "ide: Q40 IDE controller\n");

    for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
	const char *name = q40_ide_names[i];

	if (!request_region(pcide_bases[i], 8, name)) {
		printk("could not reserve ports %lx-%lx for %s\n",
		       pcide_bases[i],pcide_bases[i]+8,name);
		continue;
	}
	if (!request_region(pcide_bases[i]+0x206, 1, name)) {
		printk("could not reserve port %lx for %s\n",
		       pcide_bases[i]+0x206,name);
		release_region(pcide_bases[i], 8);
		continue;
	}
	q40_ide_setup_ports(&hw[i], pcide_bases[i], NULL,
			q40ide_default_irq(pcide_bases[i]));

	hwif = ide_find_port();
	if (hwif) {
		hwif->chipset = ide_generic;

		hws[i] = &hw[i];
		idx[i] = hwif->index;
	}
    }

    ide_device_add(idx, &q40ide_port_info, hws);

    return 0;
}

module_init(q40ide_init);

MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
58f189fc	2	* Q40 I/O port IDE Driver
1da177e4 LT	3	*
	4	* (c) Richard Zidlicky
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file COPYING in the main directory of this archive for
	8	* more details.
	9	*
	10	*
	11	*/
	12
	13	#include <linux/types.h>
	14	#include <linux/mm.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/blkdev.h>
	17	#include <linux/hdreg.h>
	18
	19	#include <linux/ide.h>
	20
	21	/*
	22	* Bases of the IDE interfaces
	23	*/
	24
	25	#define Q40IDE_NUM_HWIFS 2
	26
	27	#define PCIDE_BASE1 0x1f0
	28	#define PCIDE_BASE2 0x170
	29	#define PCIDE_BASE3 0x1e8
	30	#define PCIDE_BASE4 0x168
	31	#define PCIDE_BASE5 0x1e0
	32	#define PCIDE_BASE6 0x160
	33
	34	static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
	35	PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4 , PCIDE_BASE5,
	36	PCIDE_BASE6 */
	37	};
	38
1da177e4 LT	39	static int q40ide_default_irq(unsigned long base)
	40	{
	41	switch (base) {
	42	case 0x1f0: return 14;
	43	case 0x170: return 15;
	44	case 0x1e8: return 11;
	45	default:
	46	return 0;
	47	}
	48	}
	49
	50
	51	/*
29dd5975	52	* Addresses are pretranslated for Q40 ISA access.
1da177e4	53	*/
d28aa3ac	54	static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base,
1da177e4	55	ide_ack_intr_t *ack_intr,
1da177e4 LT	56	int irq)
1da177e4 LT	57	{
2c3e0262	58	memset(hw, 0, sizeof(hw_regs_t));
d28aa3ac AV	59	/* BIG FAT WARNING:
	60	assumption: only DATA port is ever used in 16 bit mode */
	61	hw->io_ports.data_addr = Q40_ISA_IO_W(base);
	62	hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1);
	63	hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2);
	64	hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3);
	65	hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4);
	66	hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5);
	67	hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6);
	68	hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7);
	69	hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206);
86f3a492	70
1da177e4	71	hw->irq = irq;
1da177e4	72	hw->ack_intr = ack_intr;
d427e836 BZ	73
d427e836 BZ	74	hw->chipset = ide_generic;
1da177e4 LT	75	}
1da177e4 LT	76
9567b349 BZ	77	static void q40ide_input_data(ide_drive_t drive, struct request rq,
9567b349 BZ	78	void *buf, unsigned int len)
92d3ab27	79	{
9567b349	80	unsigned long data_addr = drive->hwif->io_ports.data_addr;
92d3ab27	81
92d3ab27	82	if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
9567b349	83	return insw(data_addr, buf, (len + 1) / 2);
92d3ab27	84
9567b349	85	insw_swapw(data_addr, buf, (len + 1) / 2);
92d3ab27 BZ	86	}
92d3ab27 BZ	87
9567b349 BZ	88	static void q40ide_output_data(ide_drive_t drive, struct request rq,
9567b349 BZ	89	void *buf, unsigned int len)
92d3ab27	90	{
9567b349 BZ	91	unsigned long data_addr = drive->hwif->io_ports.data_addr;
9567b349 BZ	92
92d3ab27	93	if (drive->media == ide_disk && rq && rq->cmd_type == REQ_TYPE_FS)
9567b349	94	return outsw(data_addr, buf, (len + 1) / 2);
92d3ab27	95
9567b349	96	outsw_swapw(data_addr, buf, (len + 1) / 2);
92d3ab27	97	}
1da177e4	98
374e042c BZ	99	/* Q40 has a byte-swapped IDE interface */
	100	static const struct ide_tp_ops q40ide_tp_ops = {
	101	.exec_command = ide_exec_command,
	102	.read_status = ide_read_status,
	103	.read_altstatus = ide_read_altstatus,
	104	.read_sff_dma_status = ide_read_sff_dma_status,
	105
	106	.set_irq = ide_set_irq,
	107
	108	.tf_load = ide_tf_load,
	109	.tf_read = ide_tf_read,
	110
	111	.input_data = q40ide_input_data,
	112	.output_data = q40ide_output_data,
	113	};
	114
	115	static const struct ide_port_info q40ide_port_info = {
	116	.tp_ops = &q40ide_tp_ops,
	117	.host_flags = IDE_HFLAG_NO_DMA,
	118	};
	119
1da177e4 LT	120	/*
1da177e4 LT	121	* the static array is needed to have the name reported in /proc/ioports,
96de0e25	122	* hwif->name unfortunately isn't available yet
1da177e4 LT	123	*/
	124	static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
	125	"ide0", "ide1"
	126	};
	127
	128	/*
	129	* Probe for Q40 IDE interfaces
	130	*/
	131
ade2daf9	132	static int __init q40ide_init(void)
1da177e4 LT	133	{
	134	int i;
	135	ide_hwif_t *hwif;
c97c6aca	136	hw_regs_t hw[Q40IDE_NUM_HWIFS], *hws[] = { NULL, NULL, NULL, NULL };
8ac4ce74	137	u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
1da177e4 LT	138
1da177e4 LT	139	if (!MACH_IS_Q40)
ade2daf9	140	return -ENODEV;
1da177e4	141
c99c92c5 BZ	142	printk(KERN_INFO "ide: Q40 IDE controller\n");
c99c92c5 BZ	143
1da177e4	144	for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
c97c6aca	145	const char *name = q40_ide_names[i];
1da177e4	146
1da177e4 LT	147	if (!request_region(pcide_bases[i], 8, name)) {
	148	printk("could not reserve ports %lx-%lx for %s\n",
	149	pcide_bases[i],pcide_bases[i]+8,name);
	150	continue;
	151	}
	152	if (!request_region(pcide_bases[i]+0x206, 1, name)) {
	153	printk("could not reserve port %lx for %s\n",
	154	pcide_bases[i]+0x206,name);
	155	release_region(pcide_bases[i], 8);
	156	continue;
	157	}
c97c6aca	158	q40_ide_setup_ports(&hw[i], pcide_bases[i], NULL,
1da177e4	159	q40ide_default_irq(pcide_bases[i]));
cbb010c1	160
59bff5ba	161	hwif = ide_find_port();
cbb010c1	162	if (hwif) {
c97c6aca	163	hwif->chipset = ide_generic;
8ac4ce74	164
c97c6aca	165	hws[i] = &hw[i];
8ac4ce74	166	idx[i] = hwif->index;
cbb010c1	167	}
1da177e4	168	}
8ac4ce74	169
374e042c	170	ide_device_add(idx, &q40ide_port_info, hws);
ade2daf9 BZ	171
ade2daf9 BZ	172	return 0;
1da177e4 LT	173	}
1da177e4 LT	174
ade2daf9	175	module_init(q40ide_init);
f743d04d AB	176
f743d04d AB	177	MODULE_LICENSE("GPL");