[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / ide-generic.c

/*
 * generic/default IDE host driver
 *
 * Copyright (C) 2004, 2008 Bartlomiej Zolnierkiewicz
 * This code was split off from ide.c.  See it for original copyrights.
 *
 * May be copied or modified under the terms of the GNU General Public License.
 */

/*
 * For special cases new interfaces may be added using sysfs, i.e.
 *
 *	echo -n "0x168:0x36e:10" > /sys/class/ide_generic/add
 *
 * will add an interface using I/O ports 0x168-0x16f/0x36e and IRQ 10.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/ide.h>
#include <linux/pci_ids.h>

/* FIXME: convert m32r to use ide_platform host driver */
#ifdef CONFIG_M32R
#include <asm/m32r.h>
#endif

#define DRV_NAME	"ide_generic"

static int probe_mask;
module_param(probe_mask, int, 0);
MODULE_PARM_DESC(probe_mask, "probe mask for legacy ISA IDE ports");

static ssize_t store_add(struct class *cls, const char *buf, size_t n)
{
	unsigned int base, ctl;
	int irq, rc;
	hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };

	if (sscanf(buf, "%x:%x:%d", &base, &ctl, &irq) != 3)
		return -EINVAL;

	memset(&hw, 0, sizeof(hw));
	ide_std_init_ports(&hw, base, ctl);
	hw.irq = irq;
	hw.chipset = ide_generic;

	rc = ide_host_add(NULL, hws, NULL);
	if (rc)
		return rc;

	return n;
};

static struct class_attribute ide_generic_class_attrs[] = {
	__ATTR(add, S_IWUSR, NULL, store_add),
	__ATTR_NULL
};

static void ide_generic_class_release(struct class *cls)
{
	kfree(cls);
}

static int __init ide_generic_sysfs_init(void)
{
	struct class *cls;
	int rc;

	cls = kzalloc(sizeof(*cls), GFP_KERNEL);
	if (!cls)
		return -ENOMEM;

	cls->name = DRV_NAME;
	cls->owner = THIS_MODULE;
	cls->class_release = ide_generic_class_release;
	cls->class_attrs = ide_generic_class_attrs;

	rc = class_register(cls);
	if (rc) {
		kfree(cls);
		return rc;
	}

	return 0;
}

#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_MAPPI2) \
	|| defined(CONFIG_PLAT_OPSPUT)
static const u16 legacy_bases[] = { 0x1f0 };
static const int legacy_irqs[]  = { PLD_IRQ_CFIREQ };
#elif defined(CONFIG_PLAT_MAPPI3)
static const u16 legacy_bases[] = { 0x1f0, 0x170 };
static const int legacy_irqs[]  = { PLD_IRQ_CFIREQ, PLD_IRQ_IDEIREQ };
#elif defined(CONFIG_ALPHA)
static const u16 legacy_bases[] = { 0x1f0, 0x170, 0x1e8, 0x168 };
static const int legacy_irqs[]  = { 14, 15, 11, 10 };
#else
static const u16 legacy_bases[] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
static const int legacy_irqs[]  = { 14, 15, 11, 10, 8, 12 };
#endif

static void ide_generic_check_pci_legacy_iobases(int *primary, int *secondary)
{
	struct pci_dev *p = NULL;
	u16 val;

	for_each_pci_dev(p) {

		if (pci_resource_start(p, 0) == 0x1f0)
			*primary = 1;
		if (pci_resource_start(p, 2) == 0x170)
			*secondary = 1;

		/* Cyrix CS55{1,2}0 pre SFF MWDMA ATA on the bridge */
		if (p->vendor == PCI_VENDOR_ID_CYRIX &&
		    (p->device == PCI_DEVICE_ID_CYRIX_5510 ||
		     p->device == PCI_DEVICE_ID_CYRIX_5520))
			*primary = *secondary = 1;

		/* Intel MPIIX - PIO ATA on non PCI side of bridge */
		if (p->vendor == PCI_VENDOR_ID_INTEL &&
		    p->device == PCI_DEVICE_ID_INTEL_82371MX) {

			pci_read_config_word(p, 0x6C, &val);
			if (val & 0x8000) {
				/* ATA port enabled */
				if (val & 0x4000)
					*secondary = 1;
				else
					*primary = 1;
			}
		}
	}
}

static int __init ide_generic_init(void)
{
	hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
	unsigned long io_addr;
	int i, rc = 0, primary = 0, secondary = 0;

	ide_generic_check_pci_legacy_iobases(&primary, &secondary);

	if (!probe_mask) {
		printk(KERN_INFO DRV_NAME ": please use \"probe_mask=0x3f\" "
		     "module parameter for probing all legacy ISA IDE ports\n");

		if (primary == 0)
			probe_mask |= 0x1;

		if (secondary == 0)
			probe_mask |= 0x2;
	} else
		printk(KERN_INFO DRV_NAME ": enforcing probing of I/O ports "
			"upon user request\n");

	for (i = 0; i < ARRAY_SIZE(legacy_bases); i++) {
		io_addr = legacy_bases[i];

		if ((probe_mask & (1 << i)) && io_addr) {
			if (!request_region(io_addr, 8, DRV_NAME)) {
				printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX "
						"not free.\n",
						DRV_NAME, io_addr, io_addr + 7);
				continue;
			}

			if (!request_region(io_addr + 0x206, 1, DRV_NAME)) {
				printk(KERN_ERR "%s: I/O resource 0x%lX "
						"not free.\n",
						DRV_NAME, io_addr + 0x206);
				release_region(io_addr, 8);
				continue;
			}

			memset(&hw, 0, sizeof(hw));
			ide_std_init_ports(&hw, io_addr, io_addr + 0x206);
#ifdef CONFIG_IA64
			hw.irq = isa_irq_to_vector(legacy_irqs[i]);
#else
			hw.irq = legacy_irqs[i];
#endif
			hw.chipset = ide_generic;

			rc = ide_host_add(NULL, hws, NULL);
			if (rc) {
				release_region(io_addr + 0x206, 1);
				release_region(io_addr, 8);
			}
		}
	}

	if (ide_generic_sysfs_init())
		printk(KERN_ERR DRV_NAME ": failed to create ide_generic "
					 "class\n");

	return rc;
}

module_init(ide_generic_init);

MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* generic/default IDE host driver
	3	*
f0298512	4	* Copyright (C) 2004, 2008 Bartlomiej Zolnierkiewicz
1da177e4 LT	5	* This code was split off from ide.c. See it for original copyrights.
	6	*
	7	* May be copied or modified under the terms of the GNU General Public License.
	8	*/
	9
f0298512 BZ	10	/*
	11	* For special cases new interfaces may be added using sysfs, i.e.
	12	*
	13	* echo -n "0x168:0x36e:10" > /sys/class/ide_generic/add
	14	*
	15	* will add an interface using I/O ports 0x168-0x16f/0x36e and IRQ 10.
	16	*/
	17
1da177e4 LT	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/module.h>
	21	#include <linux/ide.h>
20df429d	22	#include <linux/pci_ids.h>
1da177e4	23
f01d35d8 BZ	24	/* FIXME: convert m32r to use ide_platform host driver */
	25	#ifdef CONFIG_M32R
	26	#include <asm/m32r.h>
	27	#endif
	28
f0298512 BZ	29	#define DRV_NAME "ide_generic"
f0298512 BZ	30
20df429d	31	static int probe_mask;
0cbccbc3 BZ	32	module_param(probe_mask, int, 0);
	33	MODULE_PARM_DESC(probe_mask, "probe mask for legacy ISA IDE ports");
	34
f0298512 BZ	35	static ssize_t store_add(struct class cls, const char buf, size_t n)
f0298512 BZ	36	{
f0298512	37	unsigned int base, ctl;
6f904d01	38	int irq, rc;
c97c6aca	39	hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
f0298512 BZ	40
	41	if (sscanf(buf, "%x:%x:%d", &base, &ctl, &irq) != 3)
	42	return -EINVAL;
	43
f0298512 BZ	44	memset(&hw, 0, sizeof(hw));
	45	ide_std_init_ports(&hw, base, ctl);
	46	hw.irq = irq;
	47	hw.chipset = ide_generic;
	48
6f904d01 BZ	49	rc = ide_host_add(NULL, hws, NULL);
	50	if (rc)
	51	return rc;
f0298512 BZ	52
	53	return n;
	54	};
	55
	56	static struct class_attribute ide_generic_class_attrs[] = {
	57	__ATTR(add, S_IWUSR, NULL, store_add),
	58	__ATTR_NULL
	59	};
	60
	61	static void ide_generic_class_release(struct class *cls)
	62	{
	63	kfree(cls);
	64	}
	65
	66	static int __init ide_generic_sysfs_init(void)
	67	{
	68	struct class *cls;
	69	int rc;
	70
	71	cls = kzalloc(sizeof(*cls), GFP_KERNEL);
	72	if (!cls)
	73	return -ENOMEM;
	74
	75	cls->name = DRV_NAME;
	76	cls->owner = THIS_MODULE;
	77	cls->class_release = ide_generic_class_release;
	78	cls->class_attrs = ide_generic_class_attrs;
	79
	80	rc = class_register(cls);
	81	if (rc) {
	82	kfree(cls);
	83	return rc;
	84	}
	85
	86	return 0;
	87	}
	88
f01d35d8 BZ	89	#if defined(CONFIG_PLAT_M32700UT) \|\| defined(CONFIG_PLAT_MAPPI2) \
	90	\|\| defined(CONFIG_PLAT_OPSPUT)
	91	static const u16 legacy_bases[] = { 0x1f0 };
	92	static const int legacy_irqs[] = { PLD_IRQ_CFIREQ };
	93	#elif defined(CONFIG_PLAT_MAPPI3)
	94	static const u16 legacy_bases[] = { 0x1f0, 0x170 };
	95	static const int legacy_irqs[] = { PLD_IRQ_CFIREQ, PLD_IRQ_IDEIREQ };
	96	#elif defined(CONFIG_ALPHA)
	97	static const u16 legacy_bases[] = { 0x1f0, 0x170, 0x1e8, 0x168 };
	98	static const int legacy_irqs[] = { 14, 15, 11, 10 };
	99	#else
	100	static const u16 legacy_bases[] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
	101	static const int legacy_irqs[] = { 14, 15, 11, 10, 8, 12 };
	102	#endif
	103
20df429d BP	104	static void ide_generic_check_pci_legacy_iobases(int primary, int secondary)
	105	{
	106	struct pci_dev *p = NULL;
	107	u16 val;
	108
	109	for_each_pci_dev(p) {
	110
	111	if (pci_resource_start(p, 0) == 0x1f0)
	112	*primary = 1;
	113	if (pci_resource_start(p, 2) == 0x170)
	114	*secondary = 1;
	115
	116	/* Cyrix CS55{1,2}0 pre SFF MWDMA ATA on the bridge */
	117	if (p->vendor == PCI_VENDOR_ID_CYRIX &&
	118	(p->device == PCI_DEVICE_ID_CYRIX_5510 \|\|
	119	p->device == PCI_DEVICE_ID_CYRIX_5520))
	120	primary = secondary = 1;
	121
	122	/* Intel MPIIX - PIO ATA on non PCI side of bridge */
	123	if (p->vendor == PCI_VENDOR_ID_INTEL &&
	124	p->device == PCI_DEVICE_ID_INTEL_82371MX) {
	125
	126	pci_read_config_word(p, 0x6C, &val);
	127	if (val & 0x8000) {
	128	/* ATA port enabled */
	129	if (val & 0x4000)
	130	*secondary = 1;
	131	else
	132	*primary = 1;
	133	}
	134	}
	135	}
	136	}
	137
1da177e4 LT	138	static int __init ide_generic_init(void)
1da177e4 LT	139	{
6ccc6d7e	140	hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
8a69580e	141	unsigned long io_addr;
6ccc6d7e	142	int i, rc = 0, primary = 0, secondary = 0;
151575e4	143
20df429d BP	144	ide_generic_check_pci_legacy_iobases(&primary, &secondary);
	145
	146	if (!probe_mask) {
	147	printk(KERN_INFO DRV_NAME ": please use \"probe_mask=0x3f\" "
	148	"module parameter for probing all legacy ISA IDE ports\n");
	149
	150	if (primary == 0)
	151	probe_mask \|= 0x1;
	152
	153	if (secondary == 0)
	154	probe_mask \|= 0x2;
	155	} else
	156	printk(KERN_INFO DRV_NAME ": enforcing probing of I/O ports "
	157	"upon user request\n");
0cbccbc3	158
f01d35d8 BZ	159	for (i = 0; i < ARRAY_SIZE(legacy_bases); i++) {
f01d35d8 BZ	160	io_addr = legacy_bases[i];
486c92e2	161
0cbccbc3	162	if ((probe_mask & (1 << i)) && io_addr) {
16649498 BZ	163	if (!request_region(io_addr, 8, DRV_NAME)) {
	164	printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX "
	165	"not free.\n",
	166	DRV_NAME, io_addr, io_addr + 7);
	167	continue;
	168	}
	169
	170	if (!request_region(io_addr + 0x206, 1, DRV_NAME)) {
	171	printk(KERN_ERR "%s: I/O resource 0x%lX "
	172	"not free.\n",
	173	DRV_NAME, io_addr + 0x206);
	174	release_region(io_addr, 8);
	175	continue;
	176	}
	177
6ccc6d7e BZ	178	memset(&hw, 0, sizeof(hw));
6ccc6d7e BZ	179	ide_std_init_ports(&hw, io_addr, io_addr + 0x206);
f01d35d8	180	#ifdef CONFIG_IA64
6ccc6d7e	181	hw.irq = isa_irq_to_vector(legacy_irqs[i]);
f01d35d8	182	#else
6ccc6d7e	183	hw.irq = legacy_irqs[i];
f01d35d8	184	#endif
6ccc6d7e	185	hw.chipset = ide_generic;
b2a53bc6	186
6ccc6d7e BZ	187	rc = ide_host_add(NULL, hws, NULL);
	188	if (rc) {
	189	release_region(io_addr + 0x206, 1);
	190	release_region(io_addr, 8);
	191	}
16649498	192	}
b2a53bc6	193	}
151575e4	194
f0298512 BZ	195	if (ide_generic_sysfs_init())
	196	printk(KERN_ERR DRV_NAME ": failed to create ide_generic "
	197	"class\n");
	198
8a69580e	199	return rc;
1da177e4 LT	200	}
	201
	202	module_init(ide_generic_init);
	203
	204	MODULE_LICENSE("GPL");