[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / cmd64x.c

/*
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998		Eddie C. Dost  (ecd@skynet.be)
 * Copyright (C) 1998		David S. Miller (davem@redhat.com)
 *
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2007-2010	Bartlomiej Zolnierkiewicz
 * Copyright (C) 2007,2009	MontaVista Software, Inc. <source@mvista.com>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "cmd64x"

/*
 * CMD64x specific registers definition.
 */
#define CFR		0x50
#define   CFR_INTR_CH0		0x04

#define	CMDTIM		0x52
#define	ARTTIM0		0x53
#define	DRWTIM0		0x54
#define ARTTIM1 	0x55
#define DRWTIM1		0x56
#define ARTTIM23	0x57
#define   ARTTIM23_DIS_RA2	0x04
#define   ARTTIM23_DIS_RA3	0x08
#define   ARTTIM23_INTR_CH1	0x10
#define DRWTIM2		0x58
#define BRST		0x59
#define DRWTIM3		0x5b

#define BMIDECR0	0x70
#define MRDMODE		0x71
#define   MRDMODE_INTR_CH0	0x04
#define   MRDMODE_INTR_CH1	0x08
#define UDIDETCR0	0x73
#define DTPR0		0x74
#define BMIDECR1	0x78
#define BMIDECSR	0x79
#define UDIDETCR1	0x7B
#define DTPR1		0x7C

static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
	const unsigned long T = 1000000 / bus_speed;
	static const u8 recovery_values[] =
		{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
	static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
	static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
	static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
	struct ide_timing t;
	u8 arttim = 0;

	ide_timing_compute(drive, mode, &t, T, 0);

	/*
	 * In case we've got too long recovery phase, try to lengthen
	 * the active phase
	 */
	if (t.recover > 16) {
		t.active += t.recover - 16;
		t.recover = 16;
	}
	if (t.active > 16)		/* shouldn't actually happen... */
		t.active = 16;

	/*
	 * Convert values to internal chipset representation
	 */
	t.recover = recovery_values[t.recover];
	t.active &= 0x0f;

	/* Program the active/recovery counts into the DRWTIM register */
	pci_write_config_byte(dev, drwtim_regs[drive->dn],
			      (t.active << 4) | t.recover);

	if (mode >= XFER_SW_DMA_0)
		return;

	/*
	 * The primary channel has individual address setup timing registers
	 * for each drive and the hardware selects the slowest timing itself.
	 * The secondary channel has one common register and we have to select
	 * the slowest address setup timing ourselves.
	 */
	if (hwif->channel) {
		ide_drive_t *pair = ide_get_pair_dev(drive);

		ide_set_drivedata(drive, (void *)(unsigned long)t.setup);

		if (pair)
			t.setup = max_t(u8, t.setup,
					(unsigned long)ide_get_drivedata(pair));
	}

	if (t.setup > 5)		/* shouldn't actually happen... */
		t.setup = 5;

	/*
	 * Program the address setup clocks into the ARTTIM registers.
	 * Avoid clearing the secondary channel's interrupt bit.
	 */
	(void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
	if (hwif->channel)
		arttim &= ~ARTTIM23_INTR_CH1;
	arttim &= ~0xc0;
	arttim |= setup_values[t.setup];
	(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
}

/*
 * Attempts to set drive's PIO mode.
 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
 */

static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	/*
	 * Filter out the prefetch control values
	 * to prevent PIO5 from being programmed
	 */
	if (pio == 8 || pio == 9)
		return;

	cmd64x_program_timings(drive, XFER_PIO_0 + pio);
}

static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 unit			= drive->dn & 0x01;
	u8 regU = 0, pciU	= hwif->channel ? UDIDETCR1 : UDIDETCR0;

	pci_read_config_byte(dev, pciU, &regU);
	regU &= ~(unit ? 0xCA : 0x35);

	switch(speed) {
	case XFER_UDMA_5:
		regU |= unit ? 0x0A : 0x05;
		break;
	case XFER_UDMA_4:
		regU |= unit ? 0x4A : 0x15;
		break;
	case XFER_UDMA_3:
		regU |= unit ? 0x8A : 0x25;
		break;
	case XFER_UDMA_2:
		regU |= unit ? 0x42 : 0x11;
		break;
	case XFER_UDMA_1:
		regU |= unit ? 0x82 : 0x21;
		break;
	case XFER_UDMA_0:
		regU |= unit ? 0xC2 : 0x31;
		break;
	case XFER_MW_DMA_2:
	case XFER_MW_DMA_1:
	case XFER_MW_DMA_0:
		cmd64x_program_timings(drive, speed);
		break;
	}

	pci_write_config_byte(dev, pciU, regU);
}

static void cmd648_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned long base	= pci_resource_start(dev, 4);
	u8  irq_mask		= hwif->channel ? MRDMODE_INTR_CH1 :
						  MRDMODE_INTR_CH0;
	u8  mrdmode		= inb(base + 1);

	/* clear the interrupt bit */
	outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
	     base + 1);
}

static void cmd64x_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= drive->hwif;
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	int irq_reg		= hwif->channel ? ARTTIM23 : CFR;
	u8  irq_mask		= hwif->channel ? ARTTIM23_INTR_CH1 :
						  CFR_INTR_CH0;
	u8  irq_stat		= 0;

	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
	/* clear the interrupt bit */
	(void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
}

static int cmd648_test_irq(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	unsigned long base	= pci_resource_start(dev, 4);
	u8 irq_mask		= hwif->channel ? MRDMODE_INTR_CH1 :
						  MRDMODE_INTR_CH0;
	u8 mrdmode		= inb(base + 1);

	pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
		 hwif->name, mrdmode, irq_mask);

	return (mrdmode & irq_mask) ? 1 : 0;
}

static int cmd64x_test_irq(ide_hwif_t *hwif)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	int irq_reg		= hwif->channel ? ARTTIM23 : CFR;
	u8  irq_mask		= hwif->channel ? ARTTIM23_INTR_CH1 :
						  CFR_INTR_CH0;
	u8  irq_stat		= 0;

	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);

	pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
		 hwif->name, irq_stat, irq_mask);

	return (irq_stat & irq_mask) ? 1 : 0;
}

/*
 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
 * event order for DMA transfers.
 */

static int cmd646_1_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_stat = 0, dma_cmd = 0;

	/* get DMA status */
	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
	/* read DMA command state */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	/* clear the INTR & ERROR bits */
	outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
	/* verify good DMA status */
	return (dma_stat & 7) != 4;
}

static int init_chipset_cmd64x(struct pci_dev *dev)
{
	u8 mrdmode = 0;

	/* Set a good latency timer and cache line size value. */
	(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	/* FIXME: pci_set_master() to ensure a good latency timer value */

	/*
	 * Enable interrupts, select MEMORY READ LINE for reads.
	 *
	 * NOTE: although not mentioned in the PCI0646U specs,
	 * bits 0-1 are write only and won't be read back as
	 * set or not -- PCI0646U2 specs clarify this point.
	 */
	(void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
	mrdmode &= ~0x30;
	(void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));

	return 0;
}

static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev  *dev	= to_pci_dev(hwif->dev);
	u8 bmidecsr = 0, mask	= hwif->channel ? 0x02 : 0x01;

	switch (dev->device) {
	case PCI_DEVICE_ID_CMD_648:
	case PCI_DEVICE_ID_CMD_649:
 		pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
		return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
	default:
		return ATA_CBL_PATA40;
	}
}

static const struct ide_port_ops cmd64x_port_ops = {
	.set_pio_mode		= cmd64x_set_pio_mode,
	.set_dma_mode		= cmd64x_set_dma_mode,
	.clear_irq		= cmd64x_clear_irq,
	.test_irq		= cmd64x_test_irq,
	.cable_detect		= cmd64x_cable_detect,
};

static const struct ide_port_ops cmd648_port_ops = {
	.set_pio_mode		= cmd64x_set_pio_mode,
	.set_dma_mode		= cmd64x_set_dma_mode,
	.clear_irq		= cmd648_clear_irq,
	.test_irq		= cmd648_test_irq,
	.cable_detect		= cmd64x_cable_detect,
};

static const struct ide_dma_ops cmd646_rev1_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= ide_dma_start,
	.dma_end		= cmd646_1_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= ide_dma_sff_read_status,
};

static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
	{	/* 0: CMD643 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
		.port_ops	= &cmd64x_port_ops,
		.host_flags	= IDE_HFLAG_CLEAR_SIMPLEX |
				  IDE_HFLAG_ABUSE_PREFETCH |
				  IDE_HFLAG_SERIALIZE,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= 0x00, /* no udma */
	},
	{	/* 1: CMD646 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH |
				  IDE_HFLAG_SERIALIZE,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA2,
	},
	{	/* 2: CMD648 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA4,
	},
	{	/* 3: CMD649 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_cmd64x,
		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
		.port_ops	= &cmd648_port_ops,
		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH,
		.pio_mask	= ATA_PIO5,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	}
};

static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d;
	u8 idx = id->driver_data;

	d = cmd64x_chipsets[idx];

	if (idx == 1) {
		/*
		 * UltraDMA only supported on PCI646U and PCI646U2, which
		 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
		 * Actually, although the CMD tech support people won't
		 * tell me the details, the 0x03 revision cannot support
		 * UDMA correctly without hardware modifications, and even
		 * then it only works with Quantum disks due to some
		 * hold time assumptions in the 646U part which are fixed
		 * in the 646U2.
		 *
		 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
		 */
		if (dev->revision < 5) {
			d.udma_mask = 0x00;
			/*
			 * The original PCI0646 didn't have the primary
			 * channel enable bit, it appeared starting with
			 * PCI0646U (i.e. revision ID 3).
			 */
			if (dev->revision < 3) {
				d.enablebits[0].reg = 0;
				d.port_ops = &cmd64x_port_ops;
				if (dev->revision == 1)
					d.dma_ops = &cmd646_rev1_dma_ops;
			}
		}
	}

	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id cmd64x_pci_tbl[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);

static struct pci_driver cmd64x_pci_driver = {
	.name		= "CMD64x_IDE",
	.id_table	= cmd64x_pci_tbl,
	.probe		= cmd64x_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init cmd64x_ide_init(void)
{
	return ide_pci_register_driver(&cmd64x_pci_driver);
}

static void __exit cmd64x_ide_exit(void)
{
	pci_unregister_driver(&cmd64x_pci_driver);
}

module_init(cmd64x_ide_init);
module_exit(cmd64x_ide_exit);

MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
60e7a82f	1	/*
1da177e4	2	* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
1da177e4 LT	3	* Due to massive hardware bugs, UltraDMA is only supported
	4	* on the 646U2 and not on the 646U.
	5	*
	6	* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
	7	* Copyright (C) 1998 David S. Miller (davem@redhat.com)
	8	*
	9	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
60349ab9	10	* Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
30e5ffc3	11	* Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	12	*/
1da177e4 LT	13
1da177e4 LT	14	#include <linux/module.h>
	15	#include <linux/types.h>
	16	#include <linux/pci.h>
1da177e4 LT	17	#include <linux/ide.h>
	18	#include <linux/init.h>
	19
	20	#include <asm/io.h>
	21
ced3ec8a BZ	22	#define DRV_NAME "cmd64x"
ced3ec8a BZ	23
1da177e4 LT	24	/*
	25	* CMD64x specific registers definition.
	26	*/
	27	#define CFR 0x50
e51e2528	28	#define CFR_INTR_CH0 0x04
1da177e4 LT	29
	30	#define CMDTIM 0x52
	31	#define ARTTIM0 0x53
	32	#define DRWTIM0 0x54
	33	#define ARTTIM1 0x55
	34	#define DRWTIM1 0x56
	35	#define ARTTIM23 0x57
	36	#define ARTTIM23_DIS_RA2 0x04
	37	#define ARTTIM23_DIS_RA3 0x08
	38	#define ARTTIM23_INTR_CH1 0x10
1da177e4 LT	39	#define DRWTIM2 0x58
	40	#define BRST 0x59
	41	#define DRWTIM3 0x5b
	42
	43	#define BMIDECR0 0x70
	44	#define MRDMODE 0x71
	45	#define MRDMODE_INTR_CH0 0x04
	46	#define MRDMODE_INTR_CH1 0x08
1da177e4 LT	47	#define UDIDETCR0 0x73
	48	#define DTPR0 0x74
	49	#define BMIDECR1 0x78
	50	#define BMIDECSR 0x79
1da177e4 LT	51	#define UDIDETCR1 0x7B
	52	#define DTPR1 0x7C
	53
60349ab9	54	static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
1da177e4	55	{
60349ab9	56	ide_hwif_t *hwif = drive->hwif;
ebae41a5	57	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
60349ab9 BZ	58	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
60349ab9 BZ	59	const unsigned long T = 1000000 / bus_speed;
60e7a82f	60	static const u8 recovery_values[] =
1da177e4	61	{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
60349ab9 BZ	62	static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
60349ab9 BZ	63	static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
60e7a82f	64	static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
60349ab9 BZ	65	struct ide_timing t;
60349ab9 BZ	66	u8 arttim = 0;
60e7a82f	67
60349ab9	68	ide_timing_compute(drive, mode, &t, T, 0);
60e7a82f	69
1da177e4	70	/*
60e7a82f SS	71	* In case we've got too long recovery phase, try to lengthen
60e7a82f SS	72	* the active phase
1da177e4	73	*/
60349ab9 BZ	74	if (t.recover > 16) {
	75	t.active += t.recover - 16;
	76	t.recover = 16;
1da177e4	77	}
60349ab9 BZ	78	if (t.active > 16) /* shouldn't actually happen... */
60349ab9 BZ	79	t.active = 16;
60e7a82f	80
1da177e4 LT	81	/*
	82	* Convert values to internal chipset representation
	83	*/
60349ab9 BZ	84	t.recover = recovery_values[t.recover];
60349ab9 BZ	85	t.active &= 0x0f;
1da177e4	86
60e7a82f	87	/* Program the active/recovery counts into the DRWTIM register */
60349ab9 BZ	88	pci_write_config_byte(dev, drwtim_regs[drive->dn],
60349ab9 BZ	89	(t.active << 4) \| t.recover);
1da177e4	90
60349ab9 BZ	91	if (mode >= XFER_SW_DMA_0)
60349ab9 BZ	92	return;
60e7a82f SS	93
	94	/*
	95	* The primary channel has individual address setup timing registers
	96	* for each drive and the hardware selects the slowest timing itself.
	97	* The secondary channel has one common register and we have to select
	98	* the slowest address setup timing ourselves.
	99	*/
	100	if (hwif->channel) {
5d44a150	101	ide_drive_t *pair = ide_get_pair_dev(drive);
60e7a82f	102
60349ab9	103	ide_set_drivedata(drive, (void *)(unsigned long)t.setup);
5d44a150 BZ	104
5d44a150 BZ	105	if (pair)
60349ab9	106	t.setup = max_t(u8, t.setup,
5bfb151f	107	(unsigned long)ide_get_drivedata(pair));
1da177e4	108	}
1da177e4	109
60349ab9 BZ	110	if (t.setup > 5) /* shouldn't actually happen... */
60349ab9 BZ	111	t.setup = 5;
1da177e4	112
60e7a82f SS	113	/*
	114	* Program the address setup clocks into the ARTTIM registers.
	115	* Avoid clearing the secondary channel's interrupt bit.
	116	*/
	117	(void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
	118	if (hwif->channel)
	119	arttim &= ~ARTTIM23_INTR_CH1;
	120	arttim &= ~0xc0;
60349ab9	121	arttim \|= setup_values[t.setup];
60e7a82f	122	(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
f92d50e6 SS	123	}
	124
	125	/*
	126	* Attempts to set drive's PIO mode.
26bcb879	127	* Special cases are 8: prefetch off, 9: prefetch on (both never worked)
f92d50e6	128	*/
26bcb879 BZ	129
26bcb879 BZ	130	static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
f92d50e6 SS	131	{
	132	/*
	133	* Filter out the prefetch control values
	134	* to prevent PIO5 from being programmed
	135	*/
	136	if (pio == 8 \|\| pio == 9)
	137	return;
	138
60349ab9	139	cmd64x_program_timings(drive, XFER_PIO_0 + pio);
1da177e4 LT	140	}
1da177e4 LT	141
88b2b32b	142	static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4	143	{
898ec223	144	ide_hwif_t *hwif = drive->hwif;
36501650	145	struct pci_dev *dev = to_pci_dev(hwif->dev);
60e7a82f SS	146	u8 unit = drive->dn & 0x01;
60e7a82f SS	147	u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
1da177e4	148
22cabc26 BZ	149	pci_read_config_byte(dev, pciU, &regU);
22cabc26 BZ	150	regU &= ~(unit ? 0xCA : 0x35);
1da177e4 LT	151
1da177e4 LT	152	switch(speed) {
60e7a82f SS	153	case XFER_UDMA_5:
	154	regU \|= unit ? 0x0A : 0x05;
	155	break;
	156	case XFER_UDMA_4:
	157	regU \|= unit ? 0x4A : 0x15;
	158	break;
	159	case XFER_UDMA_3:
	160	regU \|= unit ? 0x8A : 0x25;
	161	break;
	162	case XFER_UDMA_2:
	163	regU \|= unit ? 0x42 : 0x11;
	164	break;
	165	case XFER_UDMA_1:
	166	regU \|= unit ? 0x82 : 0x21;
	167	break;
	168	case XFER_UDMA_0:
	169	regU \|= unit ? 0xC2 : 0x31;
	170	break;
	171	case XFER_MW_DMA_2:
60e7a82f	172	case XFER_MW_DMA_1:
60e7a82f	173	case XFER_MW_DMA_0:
60349ab9	174	cmd64x_program_timings(drive, speed);
60e7a82f	175	break;
1da177e4 LT	176	}
1da177e4 LT	177
22cabc26	178	pci_write_config_byte(dev, pciU, regU);
1da177e4 LT	179	}
1da177e4 LT	180
30e5ffc3	181	static void cmd648_clear_irq(ide_drive_t *drive)
1da177e4	182	{
898ec223	183	ide_hwif_t *hwif = drive->hwif;
30e5ffc3 SS	184	struct pci_dev *dev = to_pci_dev(hwif->dev);
30e5ffc3 SS	185	unsigned long base = pci_resource_start(dev, 4);
66602c83 SS	186	u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
66602c83 SS	187	MRDMODE_INTR_CH0;
1c029fd6	188	u8 mrdmode = inb(base + 1);
66602c83 SS	189
66602c83 SS	190	/* clear the interrupt bit */
6183289c	191	outb((mrdmode & ~(MRDMODE_INTR_CH0 \| MRDMODE_INTR_CH1)) \| irq_mask,
1c029fd6	192	base + 1);
1da177e4 LT	193	}
1da177e4 LT	194
30e5ffc3	195	static void cmd64x_clear_irq(ide_drive_t *drive)
1da177e4	196	{
898ec223	197	ide_hwif_t *hwif = drive->hwif;
36501650	198	struct pci_dev *dev = to_pci_dev(hwif->dev);
66602c83 SS	199	int irq_reg = hwif->channel ? ARTTIM23 : CFR;
	200	u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
	201	CFR_INTR_CH0;
	202	u8 irq_stat = 0;
1da177e4	203
66602c83 SS	204	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
	205	/* clear the interrupt bit */
	206	(void) pci_write_config_byte(dev, irq_reg, irq_stat \| irq_mask);
66602c83 SS	207	}
66602c83 SS	208
628df2f3	209	static int cmd648_test_irq(ide_hwif_t *hwif)
66602c83	210	{
628df2f3 SS	211	struct pci_dev *dev = to_pci_dev(hwif->dev);
628df2f3 SS	212	unsigned long base = pci_resource_start(dev, 4);
66602c83 SS	213	u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
66602c83 SS	214	MRDMODE_INTR_CH0;
1c029fd6	215	u8 mrdmode = inb(base + 1);
66602c83	216
628df2f3 SS	217	pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
628df2f3 SS	218	hwif->name, mrdmode, irq_mask);
66602c83	219
628df2f3	220	return (mrdmode & irq_mask) ? 1 : 0;
1da177e4 LT	221	}
1da177e4 LT	222
628df2f3	223	static int cmd64x_test_irq(ide_hwif_t *hwif)
1da177e4	224	{
36501650	225	struct pci_dev *dev = to_pci_dev(hwif->dev);
66602c83 SS	226	int irq_reg = hwif->channel ? ARTTIM23 : CFR;
	227	u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
	228	CFR_INTR_CH0;
66602c83	229	u8 irq_stat = 0;
e51e2528 SS	230
e51e2528 SS	231	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
1da177e4	232
628df2f3 SS	233	pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
628df2f3 SS	234	hwif->name, irq_stat, irq_mask);
1da177e4	235
628df2f3	236	return (irq_stat & irq_mask) ? 1 : 0;
1da177e4 LT	237	}
	238
	239	/*
	240	* ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
	241	* event order for DMA transfers.
	242	*/
	243
5e37bdc0	244	static int cmd646_1_dma_end(ide_drive_t *drive)
1da177e4	245	{
898ec223	246	ide_hwif_t *hwif = drive->hwif;
1da177e4 LT	247	u8 dma_stat = 0, dma_cmd = 0;
1da177e4 LT	248
1da177e4	249	/* get DMA status */
cab7f8ed	250	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
1da177e4	251	/* read DMA command state */
cab7f8ed	252	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
1da177e4	253	/* stop DMA */
cab7f8ed	254	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
1da177e4	255	/* clear the INTR & ERROR bits */
cab7f8ed	256	outb(dma_stat \| 6, hwif->dma_base + ATA_DMA_STATUS);
1da177e4 LT	257	/* verify good DMA status */
	258	return (dma_stat & 7) != 4;
	259	}
	260
2ed0ef54	261	static int init_chipset_cmd64x(struct pci_dev *dev)
1da177e4	262	{
1da177e4 LT	263	u8 mrdmode = 0;
1da177e4 LT	264
1da177e4 LT	265	/* Set a good latency timer and cache line size value. */
	266	(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	267	/* FIXME: pci_set_master() to ensure a good latency timer value */
	268
83a6d4ab SS	269	/*
	270	* Enable interrupts, select MEMORY READ LINE for reads.
	271	*
	272	* NOTE: although not mentioned in the PCI0646U specs,
	273	* bits 0-1 are write only and won't be read back as
	274	* set or not -- PCI0646U2 specs clarify this point.
1da177e4	275	*/
83a6d4ab SS	276	(void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
	277	mrdmode &= ~0x30;
	278	(void) pci_write_config_byte(dev, MRDMODE, (mrdmode \| 0x02));
1da177e4	279
1da177e4 LT	280	return 0;
	281	}
	282
f454cbe8	283	static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
1da177e4	284	{
36501650	285	struct pci_dev *dev = to_pci_dev(hwif->dev);
83a6d4ab	286	u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
1da177e4	287
83a6d4ab SS	288	switch (dev->device) {
	289	case PCI_DEVICE_ID_CMD_648:
	290	case PCI_DEVICE_ID_CMD_649:
	291	pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
49521f97	292	return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
83a6d4ab	293	default:
49521f97	294	return ATA_CBL_PATA40;
1da177e4	295	}
1da177e4 LT	296	}
1da177e4 LT	297
ac95beed BZ	298	static const struct ide_port_ops cmd64x_port_ops = {
	299	.set_pio_mode = cmd64x_set_pio_mode,
	300	.set_dma_mode = cmd64x_set_dma_mode,
30e5ffc3	301	.clear_irq = cmd64x_clear_irq,
628df2f3	302	.test_irq = cmd64x_test_irq,
30e5ffc3 SS	303	.cable_detect = cmd64x_cable_detect,
	304	};
	305
	306	static const struct ide_port_ops cmd648_port_ops = {
	307	.set_pio_mode = cmd64x_set_pio_mode,
	308	.set_dma_mode = cmd64x_set_dma_mode,
	309	.clear_irq = cmd648_clear_irq,
628df2f3	310	.test_irq = cmd648_test_irq,
ac95beed BZ	311	.cable_detect = cmd64x_cable_detect,
	312	};
	313
f37afdac BZ	314	static const struct ide_dma_ops cmd646_rev1_dma_ops = {
	315	.dma_host_set = ide_dma_host_set,
	316	.dma_setup = ide_dma_setup,
f37afdac	317	.dma_start = ide_dma_start,
5e37bdc0	318	.dma_end = cmd646_1_dma_end,
f37afdac BZ	319	.dma_test_irq = ide_dma_test_irq,
f37afdac BZ	320	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	321	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	322	.dma_sff_read_status = ide_dma_sff_read_status,
5e37bdc0 BZ	323	};
5e37bdc0 BZ	324
85620436	325	static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
ced3ec8a BZ	326	{ /* 0: CMD643 */
ced3ec8a BZ	327	.name = DRV_NAME,
1da177e4	328	.init_chipset = init_chipset_cmd64x,
7accbffd	329	.enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
ac95beed	330	.port_ops = &cmd64x_port_ops,
8ac2b42a	331	.host_flags = IDE_HFLAG_CLEAR_SIMPLEX \|
9bd7496f MP	332	IDE_HFLAG_ABUSE_PREFETCH \|
9bd7496f MP	333	IDE_HFLAG_SERIALIZE,
4099d143	334	.pio_mask = ATA_PIO5,
5f8b6c34	335	.mwdma_mask = ATA_MWDMA2,
18137207	336	.udma_mask = 0x00, /* no udma */
ced3ec8a BZ	337	},
	338	{ /* 1: CMD646 */
	339	.name = DRV_NAME,
1da177e4	340	.init_chipset = init_chipset_cmd64x,
7accbffd	341	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	342	.port_ops = &cmd648_port_ops,
9bd7496f MP	343	.host_flags = IDE_HFLAG_ABUSE_PREFETCH \|
9bd7496f MP	344	IDE_HFLAG_SERIALIZE,
4099d143	345	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	346	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	347	.udma_mask = ATA_UDMA2,
ced3ec8a BZ	348	},
	349	{ /* 2: CMD648 */
	350	.name = DRV_NAME,
1da177e4	351	.init_chipset = init_chipset_cmd64x,
7accbffd	352	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	353	.port_ops = &cmd648_port_ops,
5e71d9c5	354	.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
4099d143	355	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	356	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	357	.udma_mask = ATA_UDMA4,
ced3ec8a BZ	358	},
	359	{ /* 3: CMD649 */
	360	.name = DRV_NAME,
1da177e4	361	.init_chipset = init_chipset_cmd64x,
7accbffd	362	.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
30e5ffc3	363	.port_ops = &cmd648_port_ops,
5e71d9c5	364	.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
4099d143	365	.pio_mask = ATA_PIO5,
5f8b6c34 BZ	366	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	367	.udma_mask = ATA_UDMA5,
1da177e4 LT	368	}
	369	};
	370
	371	static int __devinit cmd64x_init_one(struct pci_dev dev, const struct pci_device_id id)
	372	{
039788e1	373	struct ide_port_info d;
bfd314a3 BZ	374	u8 idx = id->driver_data;
	375
	376	d = cmd64x_chipsets[idx];
	377
5e37bdc0 BZ	378	if (idx == 1) {
	379	/*
	380	* UltraDMA only supported on PCI646U and PCI646U2, which
	381	* correspond to revisions 0x03, 0x05 and 0x07 respectively.
	382	* Actually, although the CMD tech support people won't
	383	* tell me the details, the 0x03 revision cannot support
	384	* UDMA correctly without hardware modifications, and even
	385	* then it only works with Quantum disks due to some
	386	* hold time assumptions in the 646U part which are fixed
	387	* in the 646U2.
	388	*
	389	* So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
	390	*/
	391	if (dev->revision < 5) {
	392	d.udma_mask = 0x00;
	393	/*
	394	* The original PCI0646 didn't have the primary
	395	* channel enable bit, it appeared starting with
	396	* PCI0646U (i.e. revision ID 3).
	397	*/
	398	if (dev->revision < 3) {
	399	d.enablebits[0].reg = 0;
30e5ffc3	400	d.port_ops = &cmd64x_port_ops;
5e37bdc0 BZ	401	if (dev->revision == 1)
5e37bdc0 BZ	402	d.dma_ops = &cmd646_rev1_dma_ops;
5e37bdc0 BZ	403	}
	404	}
	405	}
7accbffd	406
6cdf6eb3	407	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	408	}
1da177e4 LT	409
9cbcc5e3 BZ	410	static const struct pci_device_id cmd64x_pci_tbl[] = {
	411	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	412	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	413	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
	414	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
1da177e4 LT	415	{ 0, },
	416	};
	417	MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
	418
a9ab09e2	419	static struct pci_driver cmd64x_pci_driver = {
1da177e4 LT	420	.name = "CMD64x_IDE",
	421	.id_table = cmd64x_pci_tbl,
	422	.probe = cmd64x_init_one,
e2b15b47	423	.remove = ide_pci_remove,
feb22b7f BZ	424	.suspend = ide_pci_suspend,
feb22b7f BZ	425	.resume = ide_pci_resume,
1da177e4 LT	426	};
1da177e4 LT	427
82ab1eec	428	static int __init cmd64x_ide_init(void)
1da177e4	429	{
a9ab09e2	430	return ide_pci_register_driver(&cmd64x_pci_driver);
1da177e4 LT	431	}
1da177e4 LT	432
e2b15b47 BZ	433	static void __exit cmd64x_ide_exit(void)
e2b15b47 BZ	434	{
a9ab09e2	435	pci_unregister_driver(&cmd64x_pci_driver);
e2b15b47 BZ	436	}
e2b15b47 BZ	437
1da177e4	438	module_init(cmd64x_ide_init);
e2b15b47	439	module_exit(cmd64x_ide_exit);
1da177e4	440
60349ab9	441	MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
1da177e4 LT	442	MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
1da177e4 LT	443	MODULE_LICENSE("GPL");