Commit | Line | Data |
---|---|---|
60e7a82f | 1 | /* |
1da177e4 | 2 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. |
1da177e4 LT |
3 | * Due to massive hardware bugs, UltraDMA is only supported |
4 | * on the 646U2 and not on the 646U. | |
5 | * | |
6 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
7 | * Copyright (C) 1998 David S. Miller (davem@redhat.com) | |
8 | * | |
9 | * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> | |
30e5ffc3 | 10 | * Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com> |
1da177e4 LT |
11 | */ |
12 | ||
1da177e4 LT |
13 | #include <linux/module.h> |
14 | #include <linux/types.h> | |
15 | #include <linux/pci.h> | |
1da177e4 LT |
16 | #include <linux/ide.h> |
17 | #include <linux/init.h> | |
18 | ||
19 | #include <asm/io.h> | |
20 | ||
ced3ec8a BZ |
21 | #define DRV_NAME "cmd64x" |
22 | ||
1da177e4 LT |
23 | #define CMD_DEBUG 0 |
24 | ||
25 | #if CMD_DEBUG | |
26 | #define cmdprintk(x...) printk(x) | |
27 | #else | |
28 | #define cmdprintk(x...) | |
29 | #endif | |
30 | ||
31 | /* | |
32 | * CMD64x specific registers definition. | |
33 | */ | |
34 | #define CFR 0x50 | |
e51e2528 | 35 | #define CFR_INTR_CH0 0x04 |
1da177e4 LT |
36 | |
37 | #define CMDTIM 0x52 | |
38 | #define ARTTIM0 0x53 | |
39 | #define DRWTIM0 0x54 | |
40 | #define ARTTIM1 0x55 | |
41 | #define DRWTIM1 0x56 | |
42 | #define ARTTIM23 0x57 | |
43 | #define ARTTIM23_DIS_RA2 0x04 | |
44 | #define ARTTIM23_DIS_RA3 0x08 | |
45 | #define ARTTIM23_INTR_CH1 0x10 | |
1da177e4 LT |
46 | #define DRWTIM2 0x58 |
47 | #define BRST 0x59 | |
48 | #define DRWTIM3 0x5b | |
49 | ||
50 | #define BMIDECR0 0x70 | |
51 | #define MRDMODE 0x71 | |
52 | #define MRDMODE_INTR_CH0 0x04 | |
53 | #define MRDMODE_INTR_CH1 0x08 | |
1da177e4 LT |
54 | #define UDIDETCR0 0x73 |
55 | #define DTPR0 0x74 | |
56 | #define BMIDECR1 0x78 | |
57 | #define BMIDECSR 0x79 | |
1da177e4 LT |
58 | #define UDIDETCR1 0x7B |
59 | #define DTPR1 0x7C | |
60 | ||
e277a1aa SS |
61 | static u8 quantize_timing(int timing, int quant) |
62 | { | |
63 | return (timing + quant - 1) / quant; | |
64 | } | |
65 | ||
1da177e4 | 66 | /* |
60e7a82f SS |
67 | * This routine calculates active/recovery counts and then writes them into |
68 | * the chipset registers. | |
1da177e4 | 69 | */ |
60e7a82f | 70 | static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time) |
1da177e4 | 71 | { |
ebae41a5 | 72 | struct pci_dev *dev = to_pci_dev(drive->hwif->dev); |
30e5ee4d | 73 | int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33); |
60e7a82f SS |
74 | u8 cycle_count, active_count, recovery_count, drwtim; |
75 | static const u8 recovery_values[] = | |
1da177e4 | 76 | {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0}; |
60e7a82f SS |
77 | static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3}; |
78 | ||
79 | cmdprintk("program_cycle_times parameters: total=%d, active=%d\n", | |
80 | cycle_time, active_time); | |
81 | ||
82 | cycle_count = quantize_timing( cycle_time, clock_time); | |
83 | active_count = quantize_timing(active_time, clock_time); | |
84 | recovery_count = cycle_count - active_count; | |
85 | ||
1da177e4 | 86 | /* |
60e7a82f SS |
87 | * In case we've got too long recovery phase, try to lengthen |
88 | * the active phase | |
1da177e4 | 89 | */ |
60e7a82f SS |
90 | if (recovery_count > 16) { |
91 | active_count += recovery_count - 16; | |
92 | recovery_count = 16; | |
1da177e4 | 93 | } |
60e7a82f SS |
94 | if (active_count > 16) /* shouldn't actually happen... */ |
95 | active_count = 16; | |
96 | ||
97 | cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n", | |
98 | cycle_count, active_count, recovery_count); | |
1da177e4 LT |
99 | |
100 | /* | |
101 | * Convert values to internal chipset representation | |
102 | */ | |
60e7a82f SS |
103 | recovery_count = recovery_values[recovery_count]; |
104 | active_count &= 0x0f; | |
1da177e4 | 105 | |
60e7a82f SS |
106 | /* Program the active/recovery counts into the DRWTIM register */ |
107 | drwtim = (active_count << 4) | recovery_count; | |
108 | (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim); | |
109 | cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]); | |
1da177e4 LT |
110 | } |
111 | ||
112 | /* | |
26bcb879 BZ |
113 | * This routine writes into the chipset registers |
114 | * PIO setup/active/recovery timings. | |
1da177e4 | 115 | */ |
26bcb879 | 116 | static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio) |
1da177e4 | 117 | { |
898ec223 | 118 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 119 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
86a0e12f | 120 | struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); |
5bfb151f | 121 | unsigned long setup_count; |
7dd00083 | 122 | unsigned int cycle_time; |
5bfb151f | 123 | u8 arttim = 0; |
26bcb879 | 124 | |
60e7a82f SS |
125 | static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0}; |
126 | static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23}; | |
7dd00083 | 127 | |
26bcb879 | 128 | cycle_time = ide_pio_cycle_time(drive, pio); |
1da177e4 | 129 | |
86a0e12f | 130 | program_cycle_times(drive, cycle_time, t->active); |
1da177e4 | 131 | |
86a0e12f | 132 | setup_count = quantize_timing(t->setup, |
30e5ee4d | 133 | 1000 / (ide_pci_clk ? ide_pci_clk : 33)); |
60e7a82f SS |
134 | |
135 | /* | |
136 | * The primary channel has individual address setup timing registers | |
137 | * for each drive and the hardware selects the slowest timing itself. | |
138 | * The secondary channel has one common register and we have to select | |
139 | * the slowest address setup timing ourselves. | |
140 | */ | |
141 | if (hwif->channel) { | |
5d44a150 | 142 | ide_drive_t *pair = ide_get_pair_dev(drive); |
60e7a82f | 143 | |
5bfb151f | 144 | ide_set_drivedata(drive, (void *)setup_count); |
5d44a150 BZ |
145 | |
146 | if (pair) | |
5bfb151f JR |
147 | setup_count = max_t(u8, setup_count, |
148 | (unsigned long)ide_get_drivedata(pair)); | |
1da177e4 | 149 | } |
1da177e4 | 150 | |
60e7a82f SS |
151 | if (setup_count > 5) /* shouldn't actually happen... */ |
152 | setup_count = 5; | |
153 | cmdprintk("Final address setup count: %d\n", setup_count); | |
1da177e4 | 154 | |
60e7a82f SS |
155 | /* |
156 | * Program the address setup clocks into the ARTTIM registers. | |
157 | * Avoid clearing the secondary channel's interrupt bit. | |
158 | */ | |
159 | (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim); | |
160 | if (hwif->channel) | |
161 | arttim &= ~ARTTIM23_INTR_CH1; | |
162 | arttim &= ~0xc0; | |
163 | arttim |= setup_values[setup_count]; | |
164 | (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim); | |
165 | cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]); | |
f92d50e6 SS |
166 | } |
167 | ||
168 | /* | |
169 | * Attempts to set drive's PIO mode. | |
26bcb879 | 170 | * Special cases are 8: prefetch off, 9: prefetch on (both never worked) |
f92d50e6 | 171 | */ |
26bcb879 BZ |
172 | |
173 | static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio) | |
f92d50e6 SS |
174 | { |
175 | /* | |
176 | * Filter out the prefetch control values | |
177 | * to prevent PIO5 from being programmed | |
178 | */ | |
179 | if (pio == 8 || pio == 9) | |
180 | return; | |
181 | ||
26bcb879 | 182 | cmd64x_tune_pio(drive, pio); |
1da177e4 LT |
183 | } |
184 | ||
88b2b32b | 185 | static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed) |
1da177e4 | 186 | { |
898ec223 | 187 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 188 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
60e7a82f SS |
189 | u8 unit = drive->dn & 0x01; |
190 | u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0; | |
1da177e4 | 191 | |
f92d50e6 | 192 | if (speed >= XFER_SW_DMA_0) { |
1da177e4 | 193 | (void) pci_read_config_byte(dev, pciU, ®U); |
1da177e4 | 194 | regU &= ~(unit ? 0xCA : 0x35); |
1da177e4 LT |
195 | } |
196 | ||
197 | switch(speed) { | |
60e7a82f SS |
198 | case XFER_UDMA_5: |
199 | regU |= unit ? 0x0A : 0x05; | |
200 | break; | |
201 | case XFER_UDMA_4: | |
202 | regU |= unit ? 0x4A : 0x15; | |
203 | break; | |
204 | case XFER_UDMA_3: | |
205 | regU |= unit ? 0x8A : 0x25; | |
206 | break; | |
207 | case XFER_UDMA_2: | |
208 | regU |= unit ? 0x42 : 0x11; | |
209 | break; | |
210 | case XFER_UDMA_1: | |
211 | regU |= unit ? 0x82 : 0x21; | |
212 | break; | |
213 | case XFER_UDMA_0: | |
214 | regU |= unit ? 0xC2 : 0x31; | |
215 | break; | |
216 | case XFER_MW_DMA_2: | |
217 | program_cycle_times(drive, 120, 70); | |
218 | break; | |
219 | case XFER_MW_DMA_1: | |
220 | program_cycle_times(drive, 150, 80); | |
221 | break; | |
222 | case XFER_MW_DMA_0: | |
223 | program_cycle_times(drive, 480, 215); | |
224 | break; | |
1da177e4 LT |
225 | } |
226 | ||
60e7a82f | 227 | if (speed >= XFER_SW_DMA_0) |
1da177e4 | 228 | (void) pci_write_config_byte(dev, pciU, regU); |
1da177e4 LT |
229 | } |
230 | ||
30e5ffc3 | 231 | static void cmd648_clear_irq(ide_drive_t *drive) |
1da177e4 | 232 | { |
898ec223 | 233 | ide_hwif_t *hwif = drive->hwif; |
30e5ffc3 SS |
234 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
235 | unsigned long base = pci_resource_start(dev, 4); | |
66602c83 SS |
236 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : |
237 | MRDMODE_INTR_CH0; | |
1c029fd6 | 238 | u8 mrdmode = inb(base + 1); |
66602c83 SS |
239 | |
240 | /* clear the interrupt bit */ | |
6183289c | 241 | outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask, |
1c029fd6 | 242 | base + 1); |
1da177e4 LT |
243 | } |
244 | ||
30e5ffc3 | 245 | static void cmd64x_clear_irq(ide_drive_t *drive) |
1da177e4 | 246 | { |
898ec223 | 247 | ide_hwif_t *hwif = drive->hwif; |
36501650 | 248 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
66602c83 SS |
249 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
250 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : | |
251 | CFR_INTR_CH0; | |
252 | u8 irq_stat = 0; | |
1da177e4 | 253 | |
66602c83 SS |
254 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); |
255 | /* clear the interrupt bit */ | |
256 | (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask); | |
66602c83 SS |
257 | } |
258 | ||
628df2f3 | 259 | static int cmd648_test_irq(ide_hwif_t *hwif) |
66602c83 | 260 | { |
628df2f3 SS |
261 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
262 | unsigned long base = pci_resource_start(dev, 4); | |
66602c83 SS |
263 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : |
264 | MRDMODE_INTR_CH0; | |
1c029fd6 | 265 | u8 mrdmode = inb(base + 1); |
66602c83 | 266 | |
628df2f3 SS |
267 | pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n", |
268 | hwif->name, mrdmode, irq_mask); | |
66602c83 | 269 | |
628df2f3 | 270 | return (mrdmode & irq_mask) ? 1 : 0; |
1da177e4 LT |
271 | } |
272 | ||
628df2f3 | 273 | static int cmd64x_test_irq(ide_hwif_t *hwif) |
1da177e4 | 274 | { |
36501650 | 275 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
66602c83 SS |
276 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
277 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : | |
278 | CFR_INTR_CH0; | |
66602c83 | 279 | u8 irq_stat = 0; |
e51e2528 SS |
280 | |
281 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); | |
1da177e4 | 282 | |
628df2f3 SS |
283 | pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n", |
284 | hwif->name, irq_stat, irq_mask); | |
1da177e4 | 285 | |
628df2f3 | 286 | return (irq_stat & irq_mask) ? 1 : 0; |
1da177e4 LT |
287 | } |
288 | ||
289 | /* | |
290 | * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old | |
291 | * event order for DMA transfers. | |
292 | */ | |
293 | ||
5e37bdc0 | 294 | static int cmd646_1_dma_end(ide_drive_t *drive) |
1da177e4 | 295 | { |
898ec223 | 296 | ide_hwif_t *hwif = drive->hwif; |
1da177e4 LT |
297 | u8 dma_stat = 0, dma_cmd = 0; |
298 | ||
1da177e4 | 299 | /* get DMA status */ |
cab7f8ed | 300 | dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); |
1da177e4 | 301 | /* read DMA command state */ |
cab7f8ed | 302 | dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
1da177e4 | 303 | /* stop DMA */ |
cab7f8ed | 304 | outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); |
1da177e4 | 305 | /* clear the INTR & ERROR bits */ |
cab7f8ed | 306 | outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS); |
1da177e4 LT |
307 | /* verify good DMA status */ |
308 | return (dma_stat & 7) != 4; | |
309 | } | |
310 | ||
2ed0ef54 | 311 | static int init_chipset_cmd64x(struct pci_dev *dev) |
1da177e4 | 312 | { |
1da177e4 LT |
313 | u8 mrdmode = 0; |
314 | ||
1da177e4 LT |
315 | /* Set a good latency timer and cache line size value. */ |
316 | (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); | |
317 | /* FIXME: pci_set_master() to ensure a good latency timer value */ | |
318 | ||
83a6d4ab SS |
319 | /* |
320 | * Enable interrupts, select MEMORY READ LINE for reads. | |
321 | * | |
322 | * NOTE: although not mentioned in the PCI0646U specs, | |
323 | * bits 0-1 are write only and won't be read back as | |
324 | * set or not -- PCI0646U2 specs clarify this point. | |
1da177e4 | 325 | */ |
83a6d4ab SS |
326 | (void) pci_read_config_byte (dev, MRDMODE, &mrdmode); |
327 | mrdmode &= ~0x30; | |
328 | (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02)); | |
1da177e4 | 329 | |
1da177e4 LT |
330 | return 0; |
331 | } | |
332 | ||
f454cbe8 | 333 | static u8 cmd64x_cable_detect(ide_hwif_t *hwif) |
1da177e4 | 334 | { |
36501650 | 335 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
83a6d4ab | 336 | u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01; |
1da177e4 | 337 | |
83a6d4ab SS |
338 | switch (dev->device) { |
339 | case PCI_DEVICE_ID_CMD_648: | |
340 | case PCI_DEVICE_ID_CMD_649: | |
341 | pci_read_config_byte(dev, BMIDECSR, &bmidecsr); | |
49521f97 | 342 | return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
83a6d4ab | 343 | default: |
49521f97 | 344 | return ATA_CBL_PATA40; |
1da177e4 | 345 | } |
1da177e4 LT |
346 | } |
347 | ||
ac95beed BZ |
348 | static const struct ide_port_ops cmd64x_port_ops = { |
349 | .set_pio_mode = cmd64x_set_pio_mode, | |
350 | .set_dma_mode = cmd64x_set_dma_mode, | |
30e5ffc3 | 351 | .clear_irq = cmd64x_clear_irq, |
628df2f3 | 352 | .test_irq = cmd64x_test_irq, |
30e5ffc3 SS |
353 | .cable_detect = cmd64x_cable_detect, |
354 | }; | |
355 | ||
356 | static const struct ide_port_ops cmd648_port_ops = { | |
357 | .set_pio_mode = cmd64x_set_pio_mode, | |
358 | .set_dma_mode = cmd64x_set_dma_mode, | |
359 | .clear_irq = cmd648_clear_irq, | |
628df2f3 | 360 | .test_irq = cmd648_test_irq, |
ac95beed BZ |
361 | .cable_detect = cmd64x_cable_detect, |
362 | }; | |
363 | ||
f37afdac BZ |
364 | static const struct ide_dma_ops cmd646_rev1_dma_ops = { |
365 | .dma_host_set = ide_dma_host_set, | |
366 | .dma_setup = ide_dma_setup, | |
f37afdac | 367 | .dma_start = ide_dma_start, |
5e37bdc0 | 368 | .dma_end = cmd646_1_dma_end, |
f37afdac BZ |
369 | .dma_test_irq = ide_dma_test_irq, |
370 | .dma_lost_irq = ide_dma_lost_irq, | |
22117d6e | 371 | .dma_timer_expiry = ide_dma_sff_timer_expiry, |
592b5315 | 372 | .dma_sff_read_status = ide_dma_sff_read_status, |
5e37bdc0 BZ |
373 | }; |
374 | ||
85620436 | 375 | static const struct ide_port_info cmd64x_chipsets[] __devinitdata = { |
ced3ec8a BZ |
376 | { /* 0: CMD643 */ |
377 | .name = DRV_NAME, | |
1da177e4 | 378 | .init_chipset = init_chipset_cmd64x, |
7accbffd | 379 | .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}}, |
ac95beed | 380 | .port_ops = &cmd64x_port_ops, |
8ac2b42a | 381 | .host_flags = IDE_HFLAG_CLEAR_SIMPLEX | |
5e71d9c5 | 382 | IDE_HFLAG_ABUSE_PREFETCH, |
4099d143 | 383 | .pio_mask = ATA_PIO5, |
5f8b6c34 | 384 | .mwdma_mask = ATA_MWDMA2, |
18137207 | 385 | .udma_mask = 0x00, /* no udma */ |
ced3ec8a BZ |
386 | }, |
387 | { /* 1: CMD646 */ | |
388 | .name = DRV_NAME, | |
1da177e4 | 389 | .init_chipset = init_chipset_cmd64x, |
7accbffd | 390 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
30e5ffc3 | 391 | .port_ops = &cmd648_port_ops, |
e01698ae | 392 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH, |
4099d143 | 393 | .pio_mask = ATA_PIO5, |
5f8b6c34 BZ |
394 | .mwdma_mask = ATA_MWDMA2, |
395 | .udma_mask = ATA_UDMA2, | |
ced3ec8a BZ |
396 | }, |
397 | { /* 2: CMD648 */ | |
398 | .name = DRV_NAME, | |
1da177e4 | 399 | .init_chipset = init_chipset_cmd64x, |
7accbffd | 400 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
30e5ffc3 | 401 | .port_ops = &cmd648_port_ops, |
5e71d9c5 | 402 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH, |
4099d143 | 403 | .pio_mask = ATA_PIO5, |
5f8b6c34 BZ |
404 | .mwdma_mask = ATA_MWDMA2, |
405 | .udma_mask = ATA_UDMA4, | |
ced3ec8a BZ |
406 | }, |
407 | { /* 3: CMD649 */ | |
408 | .name = DRV_NAME, | |
1da177e4 | 409 | .init_chipset = init_chipset_cmd64x, |
7accbffd | 410 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
30e5ffc3 | 411 | .port_ops = &cmd648_port_ops, |
5e71d9c5 | 412 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH, |
4099d143 | 413 | .pio_mask = ATA_PIO5, |
5f8b6c34 BZ |
414 | .mwdma_mask = ATA_MWDMA2, |
415 | .udma_mask = ATA_UDMA5, | |
1da177e4 LT |
416 | } |
417 | }; | |
418 | ||
419 | static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
420 | { | |
039788e1 | 421 | struct ide_port_info d; |
bfd314a3 BZ |
422 | u8 idx = id->driver_data; |
423 | ||
424 | d = cmd64x_chipsets[idx]; | |
425 | ||
5e37bdc0 BZ |
426 | if (idx == 1) { |
427 | /* | |
428 | * UltraDMA only supported on PCI646U and PCI646U2, which | |
429 | * correspond to revisions 0x03, 0x05 and 0x07 respectively. | |
430 | * Actually, although the CMD tech support people won't | |
431 | * tell me the details, the 0x03 revision cannot support | |
432 | * UDMA correctly without hardware modifications, and even | |
433 | * then it only works with Quantum disks due to some | |
434 | * hold time assumptions in the 646U part which are fixed | |
435 | * in the 646U2. | |
436 | * | |
437 | * So we only do UltraDMA on revision 0x05 and 0x07 chipsets. | |
438 | */ | |
439 | if (dev->revision < 5) { | |
440 | d.udma_mask = 0x00; | |
441 | /* | |
442 | * The original PCI0646 didn't have the primary | |
443 | * channel enable bit, it appeared starting with | |
444 | * PCI0646U (i.e. revision ID 3). | |
445 | */ | |
446 | if (dev->revision < 3) { | |
447 | d.enablebits[0].reg = 0; | |
30e5ffc3 | 448 | d.port_ops = &cmd64x_port_ops; |
5e37bdc0 BZ |
449 | if (dev->revision == 1) |
450 | d.dma_ops = &cmd646_rev1_dma_ops; | |
5e37bdc0 BZ |
451 | } |
452 | } | |
453 | } | |
7accbffd | 454 | |
6cdf6eb3 | 455 | return ide_pci_init_one(dev, &d, NULL); |
1da177e4 LT |
456 | } |
457 | ||
9cbcc5e3 BZ |
458 | static const struct pci_device_id cmd64x_pci_tbl[] = { |
459 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, | |
460 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, | |
461 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 }, | |
462 | { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 }, | |
1da177e4 LT |
463 | { 0, }, |
464 | }; | |
465 | MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl); | |
466 | ||
a9ab09e2 | 467 | static struct pci_driver cmd64x_pci_driver = { |
1da177e4 LT |
468 | .name = "CMD64x_IDE", |
469 | .id_table = cmd64x_pci_tbl, | |
470 | .probe = cmd64x_init_one, | |
e2b15b47 | 471 | .remove = ide_pci_remove, |
feb22b7f BZ |
472 | .suspend = ide_pci_suspend, |
473 | .resume = ide_pci_resume, | |
1da177e4 LT |
474 | }; |
475 | ||
82ab1eec | 476 | static int __init cmd64x_ide_init(void) |
1da177e4 | 477 | { |
a9ab09e2 | 478 | return ide_pci_register_driver(&cmd64x_pci_driver); |
1da177e4 LT |
479 | } |
480 | ||
e2b15b47 BZ |
481 | static void __exit cmd64x_ide_exit(void) |
482 | { | |
a9ab09e2 | 483 | pci_unregister_driver(&cmd64x_pci_driver); |
e2b15b47 BZ |
484 | } |
485 | ||
1da177e4 | 486 | module_init(cmd64x_ide_init); |
e2b15b47 | 487 | module_exit(cmd64x_ide_exit); |
1da177e4 LT |
488 | |
489 | MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick"); | |
490 | MODULE_DESCRIPTION("PCI driver module for CMD64x IDE"); | |
491 | MODULE_LICENSE("GPL"); |