[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ide / arm / icside.c

/*
 * Copyright (c) 1996-2004 Russell King.
 *
 * Please note that this platform does not support 32-bit IDE IO.
 */

#include <linux/string.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/blkdev.h>
#include <linux/errno.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/scatterlist.h>
#include <linux/io.h>

#include <asm/dma.h>
#include <asm/ecard.h>

#define DRV_NAME "icside"

#define ICS_IDENT_OFFSET		0x2280

#define ICS_ARCIN_V5_INTRSTAT		0x0000
#define ICS_ARCIN_V5_INTROFFSET		0x0004
#define ICS_ARCIN_V5_IDEOFFSET		0x2800
#define ICS_ARCIN_V5_IDEALTOFFSET	0x2b80
#define ICS_ARCIN_V5_IDESTEPPING	6

#define ICS_ARCIN_V6_IDEOFFSET_1	0x2000
#define ICS_ARCIN_V6_INTROFFSET_1	0x2200
#define ICS_ARCIN_V6_INTRSTAT_1		0x2290
#define ICS_ARCIN_V6_IDEALTOFFSET_1	0x2380
#define ICS_ARCIN_V6_IDEOFFSET_2	0x3000
#define ICS_ARCIN_V6_INTROFFSET_2	0x3200
#define ICS_ARCIN_V6_INTRSTAT_2		0x3290
#define ICS_ARCIN_V6_IDEALTOFFSET_2	0x3380
#define ICS_ARCIN_V6_IDESTEPPING	6

struct cardinfo {
	unsigned int dataoffset;
	unsigned int ctrloffset;
	unsigned int stepping;
};

static struct cardinfo icside_cardinfo_v5 = {
	.dataoffset	= ICS_ARCIN_V5_IDEOFFSET,
	.ctrloffset	= ICS_ARCIN_V5_IDEALTOFFSET,
	.stepping	= ICS_ARCIN_V5_IDESTEPPING,
};

static struct cardinfo icside_cardinfo_v6_1 = {
	.dataoffset	= ICS_ARCIN_V6_IDEOFFSET_1,
	.ctrloffset	= ICS_ARCIN_V6_IDEALTOFFSET_1,
	.stepping	= ICS_ARCIN_V6_IDESTEPPING,
};

static struct cardinfo icside_cardinfo_v6_2 = {
	.dataoffset	= ICS_ARCIN_V6_IDEOFFSET_2,
	.ctrloffset	= ICS_ARCIN_V6_IDEALTOFFSET_2,
	.stepping	= ICS_ARCIN_V6_IDESTEPPING,
};

struct icside_state {
	unsigned int channel;
	unsigned int enabled;
	void __iomem *irq_port;
	void __iomem *ioc_base;
	unsigned int sel;
	unsigned int type;
	struct ide_host *host;
};

#define ICS_TYPE_A3IN	0
#define ICS_TYPE_A3USER	1
#define ICS_TYPE_V6	3
#define ICS_TYPE_V5	15
#define ICS_TYPE_NOTYPE	((unsigned int)-1)

/* ---------------- Version 5 PCB Support Functions --------------------- */
/* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;

	writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}

/* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;

	readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}

static const expansioncard_ops_t icside_ops_arcin_v5 = {
	.irqenable	= icside_irqenable_arcin_v5,
	.irqdisable	= icside_irqdisable_arcin_v5,
};


/* ---------------- Version 6 PCB Support Functions --------------------- */
/* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;
	void __iomem *base = state->irq_port;

	state->enabled = 1;

	switch (state->channel) {
	case 0:
		writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
		readb(base + ICS_ARCIN_V6_INTROFFSET_2);
		break;
	case 1:
		writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
		readb(base + ICS_ARCIN_V6_INTROFFSET_1);
		break;
	}
}

/* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
	struct icside_state *state = ec->irq_data;

	state->enabled = 0;

	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
}

/* Prototype: icside_irqprobe(struct expansion_card *ec)
 * Purpose  : detect an active interrupt from card
 */
static int icside_irqpending_arcin_v6(struct expansion_card *ec)
{
	struct icside_state *state = ec->irq_data;

	return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
	       readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
}

static const expansioncard_ops_t icside_ops_arcin_v6 = {
	.irqenable	= icside_irqenable_arcin_v6,
	.irqdisable	= icside_irqdisable_arcin_v6,
	.irqpending	= icside_irqpending_arcin_v6,
};

/*
 * Handle routing of interrupts.  This is called before
 * we write the command to the drive.
 */
static void icside_maskproc(ide_drive_t *drive, int mask)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct expansion_card *ec = ECARD_DEV(hwif->dev);
	struct icside_state *state = ecard_get_drvdata(ec);
	unsigned long flags;

	local_irq_save(flags);

	state->channel = hwif->channel;

	if (state->enabled && !mask) {
		switch (hwif->channel) {
		case 0:
			writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
			readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
			break;
		case 1:
			writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
			readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
			break;
		}
	} else {
		readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
		readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	}

	local_irq_restore(flags);
}

static const struct ide_port_ops icside_v6_no_dma_port_ops = {
	.maskproc		= icside_maskproc,
};

#ifdef CONFIG_BLK_DEV_IDEDMA_ICS
/*
 * SG-DMA support.
 *
 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 * There is only one DMA controller per card, which means that only
 * one drive can be accessed at one time.  NOTE! We do not enforce that
 * here, but we rely on the main IDE driver spotting that both
 * interfaces use the same IRQ, which should guarantee this.
 */

/*
 * Configure the IOMD to give the appropriate timings for the transfer
 * mode being requested.  We take the advice of the ATA standards, and
 * calculate the cycle time based on the transfer mode, and the EIDE
 * MW DMA specs that the drive provides in the IDENTIFY command.
 *
 * We have the following IOMD DMA modes to choose from:
 *
 *	Type	Active		Recovery	Cycle
 *	A	250 (250)	312 (550)	562 (800)
 *	B	187		250		437
 *	C	125 (125)	125 (375)	250 (500)
 *	D	62		125		187
 *
 * (figures in brackets are actual measured timings)
 *
 * However, we also need to take care of the read/write active and
 * recovery timings:
 *
 *			Read	Write
 *  	Mode	Active	-- Recovery --	Cycle	IOMD type
 *	MW0	215	50	215	480	A
 *	MW1	80	50	50	150	C
 *	MW2	70	25	25	120	C
 */
static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
{
	int cycle_time, use_dma_info = 0;

	switch (xfer_mode) {
	case XFER_MW_DMA_2:
		cycle_time = 250;
		use_dma_info = 1;
		break;

	case XFER_MW_DMA_1:
		cycle_time = 250;
		use_dma_info = 1;
		break;

	case XFER_MW_DMA_0:
		cycle_time = 480;
		break;

	case XFER_SW_DMA_2:
	case XFER_SW_DMA_1:
	case XFER_SW_DMA_0:
		cycle_time = 480;
		break;
	}

	/*
	 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
	 * take care to note the values in the ID...
	 */
	if (use_dma_info && drive->id->eide_dma_time > cycle_time)
		cycle_time = drive->id->eide_dma_time;

	drive->drive_data = cycle_time;

	printk("%s: %s selected (peak %dMB/s)\n", drive->name,
		ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
}

static const struct ide_port_ops icside_v6_port_ops = {
	.set_dma_mode		= icside_set_dma_mode,
	.maskproc		= icside_maskproc,
};

static void icside_dma_host_set(ide_drive_t *drive, int on)
{
}

static int icside_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct expansion_card *ec = ECARD_DEV(hwif->dev);

	drive->waiting_for_dma = 0;

	disable_dma(ec->dma);

	/* Teardown mappings after DMA has completed. */
	ide_destroy_dmatable(drive);

	return get_dma_residue(ec->dma) != 0;
}

static void icside_dma_start(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct expansion_card *ec = ECARD_DEV(hwif->dev);

	/* We can not enable DMA on both channels simultaneously. */
	BUG_ON(dma_channel_active(ec->dma));
	enable_dma(ec->dma);
}

static int icside_dma_setup(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct expansion_card *ec = ECARD_DEV(hwif->dev);
	struct icside_state *state = ecard_get_drvdata(ec);
	struct request *rq = hwif->hwgroup->rq;
	unsigned int dma_mode;

	if (rq_data_dir(rq))
		dma_mode = DMA_MODE_WRITE;
	else
		dma_mode = DMA_MODE_READ;

	/*
	 * We can not enable DMA on both channels.
	 */
	BUG_ON(dma_channel_active(ec->dma));

	hwif->sg_nents = ide_build_sglist(drive, rq);

	/*
	 * Ensure that we have the right interrupt routed.
	 */
	icside_maskproc(drive, 0);

	/*
	 * Route the DMA signals to the correct interface.
	 */
	writeb(state->sel | hwif->channel, state->ioc_base);

	/*
	 * Select the correct timing for this drive.
	 */
	set_dma_speed(ec->dma, drive->drive_data);

	/*
	 * Tell the DMA engine about the SG table and
	 * data direction.
	 */
	set_dma_sg(ec->dma, hwif->sg_table, hwif->sg_nents);
	set_dma_mode(ec->dma, dma_mode);

	drive->waiting_for_dma = 1;

	return 0;
}

static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
{
	/* issue cmd to drive */
	ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
}

static int icside_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct expansion_card *ec = ECARD_DEV(hwif->dev);
	struct icside_state *state = ecard_get_drvdata(ec);

	return readb(state->irq_port +
		     (hwif->channel ?
			ICS_ARCIN_V6_INTRSTAT_2 :
			ICS_ARCIN_V6_INTRSTAT_1)) & 1;
}

static void icside_dma_timeout(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;

	printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);

	if (icside_dma_test_irq(drive))
		return;

	ide_dump_status(drive, "DMA timeout", hwif->tp_ops->read_status(hwif));

	icside_dma_end(drive);
}

static void icside_dma_lost_irq(ide_drive_t *drive)
{
	printk(KERN_ERR "%s: IRQ lost\n", drive->name);
}

static int icside_dma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
{
	hwif->dmatable_cpu	= NULL;
	hwif->dmatable_dma	= 0;

	return 0;
}

static const struct ide_dma_ops icside_v6_dma_ops = {
	.dma_host_set		= icside_dma_host_set,
	.dma_setup		= icside_dma_setup,
	.dma_exec_cmd		= icside_dma_exec_cmd,
	.dma_start		= icside_dma_start,
	.dma_end		= icside_dma_end,
	.dma_test_irq		= icside_dma_test_irq,
	.dma_timeout		= icside_dma_timeout,
	.dma_lost_irq		= icside_dma_lost_irq,
};
#else
#define icside_v6_dma_ops NULL
#endif

static int icside_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *d)
{
	return -EOPNOTSUPP;
}

static void icside_setup_ports(hw_regs_t *hw, void __iomem *base,
			       struct cardinfo *info, struct expansion_card *ec)
{
	unsigned long port = (unsigned long)base + info->dataoffset;

	hw->io_ports.data_addr	 = port;
	hw->io_ports.error_addr	 = port + (1 << info->stepping);
	hw->io_ports.nsect_addr	 = port + (2 << info->stepping);
	hw->io_ports.lbal_addr	 = port + (3 << info->stepping);
	hw->io_ports.lbam_addr	 = port + (4 << info->stepping);
	hw->io_ports.lbah_addr	 = port + (5 << info->stepping);
	hw->io_ports.device_addr = port + (6 << info->stepping);
	hw->io_ports.status_addr = port + (7 << info->stepping);
	hw->io_ports.ctl_addr	 = (unsigned long)base + info->ctrloffset;

	hw->irq = ec->irq;
	hw->dev = &ec->dev;
	hw->chipset = ide_acorn;
}

static int __init
icside_register_v5(struct icside_state *state, struct expansion_card *ec)
{
	void __iomem *base;
	struct ide_host *host;
	hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
	int ret;

	base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
	if (!base)
		return -ENOMEM;

	state->irq_port = base;

	ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
	ec->irqmask  = 1;

	ecard_setirq(ec, &icside_ops_arcin_v5, state);

	/*
	 * Be on the safe side - disable interrupts
	 */
	icside_irqdisable_arcin_v5(ec, 0);

	icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec);

	host = ide_host_alloc(NULL, hws);
	if (host == NULL)
		return -ENODEV;

	state->host = host;

	ecard_set_drvdata(ec, state);

	ret = ide_host_register(host, NULL, hws);
	if (ret)
		goto err_free;

	return 0;
err_free:
	ide_host_free(host);
	ecard_set_drvdata(ec, NULL);
	return ret;
}

static const struct ide_port_info icside_v6_port_info __initdata = {
	.init_dma		= icside_dma_off_init,
	.port_ops		= &icside_v6_no_dma_port_ops,
	.dma_ops		= &icside_v6_dma_ops,
	.host_flags		= IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
	.mwdma_mask		= ATA_MWDMA2,
	.swdma_mask		= ATA_SWDMA2,
};

static int __init
icside_register_v6(struct icside_state *state, struct expansion_card *ec)
{
	void __iomem *ioc_base, *easi_base;
	struct ide_host *host;
	unsigned int sel = 0;
	int ret;
	hw_regs_t hw[2], *hws[] = { &hw[0], NULL, NULL, NULL };
	struct ide_port_info d = icside_v6_port_info;

	ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	if (!ioc_base) {
		ret = -ENOMEM;
		goto out;
	}

	easi_base = ioc_base;

	if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
		easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
		if (!easi_base) {
			ret = -ENOMEM;
			goto out;
		}

		/*
		 * Enable access to the EASI region.
		 */
		sel = 1 << 5;
	}

	writeb(sel, ioc_base);

	ecard_setirq(ec, &icside_ops_arcin_v6, state);

	state->irq_port   = easi_base;
	state->ioc_base   = ioc_base;
	state->sel	  = sel;

	/*
	 * Be on the safe side - disable interrupts
	 */
	icside_irqdisable_arcin_v6(ec, 0);

	icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec);
	icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec);

	host = ide_host_alloc(&d, hws);
	if (host == NULL)
		return -ENODEV;

	state->host = host;

	ecard_set_drvdata(ec, state);

	if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
		d.init_dma = icside_dma_init;
		d.port_ops = &icside_v6_port_ops;
		d.dma_ops = NULL;
	}

	ret = ide_host_register(host, NULL, hws);
	if (ret)
		goto err_free;

	return 0;
err_free:
	ide_host_free(host);
	if (d.dma_ops)
		free_dma(ec->dma);
	ecard_set_drvdata(ec, NULL);
out:
	return ret;
}

static int __devinit
icside_probe(struct expansion_card *ec, const struct ecard_id *id)
{
	struct icside_state *state;
	void __iomem *idmem;
	int ret;

	ret = ecard_request_resources(ec);
	if (ret)
		goto out;

	state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
	if (!state) {
		ret = -ENOMEM;
		goto release;
	}

	state->type	= ICS_TYPE_NOTYPE;

	idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	if (idmem) {
		unsigned int type;

		type = readb(idmem + ICS_IDENT_OFFSET) & 1;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
		ecardm_iounmap(ec, idmem);

		state->type = type;
	}

	switch (state->type) {
	case ICS_TYPE_A3IN:
		dev_warn(&ec->dev, "A3IN unsupported\n");
		ret = -ENODEV;
		break;

	case ICS_TYPE_A3USER:
		dev_warn(&ec->dev, "A3USER unsupported\n");
		ret = -ENODEV;
		break;

	case ICS_TYPE_V5:
		ret = icside_register_v5(state, ec);
		break;

	case ICS_TYPE_V6:
		ret = icside_register_v6(state, ec);
		break;

	default:
		dev_warn(&ec->dev, "unknown interface type\n");
		ret = -ENODEV;
		break;
	}

	if (ret == 0)
		goto out;

	kfree(state);
 release:
	ecard_release_resources(ec);
 out:
	return ret;
}

static void __devexit icside_remove(struct expansion_card *ec)
{
	struct icside_state *state = ecard_get_drvdata(ec);

	switch (state->type) {
	case ICS_TYPE_V5:
		/* FIXME: tell IDE to stop using the interface */

		/* Disable interrupts */
		icside_irqdisable_arcin_v5(ec, 0);
		break;

	case ICS_TYPE_V6:
		/* FIXME: tell IDE to stop using the interface */
		if (ec->dma != NO_DMA)
			free_dma(ec->dma);

		/* Disable interrupts */
		icside_irqdisable_arcin_v6(ec, 0);

		/* Reset the ROM pointer/EASI selection */
		writeb(0, state->ioc_base);
		break;
	}

	ecard_set_drvdata(ec, NULL);

	kfree(state);
	ecard_release_resources(ec);
}

static void icside_shutdown(struct expansion_card *ec)
{
	struct icside_state *state = ecard_get_drvdata(ec);
	unsigned long flags;

	/*
	 * Disable interrupts from this card.  We need to do
	 * this before disabling EASI since we may be accessing
	 * this register via that region.
	 */
	local_irq_save(flags);
	ec->ops->irqdisable(ec, 0);
	local_irq_restore(flags);

	/*
	 * Reset the ROM pointer so that we can read the ROM
	 * after a soft reboot.  This also disables access to
	 * the IDE taskfile via the EASI region.
	 */
	if (state->ioc_base)
		writeb(0, state->ioc_base);
}

static const struct ecard_id icside_ids[] = {
	{ MANU_ICS,  PROD_ICS_IDE  },
	{ MANU_ICS2, PROD_ICS2_IDE },
	{ 0xffff, 0xffff }
};

static struct ecard_driver icside_driver = {
	.probe		= icside_probe,
	.remove		= __devexit_p(icside_remove),
	.shutdown	= icside_shutdown,
	.id_table	= icside_ids,
	.drv = {
		.name	= "icside",
	},
};

static int __init icside_init(void)
{
	return ecard_register_driver(&icside_driver);
}

MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("ICS IDE driver");

module_init(icside_init);
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (c) 1996-2004 Russell King.
	3	*
	4	* Please note that this platform does not support 32-bit IDE IO.
	5	*/
	6
1da177e4 LT	7	#include <linux/string.h>
	8	#include <linux/module.h>
	9	#include <linux/ioport.h>
	10	#include <linux/slab.h>
	11	#include <linux/blkdev.h>
	12	#include <linux/errno.h>
	13	#include <linux/hdreg.h>
	14	#include <linux/ide.h>
	15	#include <linux/dma-mapping.h>
	16	#include <linux/device.h>
	17	#include <linux/init.h>
	18	#include <linux/scatterlist.h>
ba5b55d0	19	#include <linux/io.h>
1da177e4 LT	20
	21	#include <asm/dma.h>
	22	#include <asm/ecard.h>
1da177e4	23
67717e22 BZ	24	#define DRV_NAME "icside"
67717e22 BZ	25
1da177e4 LT	26	#define ICS_IDENT_OFFSET 0x2280
	27
	28	#define ICS_ARCIN_V5_INTRSTAT 0x0000
	29	#define ICS_ARCIN_V5_INTROFFSET 0x0004
	30	#define ICS_ARCIN_V5_IDEOFFSET 0x2800
	31	#define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
	32	#define ICS_ARCIN_V5_IDESTEPPING 6
	33
	34	#define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
	35	#define ICS_ARCIN_V6_INTROFFSET_1 0x2200
	36	#define ICS_ARCIN_V6_INTRSTAT_1 0x2290
	37	#define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
	38	#define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
	39	#define ICS_ARCIN_V6_INTROFFSET_2 0x3200
	40	#define ICS_ARCIN_V6_INTRSTAT_2 0x3290
	41	#define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
	42	#define ICS_ARCIN_V6_IDESTEPPING 6
	43
	44	struct cardinfo {
	45	unsigned int dataoffset;
	46	unsigned int ctrloffset;
	47	unsigned int stepping;
	48	};
	49
	50	static struct cardinfo icside_cardinfo_v5 = {
	51	.dataoffset = ICS_ARCIN_V5_IDEOFFSET,
	52	.ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET,
	53	.stepping = ICS_ARCIN_V5_IDESTEPPING,
	54	};
	55
	56	static struct cardinfo icside_cardinfo_v6_1 = {
	57	.dataoffset = ICS_ARCIN_V6_IDEOFFSET_1,
	58	.ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1,
	59	.stepping = ICS_ARCIN_V6_IDESTEPPING,
	60	};
	61
	62	static struct cardinfo icside_cardinfo_v6_2 = {
	63	.dataoffset = ICS_ARCIN_V6_IDEOFFSET_2,
	64	.ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2,
	65	.stepping = ICS_ARCIN_V6_IDESTEPPING,
	66	};
	67
	68	struct icside_state {
	69	unsigned int channel;
	70	unsigned int enabled;
	71	void __iomem *irq_port;
	72	void __iomem *ioc_base;
26839f09	73	unsigned int sel;
1da177e4	74	unsigned int type;
48c3c107	75	struct ide_host *host;
1da177e4 LT	76	};
	77
	78	#define ICS_TYPE_A3IN 0
	79	#define ICS_TYPE_A3USER 1
	80	#define ICS_TYPE_V6 3
	81	#define ICS_TYPE_V5 15
	82	#define ICS_TYPE_NOTYPE ((unsigned int)-1)
	83
	84	/* ---------------- Version 5 PCB Support Functions --------------------- */
	85	/* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
	86	* Purpose : enable interrupts from card
	87	*/
	88	static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
	89	{
	90	struct icside_state *state = ec->irq_data;
	91
	92	writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
	93	}
	94
	95	/* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
	96	* Purpose : disable interrupts from card
	97	*/
	98	static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
	99	{
	100	struct icside_state *state = ec->irq_data;
	101
	102	readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
	103	}
	104
	105	static const expansioncard_ops_t icside_ops_arcin_v5 = {
	106	.irqenable = icside_irqenable_arcin_v5,
	107	.irqdisable = icside_irqdisable_arcin_v5,
	108	};
	109
	110
	111	/* ---------------- Version 6 PCB Support Functions --------------------- */
	112	/* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
	113	* Purpose : enable interrupts from card
	114	*/
	115	static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
	116	{
	117	struct icside_state *state = ec->irq_data;
	118	void __iomem *base = state->irq_port;
	119
	120	state->enabled = 1;
	121
	122	switch (state->channel) {
	123	case 0:
	124	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
	125	readb(base + ICS_ARCIN_V6_INTROFFSET_2);
	126	break;
	127	case 1:
	128	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
	129	readb(base + ICS_ARCIN_V6_INTROFFSET_1);
	130	break;
	131	}
	132	}
	133
	134	/* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
	135	* Purpose : disable interrupts from card
	136	*/
	137	static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
	138	{
	139	struct icside_state *state = ec->irq_data;
140
141	state->enabled = 0;
142
143	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
144	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
145	}
146
147	/* Prototype: icside_irqprobe(struct expansion_card *ec)
148	* Purpose : detect an active interrupt from card
149	*/
150	static int icside_irqpending_arcin_v6(struct expansion_card *ec)
151	{
152	struct icside_state *state = ec->irq_data;
153
154	return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 \|\|
155	readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
156	}
157
158	static const expansioncard_ops_t icside_ops_arcin_v6 = {
159	.irqenable = icside_irqenable_arcin_v6,
160	.irqdisable = icside_irqdisable_arcin_v6,
161	.irqpending = icside_irqpending_arcin_v6,
162	};
163
164	/*
165	* Handle routing of interrupts. This is called before
166	* we write the command to the drive.
167	*/
168	static void icside_maskproc(ide_drive_t *drive, int mask)
169	{
170	ide_hwif_t *hwif = HWIF(drive);
26839f09 BZ	171	struct expansion_card *ec = ECARD_DEV(hwif->dev);
26839f09 BZ	172	struct icside_state *state = ecard_get_drvdata(ec);
1da177e4 LT	173	unsigned long flags;
	174
	175	local_irq_save(flags);
	176
	177	state->channel = hwif->channel;
	178
	179	if (state->enabled && !mask) {
	180	switch (hwif->channel) {
	181	case 0:
	182	writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	183	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
	184	break;
	185	case 1:
	186	writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
	187	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	188	break;
	189	}
	190	} else {
	191	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
	192	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	193	}
	194
	195	local_irq_restore(flags);
	196	}
	197
ac95beed BZ	198	static const struct ide_port_ops icside_v6_no_dma_port_ops = {
	199	.maskproc = icside_maskproc,
	200	};
	201
1da177e4	202	#ifdef CONFIG_BLK_DEV_IDEDMA_ICS
1da177e4 LT	203	/*
	204	* SG-DMA support.
	205	*
	206	* Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
	207	* There is only one DMA controller per card, which means that only
	208	* one drive can be accessed at one time. NOTE! We do not enforce that
	209	* here, but we rely on the main IDE driver spotting that both
	210	* interfaces use the same IRQ, which should guarantee this.
	211	*/
	212
1da177e4 LT	213	/*
	214	* Configure the IOMD to give the appropriate timings for the transfer
	215	* mode being requested. We take the advice of the ATA standards, and
	216	* calculate the cycle time based on the transfer mode, and the EIDE
	217	* MW DMA specs that the drive provides in the IDENTIFY command.
	218	*
	219	* We have the following IOMD DMA modes to choose from:
	220	*
	221	* Type Active Recovery Cycle
	222	* A 250 (250) 312 (550) 562 (800)
	223	* B 187 250 437
	224	* C 125 (125) 125 (375) 250 (500)
	225	* D 62 125 187
	226	*
	227	* (figures in brackets are actual measured timings)
	228	*
	229	* However, we also need to take care of the read/write active and
	230	* recovery timings:
	231	*
	232	* Read Write
	233	* Mode Active -- Recovery -- Cycle IOMD type
	234	* MW0 215 50 215 480 A
	235	* MW1 80 50 50 150 C
	236	* MW2 70 25 25 120 C
	237	*/
88b2b32b	238	static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
1da177e4	239	{
f44ae58a	240	int cycle_time, use_dma_info = 0;
1da177e4	241
1da177e4 LT	242	switch (xfer_mode) {
	243	case XFER_MW_DMA_2:
	244	cycle_time = 250;
	245	use_dma_info = 1;
	246	break;
	247
	248	case XFER_MW_DMA_1:
	249	cycle_time = 250;
	250	use_dma_info = 1;
	251	break;
	252
	253	case XFER_MW_DMA_0:
	254	cycle_time = 480;
	255	break;
	256
	257	case XFER_SW_DMA_2:
	258	case XFER_SW_DMA_1:
	259	case XFER_SW_DMA_0:
	260	cycle_time = 480;
	261	break;
	262	}
	263
	264	/*
	265	* If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
	266	* take care to note the values in the ID...
	267	*/
	268	if (use_dma_info && drive->id->eide_dma_time > cycle_time)
	269	cycle_time = drive->id->eide_dma_time;
	270
	271	drive->drive_data = cycle_time;
	272
1da177e4 LT	273	printk("%s: %s selected (peak %dMB/s)\n", drive->name,
1da177e4 LT	274	ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
1da177e4 LT	275	}
1da177e4 LT	276
ac95beed BZ	277	static const struct ide_port_ops icside_v6_port_ops = {
	278	.set_dma_mode = icside_set_dma_mode,
	279	.maskproc = icside_maskproc,
	280	};
	281
15ce926a	282	static void icside_dma_host_set(ide_drive_t *drive, int on)
1da177e4	283	{
1da177e4 LT	284	}
1da177e4 LT	285
1da177e4 LT	286	static int icside_dma_end(ide_drive_t *drive)
	287	{
	288	ide_hwif_t *hwif = HWIF(drive);
f8341c1c	289	struct expansion_card *ec = ECARD_DEV(hwif->dev);
1da177e4 LT	290
	291	drive->waiting_for_dma = 0;
	292
f8341c1c	293	disable_dma(ec->dma);
1da177e4 LT	294
1da177e4 LT	295	/* Teardown mappings after DMA has completed. */
062f9f02	296	ide_destroy_dmatable(drive);
1da177e4	297
f8341c1c	298	return get_dma_residue(ec->dma) != 0;
1da177e4 LT	299	}
	300
	301	static void icside_dma_start(ide_drive_t *drive)
	302	{
	303	ide_hwif_t *hwif = HWIF(drive);
f8341c1c	304	struct expansion_card *ec = ECARD_DEV(hwif->dev);
1da177e4 LT	305
1da177e4 LT	306	/* We can not enable DMA on both channels simultaneously. */
f8341c1c BZ	307	BUG_ON(dma_channel_active(ec->dma));
f8341c1c BZ	308	enable_dma(ec->dma);
1da177e4 LT	309	}
	310
	311	static int icside_dma_setup(ide_drive_t *drive)
	312	{
	313	ide_hwif_t *hwif = HWIF(drive);
f8341c1c	314	struct expansion_card *ec = ECARD_DEV(hwif->dev);
26839f09	315	struct icside_state *state = ecard_get_drvdata(ec);
1da177e4 LT	316	struct request *rq = hwif->hwgroup->rq;
	317	unsigned int dma_mode;
	318
	319	if (rq_data_dir(rq))
	320	dma_mode = DMA_MODE_WRITE;
	321	else
	322	dma_mode = DMA_MODE_READ;
	323
	324	/*
	325	* We can not enable DMA on both channels.
	326	*/
f8341c1c	327	BUG_ON(dma_channel_active(ec->dma));
1da177e4	328
062f9f02	329	hwif->sg_nents = ide_build_sglist(drive, rq);
1da177e4 LT	330
	331	/*
	332	* Ensure that we have the right interrupt routed.
	333	*/
	334	icside_maskproc(drive, 0);
	335
	336	/*
	337	* Route the DMA signals to the correct interface.
	338	*/
26839f09	339	writeb(state->sel \| hwif->channel, state->ioc_base);
1da177e4 LT	340
	341	/*
	342	* Select the correct timing for this drive.
	343	*/
f8341c1c	344	set_dma_speed(ec->dma, drive->drive_data);
1da177e4 LT	345
	346	/*
	347	* Tell the DMA engine about the SG table and
	348	* data direction.
	349	*/
f8341c1c BZ	350	set_dma_sg(ec->dma, hwif->sg_table, hwif->sg_nents);
f8341c1c BZ	351	set_dma_mode(ec->dma, dma_mode);
1da177e4 LT	352
	353	drive->waiting_for_dma = 1;
	354
	355	return 0;
	356	}
	357
	358	static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
	359	{
	360	/* issue cmd to drive */
	361	ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
	362	}
	363
	364	static int icside_dma_test_irq(ide_drive_t *drive)
	365	{
	366	ide_hwif_t *hwif = HWIF(drive);
26839f09 BZ	367	struct expansion_card *ec = ECARD_DEV(hwif->dev);
26839f09 BZ	368	struct icside_state *state = ecard_get_drvdata(ec);
1da177e4 LT	369
	370	return readb(state->irq_port +
	371	(hwif->channel ?
	372	ICS_ARCIN_V6_INTRSTAT_2 :
	373	ICS_ARCIN_V6_INTRSTAT_1)) & 1;
	374	}
	375
c283f5db	376	static void icside_dma_timeout(ide_drive_t *drive)
1da177e4	377	{
b73c7ee2 BZ	378	ide_hwif_t *hwif = drive->hwif;
b73c7ee2 BZ	379
1da177e4 LT	380	printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
	381
	382	if (icside_dma_test_irq(drive))
c283f5db	383	return;
1da177e4	384
374e042c	385	ide_dump_status(drive, "DMA timeout", hwif->tp_ops->read_status(hwif));
1da177e4	386
c283f5db	387	icside_dma_end(drive);
1da177e4 LT	388	}
1da177e4 LT	389
841d2a9b	390	static void icside_dma_lost_irq(ide_drive_t *drive)
1da177e4 LT	391	{
1da177e4 LT	392	printk(KERN_ERR "%s: IRQ lost\n", drive->name);
1da177e4 LT	393	}
1da177e4 LT	394
91432f48	395	static int icside_dma_init(ide_hwif_t hwif, const struct ide_port_info d)
1da177e4	396	{
1da177e4 LT	397	hwif->dmatable_cpu = NULL;
1da177e4 LT	398	hwif->dmatable_dma = 0;
1da177e4	399
91432f48	400	return 0;
1da177e4	401	}
5e37bdc0	402
f37afdac	403	static const struct ide_dma_ops icside_v6_dma_ops = {
5e37bdc0 BZ	404	.dma_host_set = icside_dma_host_set,
	405	.dma_setup = icside_dma_setup,
	406	.dma_exec_cmd = icside_dma_exec_cmd,
	407	.dma_start = icside_dma_start,
	408	.dma_end = icside_dma_end,
	409	.dma_test_irq = icside_dma_test_irq,
	410	.dma_timeout = icside_dma_timeout,
	411	.dma_lost_irq = icside_dma_lost_irq,
	412	};
	413	#else
	414	#define icside_v6_dma_ops NULL
1da177e4 LT	415	#endif
1da177e4 LT	416
91432f48 BZ	417	static int icside_dma_off_init(ide_hwif_t hwif, const struct ide_port_info d)
	418	{
	419	return -EOPNOTSUPP;
	420	}
	421
b25afdf1 BZ	422	static void icside_setup_ports(hw_regs_t hw, void __iomem base,
b25afdf1 BZ	423	struct cardinfo info, struct expansion_card ec)
1da177e4 LT	424	{
1da177e4 LT	425	unsigned long port = (unsigned long)base + info->dataoffset;
1da177e4	426
b25afdf1 BZ	427	hw->io_ports.data_addr = port;
	428	hw->io_ports.error_addr = port + (1 << info->stepping);
	429	hw->io_ports.nsect_addr = port + (2 << info->stepping);
	430	hw->io_ports.lbal_addr = port + (3 << info->stepping);
	431	hw->io_ports.lbam_addr = port + (4 << info->stepping);
	432	hw->io_ports.lbah_addr = port + (5 << info->stepping);
	433	hw->io_ports.device_addr = port + (6 << info->stepping);
	434	hw->io_ports.status_addr = port + (7 << info->stepping);
	435	hw->io_ports.ctl_addr = (unsigned long)base + info->ctrloffset;
	436
	437	hw->irq = ec->irq;
	438	hw->dev = &ec->dev;
	439	hw->chipset = ide_acorn;
1da177e4 LT	440	}
	441
	442	static int __init
	443	icside_register_v5(struct icside_state state, struct expansion_card ec)
	444	{
1da177e4	445	void __iomem *base;
48c3c107	446	struct ide_host *host;
c97c6aca	447	hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
8a69580e	448	int ret;
1da177e4	449
10bdaaa0	450	base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
1da177e4 LT	451	if (!base)
	452	return -ENOMEM;
	453
	454	state->irq_port = base;
	455
	456	ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
	457	ec->irqmask = 1;
c7b87f3d RK	458
c7b87f3d RK	459	ecard_setirq(ec, &icside_ops_arcin_v5, state);
1da177e4 LT	460
	461	/*
	462	* Be on the safe side - disable interrupts
	463	*/
	464	icside_irqdisable_arcin_v5(ec, 0);
	465
b25afdf1 BZ	466	icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec);
b25afdf1 BZ	467
48c3c107 BZ	468	host = ide_host_alloc(NULL, hws);
48c3c107 BZ	469	if (host == NULL)
1da177e4	470	return -ENODEV;
1da177e4	471
48c3c107	472	state->host = host;
1da177e4	473
26839f09 BZ	474	ecard_set_drvdata(ec, state);
26839f09 BZ	475
8a69580e BZ	476	ret = ide_host_register(host, NULL, hws);
	477	if (ret)
	478	goto err_free;
1da177e4 LT	479
1da177e4 LT	480	return 0;
8a69580e BZ	481	err_free:
	482	ide_host_free(host);
	483	ecard_set_drvdata(ec, NULL);
	484	return ret;
1da177e4 LT	485	}
1da177e4 LT	486
c413b9b9	487	static const struct ide_port_info icside_v6_port_info __initdata = {
91432f48	488	.init_dma = icside_dma_off_init,
ac95beed	489	.port_ops = &icside_v6_no_dma_port_ops,
5e37bdc0	490	.dma_ops = &icside_v6_dma_ops,
c5dd43ec	491	.host_flags = IDE_HFLAG_SERIALIZE \| IDE_HFLAG_MMIO,
c413b9b9 BZ	492	.mwdma_mask = ATA_MWDMA2,
	493	.swdma_mask = ATA_SWDMA2,
	494	};
	495
1da177e4 LT	496	static int __init
	497	icside_register_v6(struct icside_state state, struct expansion_card ec)
	498	{
1da177e4	499	void __iomem ioc_base, easi_base;
48c3c107	500	struct ide_host *host;
1da177e4 LT	501	unsigned int sel = 0;
1da177e4 LT	502	int ret;
c97c6aca	503	hw_regs_t hw[2], *hws[] = { &hw[0], NULL, NULL, NULL };
c413b9b9	504	struct ide_port_info d = icside_v6_port_info;
1da177e4	505
10bdaaa0	506	ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
1da177e4 LT	507	if (!ioc_base) {
	508	ret = -ENOMEM;
	509	goto out;
	510	}
	511
	512	easi_base = ioc_base;
	513
	514	if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
10bdaaa0	515	easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
1da177e4 LT	516	if (!easi_base) {
1da177e4 LT	517	ret = -ENOMEM;
10bdaaa0	518	goto out;
1da177e4 LT	519	}
	520
	521	/*
	522	* Enable access to the EASI region.
	523	*/
	524	sel = 1 << 5;
	525	}
	526
	527	writeb(sel, ioc_base);
	528
c7b87f3d	529	ecard_setirq(ec, &icside_ops_arcin_v6, state);
1da177e4 LT	530
	531	state->irq_port = easi_base;
	532	state->ioc_base = ioc_base;
26839f09	533	state->sel = sel;
1da177e4 LT	534
	535	/*
	536	* Be on the safe side - disable interrupts
	537	*/
	538	icside_irqdisable_arcin_v6(ec, 0);
	539
b25afdf1 BZ	540	icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec);
	541	icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec);
	542
48c3c107 BZ	543	host = ide_host_alloc(&d, hws);
48c3c107 BZ	544	if (host == NULL)
b25afdf1	545	return -ENODEV;
1da177e4	546
48c3c107	547	state->host = host;
1da177e4	548
26839f09	549	ecard_set_drvdata(ec, state);
1da177e4	550
67717e22	551	if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
91432f48	552	d.init_dma = icside_dma_init;
9c391bae	553	d.port_ops = &icside_v6_port_ops;
5e37bdc0	554	d.dma_ops = NULL;
91432f48	555	}
1da177e4	556
8a69580e BZ	557	ret = ide_host_register(host, NULL, hws);
	558	if (ret)
	559	goto err_free;
1da177e4 LT	560
1da177e4 LT	561	return 0;
8a69580e BZ	562	err_free:
	563	ide_host_free(host);
	564	if (d.dma_ops)
	565	free_dma(ec->dma);
	566	ecard_set_drvdata(ec, NULL);
	567	out:
1da177e4 LT	568	return ret;
	569	}
	570
	571	static int __devinit
	572	icside_probe(struct expansion_card ec, const struct ecard_id id)
	573	{
	574	struct icside_state *state;
	575	void __iomem *idmem;
	576	int ret;
	577
	578	ret = ecard_request_resources(ec);
	579	if (ret)
	580	goto out;
	581
cc60d8ba	582	state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
1da177e4 LT	583	if (!state) {
	584	ret = -ENOMEM;
	585	goto release;
	586	}
	587
1da177e4	588	state->type = ICS_TYPE_NOTYPE;
1da177e4	589
10bdaaa0	590	idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
1da177e4 LT	591	if (idmem) {
	592	unsigned int type;
	593
	594	type = readb(idmem + ICS_IDENT_OFFSET) & 1;
	595	type \|= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
	596	type \|= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
	597	type \|= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
10bdaaa0	598	ecardm_iounmap(ec, idmem);
1da177e4 LT	599
	600	state->type = type;
	601	}
	602
	603	switch (state->type) {
	604	case ICS_TYPE_A3IN:
	605	dev_warn(&ec->dev, "A3IN unsupported\n");
	606	ret = -ENODEV;
	607	break;
	608
	609	case ICS_TYPE_A3USER:
	610	dev_warn(&ec->dev, "A3USER unsupported\n");
	611	ret = -ENODEV;
	612	break;
	613
	614	case ICS_TYPE_V5:
	615	ret = icside_register_v5(state, ec);
	616	break;
	617
	618	case ICS_TYPE_V6:
	619	ret = icside_register_v6(state, ec);
	620	break;
	621
	622	default:
	623	dev_warn(&ec->dev, "unknown interface type\n");
	624	ret = -ENODEV;
	625	break;
	626	}
	627
26839f09	628	if (ret == 0)
1da177e4	629	goto out;
1da177e4 LT	630
	631	kfree(state);
	632	release:
	633	ecard_release_resources(ec);
	634	out:
	635	return ret;
	636	}
	637
	638	static void __devexit icside_remove(struct expansion_card *ec)
	639	{
	640	struct icside_state *state = ecard_get_drvdata(ec);
	641
	642	switch (state->type) {
	643	case ICS_TYPE_V5:
	644	/* FIXME: tell IDE to stop using the interface */
	645
	646	/* Disable interrupts */
	647	icside_irqdisable_arcin_v5(ec, 0);
	648	break;
	649
	650	case ICS_TYPE_V6:
	651	/* FIXME: tell IDE to stop using the interface */
	652	if (ec->dma != NO_DMA)
	653	free_dma(ec->dma);
	654
	655	/* Disable interrupts */
	656	icside_irqdisable_arcin_v6(ec, 0);
	657
	658	/* Reset the ROM pointer/EASI selection */
	659	writeb(0, state->ioc_base);
	660	break;
	661	}
	662
	663	ecard_set_drvdata(ec, NULL);
1da177e4	664
1da177e4 LT	665	kfree(state);
	666	ecard_release_resources(ec);
	667	}
	668
	669	static void icside_shutdown(struct expansion_card *ec)
	670	{
	671	struct icside_state *state = ecard_get_drvdata(ec);
	672	unsigned long flags;
	673
	674	/*
	675	* Disable interrupts from this card. We need to do
	676	* this before disabling EASI since we may be accessing
	677	* this register via that region.
	678	*/
	679	local_irq_save(flags);
	680	ec->ops->irqdisable(ec, 0);
	681	local_irq_restore(flags);
	682
	683	/*
	684	* Reset the ROM pointer so that we can read the ROM
	685	* after a soft reboot. This also disables access to
	686	* the IDE taskfile via the EASI region.
	687	*/
	688	if (state->ioc_base)
	689	writeb(0, state->ioc_base);
	690	}
	691
	692	static const struct ecard_id icside_ids[] = {
	693	{ MANU_ICS, PROD_ICS_IDE },
	694	{ MANU_ICS2, PROD_ICS2_IDE },
	695	{ 0xffff, 0xffff }
	696	};
	697
	698	static struct ecard_driver icside_driver = {
	699	.probe = icside_probe,
	700	.remove = __devexit_p(icside_remove),
	701	.shutdown = icside_shutdown,
	702	.id_table = icside_ids,
	703	.drv = {
	704	.name = "icside",
	705	},
	706	};
	707
	708	static int __init icside_init(void)
	709	{
	710	return ecard_register_driver(&icside_driver);
	711	}
	712
	713	MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
	714	MODULE_LICENSE("GPL");
	715	MODULE_DESCRIPTION("ICS IDE driver");
	716
	717	module_init(icside_init);